OpenRAM
An Open-Source Memory Compiler
Matthew Guthaus
mrg@ucsc.edu

https://vlsida.github.io/OpenRAM/

Banana Slugs

https://vlsida.github.io/OpenRAM/

Why an Open Source Memory Compiler?
● Memories have become a commodity part...
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but there are none available for “free”.

● Many IP cores are available for “free”...
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but these don’t include necessary memories.

● Memories are a bottleneck for performance and power...
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but their performance and power vary drastically.

● Memories have a regular structure which leads to automation...
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but developing for multiple technologies and tool methodologies is hard.

https://vlsida.github.io/OpenRAM/

Why NOT an Open Source Memory Compiler?
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Bit cells are proprietary from the foundry
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Lithography issues and DRC waivers

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Need to characterize real silicon

Design rules are not accessible
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PDKs are hard to access and not “open”

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It’s a lot of work

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You can just buy memory IP

https://vlsida.github.io/OpenRAM/

Contemporary Compilers and/or IP
Industry compilers:
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Intel rolls their own

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Cadence Legato Memory Solution

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Synopsys DesignWare (acquired Virage Logic)

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ARM Memory IP (acquired Artisan)

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Mobile Semiconductor Trailblaze

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Many others...

2(2𝝅r) is twice as round?

Free options depend on commercial tools and only one technology:
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FabMem (NCSU)

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Potstill ( https://github.com/fabianschuiki/potstill )

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https://vlsida.github.io/OpenRAM/

Optimists vs Pessimists vs Engineers
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An optimist sees the glass as half full.

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A pessimist sees the glass as half empty.

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An engineer asks why the glass is twice as big as it needs to be.

https://vlsida.github.io/OpenRAM/

OpenRAM Guiding Principles
1.

Be “extensible” by hardware engineers

2.

Be “independent” of technology

3.

Be “independent” of specific tools or methodologies

4.

Support multiple memory types and configurations

https://vlsida.github.io/OpenRAM/

OpenRAM Features
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Implemented in Python 3.5+

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Licensed with 3-clause BSD

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Provides reference circuit and physical implementations
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FreePDK45 (generic, non-fabricable 45nm)

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MOSIS Scalable CMOS (scn4m_subm 0.35um)

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Provides a timing/power characterization methodology and functional verification

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Generates GDSII layout data, SPICE netlist, Verilog model, DRC/LVS verification
reports and P&R macro view.

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Wrappers for both open-source and commercial tools

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https://vlsida.github.io/OpenRAM/

OpenRAM SRAM
Architecture
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Bit-cell Array
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Multiport Bitcells

Each port:
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Address Decoder(s)

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Wordline Driver(s)

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Column Multiplexer(s)

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Bitline Precharge(s)

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Sense Amplifier(s)

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Write Driver(s)

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Control Logic with
Replica Bitline

9
https://vlsida.github.io/OpenRAM/

OpenRAM Implementation
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Front-end mode for architects/systems people
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Generates spice, layout views, timing models
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Netlist only mode can skip the physical design too

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Doesn’t perform DRC/LVS

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Estimates power/delay analytically

Back-end mode for circuits/VLSI people
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Generates spice, layout views, timing models

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Performs DRC/LVS
■

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Can perform at each level of hierarchy or at the end

Simulates power/delay
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Can be back-annotated or not
https://vlsida.github.io/OpenRAM/

Configuration Files
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Usage:
$ openram.py myconfig
$ openram.py myconfig.py

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Uses Python instead of
additional language

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Can specify tools when
multiple available

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Can override modules
with custom
implementations

myconfig.py
# Size and technology
tech_name = "scn4m_subm"
word_size = 16
num_words = 256
# Corners are process x supply x temperature
process_corners = ["TT"]
supply_voltages = [ 3.3 ]
temperatures = [ 25 ]
# Output storage
output_path = "/my/results/directory"
output_name = "btb_sram"
# Tools
spice = "ngspice"
drc_name = "magic"
lvs_name = "netgen"
pex_name = "magic"
# Custom logic module
decoder = "mydecoder"

https://vlsida.github.io/OpenRAM/

Data Sheets are a Feature!?

https://vlsida.github.io/OpenRAM/

Unit Tests & DevOps
● Why is testing a “feature”!?
● Uses Python unit test framework
● GitLab runner for code coverage and results
● Tests for...
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guiding users when porting to new technologies.

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allowing users to add features without worrying about breaking functionality.

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functionality, cell verification, timing verification, and technology verification.

https://vlsida.github.io/OpenRAM/

Design Classes
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Spice and layout Interfaces
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Custom cells (read GDS2 and SPICE)

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Generated cells (creates GDS2 and SPICE “on the fly”)

Netlist functions
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Add (directional) pins

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Add and connect instances

Layout functions
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Place instances

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Add wires, routes, vias

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Channel and Power router

Verification functions (wrap around DRC and LVS tools)
https://vlsida.github.io/OpenRAM/

Required Custom Design
● A few library cells with layout and spice:
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Bitcell (and replica bitcell)
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Could be from the foundry

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Sense amplifier

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DFF (from a standard cell library)

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(Removing soon: write driver, tristate)

Standard 6T (1rw)
6.8um x 9.2um

● P&R border layer defined for placement
● Sense amplifier pitch matched width to bitcell

https://vlsida.github.io/OpenRAM/

Parameterized Gates and Transistors
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Needs to be “good enough” since not dominant
portion of area

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Parameterized transistors

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Parameterized logic gates (pinv, pnand2, pnor2,
pnand3)

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Multi-stage drivers

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Precharge

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Column mux

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(Soon: write driver, tristate)

https://vlsida.github.io/OpenRAM/

Hierarchical Modules
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SRAM building blocks
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Bank, Control Logic, Decoders, Column Mux, Various arrays (DFF, drivers)

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Can override every module with a custom one in the configuration file

Each module must:
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Create netlist
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Define inputs/outputs

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Instantiate and connect sub-modules and cells

Create layout
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Place and route itself

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Route vdd/gnd to M3

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(Optional) Run DRC/LVS

Analytically model timing and power
https://vlsida.github.io/OpenRAM/

Tool Portability
● OpenRAM uses a “wrapper” approach for DRC and LVS tools
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Currently supports: Magic+Netgen and some commercial tools
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Wish list: klayout, more commercial tools

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Wish list: open source DRC and extraction?

OpenRAM uses standard spice syntax
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Currently supports: ngspice and some commercial tools
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Wish list: xyce

Multi-threaded support is highly recommended (e.g. ngspice with OpenMP)

https://vlsida.github.io/OpenRAM/

GDSII Result Samples

512 x 16b x 1rw FreePDK45

2048 x 32b x 1rw FreePDK45
https://vlsida.github.io/OpenRAM/

Area Results

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https://vlsida.github.io/OpenRAM/

Area and Timing Results

https://vlsida.github.io/OpenRAM/

Some Features in Progress
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FreePDK15 (15nm FinFET process)
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Creating a pfinfet.py parameterized FinFET class

XFab XH018 (180nm)
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Working on collaboration to tape out memories

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Asynchronous control interface

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Built in Self Test (BIST)

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Error Correcting Codes (ECC)

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https://vlsida.github.io/OpenRAM/

Conclusions
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OpenRAM generates the circuit, functional model, and layout of variable-sized
SRAMs.

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OpenRAM provides a memory characterizer for synthesis timing and power
models.

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OpenRAM is open-sourced, flexible, and portable.

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OpenRAM aims to be independent of specific tools and methodologies.

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We are actively developing new features and improvements.

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We are actively seeking feedback and collaborations (and, of course,
funding!)
https://vlsida.github.io/OpenRAM/

Contributors
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Numerous UCSC Graduate Students
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Bin Wu, Hunter Nichols, Jennifer Sowash, Jesse Cirimelli-Low

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Former Students: Michael Grimes (Achronix), Jeff Butera (Mentor)

Oklahoma State University
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Prof. James Stine

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Dr. Samira Ataei (post-doc at Yale now)

Other Collaboration
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Tim Edwards (eFabless, Open Circuit Design)

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Edmund Humenberger & Others (Symbiotic EDA)

https://vlsida.github.io/OpenRAM/

Questions?
https://github.com/VLSIDA/OpenRAM
Matthew Guthaus
mrg@ucsc.edu

https://vlsida.github.io/OpenRAM/

Channel Router
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SRAMs typically try to use minimal layers of metal
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Primarily used to connect decoders,
input/output circuitry, or control logic

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Wish list
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Minimize number of tracks

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Must consider impact on floorplan
Credit: Chen & Chang, EDA
Handbook, Chapter 12, Global and
detailed routing

Sense amp to data flop connection

https://vlsida.github.io/OpenRAM/

Power Supply Router
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Power pins are brought up to M3 throughout design

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Horizontal/vertical power grid (M3 and M4)

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Blockage-aware

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Uses conservative routing pitch

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Wide metal DRC spacing supported

Multi-pass algorithm
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1st: Route vertical and horizontal grids (blockage aware, allow connection to correct supply)

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2nd: Check direct overlaps of power pins

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3rd: Single direction probes to connect

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4th: A* maze router

https://vlsida.github.io/OpenRAM/

In Progress: OpenRAM Library
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Downloadable IP

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Pre-characterized

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Various sizes and
configs

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Technologies
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SCMOS (scn4m_subm
0.35um)

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FreePDK45 (45nm)

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TODO: More

https://vlsida.github.io/OpenRAMLibrary/
https://vlsida.github.io/OpenRAM/