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The copyright of this thesis vests in the author. No
quotation from it or information derived from it is to be
published without full acknowledgement of the source.
The thesis is to be used for private study or noncommercial research purposes only.
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Published by the University of Cape Town (UCT) in terms
of the non-exclusive license granted to UCT by the author.
RHINO:
R ECONFIGURABLE H ARDWARE I NTERFACE FOR COMPUTATIO N AND RADI O
by
To
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Simon Scott
e
A dissertation submitted to the Department of Electrical Engineering
in fulfilment of the requirements for the degree of
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MS C E LECTRICAL E NGINEERING
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U NIVERSITY OF C APE T OWN
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Supervisors:
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Dr Alan Langman
Prof Michael Inggs
c
⃝University
of Cape Town
March 2011
The financial assistance of the National Research Foundation (NRF) towards this research is hereby acknowledged. Opinions
expressed and conclusions arrived at, are those of the author and are not necessarily to be attributed to the NRF.
Declaration
I declare that this project is my own unaided work; all sources that I have used have been referenced and are
listed in the Bibliography. It is being submitted for the degree of Master of Science in Electrical Engineering
at the University of Cape Town. This work has not been submitted before for any other degree or examination
in any other university.
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Signature of Author: ............................
Cape Town
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28 March 2011
A BSTRACT
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Field-programmable gate arrays, or FPGAs, provide an attractive computing platform for software-defined
radio applications. Their reconfigurable nature allows many digital signal processing (DSP) algorithms to be
highly parallelised within the FPGA fabric, while their customisable I/O interfaces allow simple interfacing
to analogue-to-digital converters (ADCs) and digital-to-analogue converters (DACs). However, FPGA boards
that deliver sufficient performance to be useful in real-world applications are generally expensive. These high
prices act as a barrier to entry to FPGA systems for smaller development teams and research groups.
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In order to overcome this barrier, Rhino was developed. Rhino is an FPGA-based hardware processing platform that primarily supports software-defined radio applications. The goal of Rhino is to aid research and
training in smaller university research groups and development teams with limited budgets. Rhino therefore
aims to provide sufficient performance to be useful, while keeping the costs low.
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The architecture for Rhino was designed so that it would best serve three target applications: radar, radio
astronomy and bioinformatics. The architecture centres around a Xilinx Spartan-6 FPGA connected to an
AM3517 ARM processor via a parallel bus. The FPGA is used for processing computationally-intensive
algorithms, such as DSP operations for radar or matrix calculations for bioinformatics. The processor is used
for coordinating the flow of data in and out of the FPGA, as well as for configuring the FPGA. The FPGA
connects to ADC/DAC daughterboards using industry-standard FMC connectors. The FPGA can stream the
data off the board via two 10Gbps Ethernet links, or buffer it in its 512MB of DDR3 SDRAM. A 1Gbps
Ethernet link is also provided.
The processor runs BORPH, a Linux variant that allows users to communicate with the FPGA via the operating
system’s filesystem. The processor has a 100Mbps Ethernet link that allows users to access the board remotely
and copy files to the processor over the network. The processor is supplied with 256MB of DDR2 SDRAM,
and is able to boot from NAND flash memory, an SD card or from a network server. It also has USB host ports,
a real-time clock and audio and video interfaces. The clocks on multiple Rhino boards can be synchronised
to within 10ns of each other using the Precision Time Protocol, which runs over the Ethernet link. The entire
board is monitored using power and temperature sensors.
The design of the manufactured Rhino board was verified using special test software and gateware. The board
passed all software-based tests, proving that it performs as expected. Unfortunately, the FMC interface could
only be tested at reduced speed, as no high-speed test hardware was available.
The final cost estimate for a complete Rhino system is under $1700, cheaper than similar FPGA boards that
deliver much lower performance.
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ACKNOWLEDGEMENTS
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I would like to express my gratitude to the following people who assisted me during the course of this thesis.
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To
Alan Langman for conceiving the idea of Rhino in the first place, and remaining involved throughout the
duration of the project. I thank you for for always providing me with new ideas, for checking my work at each
stage of the design process, and for the time you have spent organising the logistics of this project. I especially
thank you for the all the stimulating discussions we have had over the past year. It has been a pleasure working
with you.
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Michael Inggs for overseeing the Rhino project and always ensuring that it stayed on track. Thank you also
for all the input you provided during the editing stages of the dissertation. It is much appreciated.
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Everyone who participated in the design reviews and provided such useful feedback. This includes, but is
not limited to, Henry Chen, Matt Dexter, David George, Philip Gibbs, David Hawkins, Francois Kapp,
Pablo Sanchez and Jonathan Weintroub.
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The following organisations for funding this research through various scholarships: the NRF via the Prestigious Masters Scholarship, the CSIR and the Department of Defense via the Project Ledger Scholarship
and the University of Cape Town through the Manuel & Luby Washkansky Scholarship.
U
Lastly, I would like to thank SKA South Africa for sponsoring the electrical components and the manufacturing of the PCBs. Without this funding, Rhino would not have been a reality.
ii
G LOSSARY OF T ERMS
Analogue to Digital Converter: a device that converts a continuous (analogue) signal to a
discrete digital number. An analogue signal must be digitised by an ADC before it can be
processed on an FPGA.
ASIC:
Application-specific Integrated Circuit: an integrated circuit that is designed for a specific
application, rather than for general use.
BGA:
Ball Grid Array: a type of integrated circuit package containing an array of solder balls
affixed to its underside.
DAC:
Digital to Analogue Converter: a device that converts a digital signal into an analogue signal.
It therefore performs the inverse operation of a ADC.
DIMM:
Dual In-line Memory Module: a number of DRAM ICs mounted on a single PCB.
DSP:
Digital Signal Processing involves the representation of signals as sequences of numbers, and
these sequences are processed using mathematical algorithms.
FMC:
FPGA Mezzanine Card: an ANSI standard that defines a standard mezzanine card form factor
and connector interface to an FPGA located on a carrier board.
FPGA:
Field Programmable Gate Array: an integrated circuit consisting of an array of logic cells,
each of which can be programmed to perform a specific logic function.
Gateware:
Gateware is for FPGAs what firmware is for embedded processors. It is the configuration
data that is used to program/configure the FPGA.
HPC:
High Pin Count (for FMC connectors): an FMC connector with 400 pins.
LPC:
Low Pin Count (for FMC connectors): an FMC connector with 160 pins.
LVDS:
Low voltage differential signalling: a standard for representing digital data using two separate
voltage signals.
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ADC:
iii
Printed Circuit Board. Also known as a printed wire board.
PLL:
Phase-Locked Loop. A circuit that generates a clock signal with the same phase as an input
reference signal, but with a frequency that may be a multiple of the reference frequency. Both
the processor and the FPGA on Rhino contain PLLs for generating the correct internal clock
frequencies.
Rhino:
Reconfigurable Hardware Interface for computatioN and radiO. A low-cost FPGA board that
targets software-defined radio, radio astronomy and bioinformatics applications. It is also the
topic of this dissertation.
SDRAM:
Synchronous Dynamic Random Access Memory: a type of RAM that requires regular refreshing (dynamic), and is synchronised to a system clock.
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PCB:
C ONTENTS
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Abstract
Acknowledgements
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To
Glossary of Terms
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Contents
of
List of Tables
Introduction
1.1 The Need for New Computing Architectures . . .
1.2 FPGAs as an Alternative Computing Architecture
1.3 Rhino, a Low-Cost FPGA Board . . . . . . . . .
1.4 Rhino Target Applications . . . . . . . . . . . .
1.4.1 Radar . . . . . . . . . . . . . . . . . . .
1.4.2 Radio Astronomy . . . . . . . . . . . . .
1.4.3 Bioinformatics . . . . . . . . . . . . . .
1.5 Analysis of the Requirements for Rhino . . . . .
1.6 Scope of this Thesis . . . . . . . . . . . . . . . .
1.7 A Note on Nomenclature . . . . . . . . . . . . .
1.8 Structure of the Thesis . . . . . . . . . . . . . .
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List of Figures
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Review of Existing Software-Defined Radio Hardware
2.1 ROACH . . . . . . . . . . . . . . . . . . . . . . .
2.1.1 Hardware Architecture . . . . . . . . . . .
2.1.2 Software Environment . . . . . . . . . . .
2.1.3 Strengths of ROACH . . . . . . . . . . . .
2.1.4 Weaknesses of ROACH . . . . . . . . . .
2.2 USRP N200 and N210 . . . . . . . . . . . . . . .
2.2.1 Hardware Architecture . . . . . . . . . . .
2.2.2 Software Environment . . . . . . . . . . .
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The Architecture of Rhino
3.1 High-level Block Diagram and Detailed Specification for Rhino
3.2 Software Architecture for Rhino . . . . . . . . . . . . . . . . .
3.3 Selection of Major Components . . . . . . . . . . . . . . . . .
3.3.1 Selection of Spartan-6 FPGA . . . . . . . . . . . . . . .
3.3.2 Processor Selection . . . . . . . . . . . . . . . . . . . .
3.3.3 Selection of I/O Connector for ADC and DAC Cards . .
3.3.4 Selection of High-speed Network Interface . . . . . . .
3.3.5 Selection of SDRAM for the FPGA . . . . . . . . . . .
3.3.6 Selection of Flash Memory Technology for the Processor
3.3.7 Comparison of Analogue and Digital Power Supplies . .
3.4 Updated High-level Block Diagram . . . . . . . . . . . . . . .
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Schematic-level Hardware Design of Rhino
4.1 Detailed Hardware Sub-System Description for Rhino . . . . . . . . . . . . . . . . .
4.1.1 FPGA and its Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.2 Processor and its Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.3 Debugging Sub-Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.4 Power Generation and Monitoring Sub-Systems . . . . . . . . . . . . . . . .
4.2 The Rhino Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.1 Cover Page, Table of Contents and Rhino Power Distribution and Monitoring
4.2.2 Rhino Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.3 Spartan-6 (top-level) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.4 Spartan-6 Bank 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.5 Spartan-6 Bank 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.6 Dual LVDS Receiver 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.7 Spartan-6 Bank 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.8 Spartan-6 Bank 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.9 Dual LVDS Receiver 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.10 Spartan-6 Bank 4 and Bank 5 . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.11 Spartan-6 Multi-Gigabit Transceivers . . . . . . . . . . . . . . . . . . . . .
4.2.12 Spartan-6 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.13 Spartan-6 Power and Supply Decoupling Caps . . . . . . . . . . . . . . . .
4.2.14 DDR3 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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2.2.3 Strengths of the USRP N200 Series . . .
2.2.4 Weaknesses of the USRP N200 Series . .
BEE4 . . . . . . . . . . . . . . . . . . . . . . .
2.3.1 Hardware Architecture . . . . . . . . . .
2.3.2 Software Environment . . . . . . . . . .
2.3.3 Strengths of the BEE4 . . . . . . . . . .
2.3.4 Weaknesses of the BEE4 . . . . . . . . .
Xilinx SP605 . . . . . . . . . . . . . . . . . . .
2.4.1 Hardware Architecture . . . . . . . . . .
Outline for a New, Improved, Hardware Platform
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5
Rhino PCB Layout and Routing
5.1 The Theory behind Routing High-Speed Digital Signals
5.1.1 What Happens at High Frequencies? . . . . . .
5.1.2 How can these Problems be Avoided? . . . . .
5.1.3 Calculating Characteristic Impedance . . . . .
5.2 Placement of Major Components . . . . . . . . . . . .
5.3 The PCB Stackup . . . . . . . . . . . . . . . . . . . .
5.4 Defining the Routing Rules for Rhino . . . . . . . . .
5.4.1 Minimum Trace Width . . . . . . . . . . . . .
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e
4.2.15 FMC HPC Connector . . . . . . . . . . . . .
4.2.16 CX4 10Gbps Ethernet Connector . . . . . .
4.2.17 1 Gbps Ethernet PHY . . . . . . . . . . . . .
4.2.18 Spartan-6 GPIO Header and LEDs . . . . . .
4.2.19 Spartan-6 Clocks . . . . . . . . . . . . . . .
4.2.20 AM3517 (top-level) . . . . . . . . . . . . .
4.2.21 AM3517 Peripherals (Part A) . . . . . . . .
4.2.22 AM3517 Peripherals (Part B) . . . . . . . .
4.2.23 AM3517 Power and Supply Decoupling Caps
4.2.24 AM3517 DDR2 RAM (top level) . . . . . .
4.2.25 DDR2 RAM . . . . . . . . . . . . . . . . .
4.2.26 NAND Flash . . . . . . . . . . . . . . . . .
4.2.27 100Mbps Ethernet PHY . . . . . . . . . . .
4.2.28 RS-232 Header for Peripherals . . . . . . . .
4.2.29 AM3517 Clocks . . . . . . . . . . . . . . .
4.2.30 USB On-the-Go . . . . . . . . . . . . . . .
4.2.31 USB Host Transceivers . . . . . . . . . . . .
4.2.32 SD Card and Real-time Clock . . . . . . . .
4.2.33 HDMI Video Transmitter . . . . . . . . . . .
4.2.34 Audio . . . . . . . . . . . . . . . . . . . . .
4.2.35 USB to JTAG/I2 C/RS-232 . . . . . . . . . .
4.2.36 JTAG Chain . . . . . . . . . . . . . . . . . .
4.2.37 Configuration Interface Level Translator . . .
4.2.38 Power Supply Management . . . . . . . . .
4.2.39 Spartan-6 Power Supplies . . . . . . . . . .
4.2.40 Spartan-6 LDO Power Supplies . . . . . . .
4.2.41 FMC Power Supply Switches . . . . . . . .
4.2.42 Si6463BDQ FET Load Switch . . . . . . . .
4.2.43 AM3517 Power Supply . . . . . . . . . . . .
4.2.44 Power Monitors . . . . . . . . . . . . . . . .
4.2.45 Temperature Monitor and Fan Controller . .
4.2.46 Power LEDs . . . . . . . . . . . . . . . . .
4.2.47 Mounting Holes and Fiducials . . . . . . . .
Clocking the Spartan-6 FPGA . . . . . . . . . . . .
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68
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77
Development of Tools for Verification of Hardware Design
6.1 The Rhino Test Rig . . . . . . . . . . . . . . . . . . .
6.2 Processor Bootloader Software . . . . . . . . . . . . .
6.2.1 X-Loader . . . . . . . . . . . . . . . . . . . .
6.2.2 U-Boot . . . . . . . . . . . . . . . . . . . . .
6.3 Configuring the GPMC Bus . . . . . . . . . . . . . . .
6.4 Processor Test Software . . . . . . . . . . . . . . . . .
6.4.1 Application: Rhino LEDs . . . . . . . . . . .
6.4.2 Application: Rhino PSU Enable . . . . . . . .
6.4.3 Application: Rhino FMC Control . . . . . . .
6.4.4 Application: Rhino GPMC Test . . . . . . . .
6.4.5 Application: Rhino RTC Test . . . . . . . . .
6.4.6 Application: Rhino System Monitor . . . . . .
6.5 FPGA Test Gateware . . . . . . . . . . . . . . . . . .
6.5.1 Rhino Blinky . . . . . . . . . . . . . . . . . .
6.5.2 Rhino DDR3 Memory Test . . . . . . . . . . .
6.5.3 Rhino 1GBE Test . . . . . . . . . . . . . . . .
6.5.4 Rhino 10GBE Test . . . . . . . . . . . . . . .
6.5.5 Rhino FMC Test . . . . . . . . . . . . . . . .
6.5.6 Rhino Processor Interface Test . . . . . . . . .
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Results of Hardware Verification
7.1 The Completed Rhino PCBs . . . . . . . . . . . . .
7.2 PCB Manufacturing Test Results . . . . . . . . . . .
7.3 Hardware Bugs and Modifications . . . . . . . . . .
7.4 Results of the Software-based Tests . . . . . . . . .
7.4.1 The Processor and its Peripherals . . . . . .
7.4.2 Spartan-6 FPGA and its User LEDs . . . . .
7.4.3 DDR3 SDRAM . . . . . . . . . . . . . . . .
7.4.4 Processor-FPGA Interface . . . . . . . . . .
7.4.5 CX4 10Gbps Ethernet Ports . . . . . . . . .
7.4.6 1Gbps Ethernet . . . . . . . . . . . . . . . .
7.4.7 FMC Connectors . . . . . . . . . . . . . . .
7.4.8 GPIO Connector . . . . . . . . . . . . . . .
7.4.9 Power Supply and Management Sub-System
7.4.10 Summary of Test Results . . . . . . . . . . .
7.5 Estimated Board Cost . . . . . . . . . . . . . . . . .
U
7
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ap
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To
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5.5
5.4.2 Widths of Power-Carrying Traces
5.4.3 Inter-trace Spacing . . . . . . . .
5.4.4 Trace Length Matching . . . . . .
Verification of PCB Layout and Routing .
5.5.1 3D Models to Check Footprints .
5.5.2 Signal-Integrity Simulations . . .
5.5.3 Full 3D Model of the Rhino PCB
viii
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8
Conclusions and Future Work
8.1 Summary of the Rhino Design Process . . . . . . . . . . . . . . . . . . . . . .
8.2 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3 Future Work for Rhino . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3.1 Manufacture Next Revision of Rhino with the Necessary Modifications
8.3.2 Further Reduce Board Cost . . . . . . . . . . . . . . . . . . . . . . . .
8.3.3 Upgrade to SFP+ Network Connectors . . . . . . . . . . . . . . . . . .
8.3.4 Build the Rhino Hide . . . . . . . . . . . . . . . . . . . . . . . . . . .
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115
A I/O Interface Requirements
116
A.1 I/O Requirements for Radar Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
A.2 I/O Requirements for Radio Astronomy Applications . . . . . . . . . . . . . . . . . . . . . . 117
118
w
n
B Full Rhino Schematics
To
C Layout of the Rhino Hide
D Listing of Files on Attached CD
U
ni
v
er
si
ty
of
C
ap
e
Bibliography
ix
184
185
186
L IST OF F IGURES
Photograph of a ROACH board . . . . . . . . . . . . . . . . . . .
The architecture of ROACH . . . . . . . . . . . . . . . . . . . .
The USRP N210 . . . . . . . . . . . . . . . . . . . . . . . . . .
The USRP2 and USRP N200 series architecture . . . . . . . . . .
The BEE4 FPGA board . . . . . . . . . . . . . . . . . . . . . . .
The architecture of a single FPGA processing cell on the BEE4-W
The Xilinx SP605 development board . . . . . . . . . . . . . . .
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3.1
3.2
Rhino high-level block diagram, indicating performance requirements . . . . . . . . . . . . . 22
Updated Rhino high-level block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.1
4.2
4.3
4.4
4.5
4.6
Sub-system diagram of Rhino . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power generation and management for Rhino . . . . . . . . . . . . . . . . . . . . . . .
An example of Altium’s hierarchical schematic structure . . . . . . . . . . . . . . . . .
The PCB directive for a differential pair . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal routing of GCLKs to BUFGMUXs within the Spartan 6, for Bank 0 and Bank 1
Rhino’s clock sources, and how the connect to the FPGA . . . . . . . . . . . . . . . . .
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5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11
5.12
5.13
5.14
5.15
5.16
The stair-step waveform that occurs if the line impedance is less than the source impedance .
The ringing waveform that occurs if the line impedance is greater than the source impedance
Parameters used when calculating the characteristic impedance of a microstrip . . . . . . . .
Parameters used when calculating the odd-mode impedance of a differential microstrip . . .
Parameters used when calculating the characteristic impedance of a stripline . . . . . . . . .
Parameters used when calculating the odd-mode impedance of a differential stripline . . . .
Diagram showing placement of major components on the Rhino PCB . . . . . . . . . . . .
Stackup of the Rhino PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Definition of the inter-trace dimensions (A, B, C and D) on a PCB . . . . . . . . . . . . . .
3D model of the Fujitsu CX4 connector, as shown from the rear . . . . . . . . . . . . . . .
Signal integrity simulation for net A1 on the DDR2 bus. . . . . . . . . . . . . . . . . . . .
Signal integrity simulation for nets CK P and CK N on the DDR2 bus. . . . . . . . . . . . .
Signal integrity simulation for the DQ2 net on the DDR2 1 bus . . . . . . . . . . . . . . . .
Signal integrity simulation for the DQ8 net on the DDR2 0 bus . . . . . . . . . . . . . . . .
Signal integrity simulation for net A4 on the DDR3 1 bus. . . . . . . . . . . . . . . . . . .
Signal integrity simulation for nets CK P and CK N on the DDR3 1 bus. . . . . . . . . . .
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2.6
2.7
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Signal integrity simulation for the DQ3 net on the DDR3 1 bus . . . . . . .
Signal integrity simulation for the LDQS N and LDQS P nets on the DDR3
Signal integrity simulation for the FMC1 CLK0 M2C single-ended net . .
Signal integrity simulation for the FMC0 LA P/N21 net . . . . . . . . . .
Signal integrity simulation for the FMC0 ZDOK P/N0 net . . . . . . . . .
Signal integrity simulation for the GMII RX CLK trace . . . . . . . . . . .
Signal integrity simulation for the TXD2 signal on the GMII bus . . . . . .
3D model of the complete Rhino PCB . . . . . . . . . . . . . . . . . . . .
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1 bus
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6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
3D model of the Rhino test rig . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Photo of the completed Rhino test rig . . . . . . . . . . . . . . . . . . . . . . . . .
The AM3517 boot process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The GPMC bus in the Rhino schematics . . . . . . . . . . . . . . . . . . . . . . . .
The GPMC read operation, as configured for Rhino . . . . . . . . . . . . . . . . . .
The GPMC write operation, as configured for Rhino . . . . . . . . . . . . . . . . . .
Xilinx XM105 FMC debug card . . . . . . . . . . . . . . . . . . . . . . . . . . . .
State chart for the DDR3 0 memory test . . . . . . . . . . . . . . . . . . . . . . . .
Loopback connections using jumpers on the FMC debug card . . . . . . . . . . . . .
Flowchart describing the flow of logic in the Rhino Processor Interface Test gateware
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7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
7.14
7.15
The completed Rhino PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Another view of the completed Rhino PCB, with annotations . . . . . . . . . . . . . . . . . . 97
X-ray of one of the DDR3 SDRAM ICs on Rhino after production . . . . . . . . . . . . . . . 98
Void analysis of six of the balls on the DDR3 SDRAM IC . . . . . . . . . . . . . . . . . . . . 99
The Rhino test rig being used to power up a board . . . . . . . . . . . . . . . . . . . . . . . . 99
DDR2 SDRAM oscilloscope traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
DDR3 0 SDRAM oscilloscope traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Oscilloscope traces for the processor-FPGA bus, showing signals nADV (top) and D0 (bottom) 105
Windows XP network status when connected to Rhino via CX4 cable . . . . . . . . . . . . . 106
Eye diagrams for the XAUI signals on different length CX4 cables . . . . . . . . . . . . . . . 106
Windows XP network status when connected to Rhino via 1Gbps Ethernet cable . . . . . . . . 107
Oscilloscope plots of the FMC signals during testing . . . . . . . . . . . . . . . . . . . . . . 109
Plot of the voltage readings taken by the Rhino System Monitor . . . . . . . . . . . . . . . . 110
Plot of the current readings taken by the Rhino System Monitor . . . . . . . . . . . . . . . . . 111
Plot of the temperature and fan speed readings taken by the Rhino System Monitor . . . . . . 112
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5.18
5.19
5.20
5.21
5.22
5.23
5.24
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L IST OF TABLES
Requirements for Rhino for Target Applications . . . . . . . . . . . . . . . . . . . . . . . . .
Summary of Rhino Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
Characteristic of the XC6SLX150T Spartan-6 FPGA . . . . . . . . . . . . . . . . .
Spartan-6 XC6SLX150T Package Options . . . . . . . . . . . . . . . . . . . . . . .
FPGA I/O Requirements for Each Peripheral . . . . . . . . . . . . . . . . . . . . .
Texas Instruments ARM Microprocessors . . . . . . . . . . . . . . . . . . . . . . .
Texas Instruments Sitara Microprocessor Family (only devices with Ethernet support)
Feature Set of the AM3517 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The Z-DOK+ Connector Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The FMC LPC Connector Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Comparison of Analogue and Digital Power Supplies for Rhino . . . . . . . . . . . .
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
LED Settings for the Marvell 88E1111 Gigabit Ethernet PHY . . .
FPGA Serial Configuration Interface Signals . . . . . . . . . . . . .
Power Requirements for the FPGA and its Peripherals . . . . . . . .
FMC Mezzanine Card Power Requirements . . . . . . . . . . . . .
Power Requirements for the Processor and its Peripherals . . . . . .
Rhino Power Consumption . . . . . . . . . . . . . . . . . . . . . .
List of Clock Inputs to the Spartan-6 FPGA on Rhino . . . . . . . .
Shared BUFGMUXs for Global Clocks on Banks 0 and 1 on Rhino
Shared BUFGMUXs for Global Clocks on Banks 2 and 3 on Rhino
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5.5
5.6
5.7
5.8
5.9
5.10
Rhino High-Speed Digital Buses . . . . . . . . . . . . . .
Rhino Net Classes for PCB Routing . . . . . . . . . . . .
Signal Integrity Simulation Results for the DDR2 SDRAM
Crosstalk Simulation Results for the DDR2 SDRAM . . .
Signal Integrity Simulation Results for the DDR3 SDRAM
Crosstalk Simulation Results for the DDR3 SDRAM . . .
Signal Integrity Simulation Results for the FMC Signals .
Crosstalk Simulation Results for the FMC Signals . . . . .
Signal Integrity Simulation Results for the GMII Signals .
Crosstalk Simulation Results for the GMII Signals . . . .
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6.1
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Chip Select Regions for the GPMC Bus on Rhino . . . . . . . . . . . . . . . . . . . . . . . . 84
GPMC Control Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Main State Machine for Rhino 1GBE Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
Impedance Measurement Results for the Rhino PCB . . . . . . . . .
Rhino Hardware Design Errors . . . . . . . . . . . . . . . . . . . . .
Status of the FPGA LEDs during the DDR3 SDRAM Test . . . . . .
Status of the FPGA LEDs during the CX4 Test . . . . . . . . . . . .
Status of the FPGA LEDs during the 1Gbps Ethernet Test . . . . . . .
Status of the FPGA LEDs after the FMC Tests . . . . . . . . . . . . .
Comparison of Automated Measurements and Manual Measurements
Estimated System Cost for Rhino . . . . . . . . . . . . . . . . . . . .
8.1
Comparison of the Detailed Rhino Specification and the Manufactured Board . . . . . . . . . 114
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CH A P T E R 1
1.1 T HE N EED FOR N EW C OMPUTING A RCHITECTURES
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I NTRODUCTION
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In the past, computer architects have always viewed increasing the clock frequency as the primary method of
improving processor performance [1]. However, it is now generally accepted that this is no longer possible,
due to what Asanovik et al. call the “power wall” [2]. This refers to the fact that by running microprocessors
at multi-GHz clock speeds, semiconductor manufacturers have now hit the limit of the amount of power that a
single integrated circuit can dissipate. Therefore, instead of trying to increase the clock speed of the processors
further, semiconductor companies are instead improving performance by placing several smaller (and hence
more power efficient) parallel processors on a single die [2].
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Although Moore’s Law (the trend of doubling the number of transistors in a microprocessor every two years)
still holds, computer architects are no longer trying to double the number of transistors in a single microprocessor core. Instead, the new trend is to double the number of cores on a single multiprocessor die every
two years. However, many believe that this approach of doubling the number of cores with each generation
of processors will lead to diminishing returns once eight processors per die are exceeded [1]. Instead, it is
believed that semiconductor companies should rather be designing multiprocessors that contain thousands of
cores per die. This very large number of processors per die will result in both the highest performance (due to
large number of parallel datapaths) and efficiency (as each core can be clocked at slower rate). Furthermore,
the high level of parallelism will force programmers to stop thinking in terms of sequential processing, and
rather write highly parallel software that makes the most efficient use of the computing resources available.
Unfortunately, processors with thousands of cores are probably still many years away. In the meantime,
computer architects are looking at alternative processing devices that are inherently parallel in nature. Two
such processing devices are graphics processors (formally known as graphics processing units, or GPUs) and
field programmable gate arrays (FPGAs). An example of a high-end GPU is the NVIDIA Tesla C2050, which
has 448 parallel processors [3]. Patterson [4] explains that this large number of parallel cores, coupled with
the ease of use of GPUs, makes them an ideal platform on which to run software that is inherently parallel.
GPUs are commonly used for digital signal processing applications (such as image and video processing),
where speed-ups of ten times over traditional sequential CPU implementations are common. For example,
Cope et al. recorded an 18 times throughput increase when using a GPU, instead of a CPU, to do primary
colour correction [5].
The one disadvantage of GPUs is that they have a fixed hardware architecture. It is not possible to increase or
decrease the number of cores as required, nor can one modify the datapath design of each processor to better
suit the application. Furthermore, there is often a bottleneck transferring data in and out of the GPU over the
1
PCI and DRAM buses.
FPGAs, on the other hand, do not experience these shortcomings. They can be completely reconfigured to
support a variable number of cores, and the datapath of each core is completely customisable. In fact, many
manufacturers of embedded computing devices have already moved away from per-product ASIC designs
to FPGA devices, due to “the need to amortize rapidly increasing design costs, the desire to minimize endproduct design risk, and the value in providing flexible platforms” [2].
1.2 FPGA S AS AN A LTERNATIVE C OMPUTING A RCHITECTURE
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A field programmable gate array (FPGA) can be defined as “a chip composed of an array of configurable logic
cells (also called logic blocks). Each cell can be configured, or programmed, to perform one of a variety of
simple functions... FPGA logic cells can be used as building blocks to implement any kind of functionality
desired, from low-complexity state machines to complete microprocessors.” [6]. An FPGA can therefore be
regarded as a piece of programmable hardware, and since hardware is by its very nature parallel, FPGAs are
inherently parallel processing devices. Depending on the application, an FPGA can be programmed to have
one or one thousand parallel processing datapaths.
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It is this reconfigurable parallel nature that makes FPGAs ideal for high-performance computing applications,
such as physics simulations and DNA sequencing (see Yu et al. [7]). FPGA’s also have a simple physical
I/O interface, as each physical pin on the integrated circuit (IC) can be individually programmed to perform a
specific function. This allows FPGA’s to be easily connected to external components, such as memory ICs or
analogue-to-digital converters (ADCs). Since software-defined radio applications are both DSP (digital signal
processing)-intensive and require the use of ADCs and DACs, FPGAs are ideally suited to such applications.
Examples of software-defined radio applications are radar and radio astronomy, where the FPGAs are typically
connected to an analogue-to-digital converter (ADC) and are used to perform filtering and Fourier Transform
operations on the sampled waveform.
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However, there still remain definite barriers that hinder the development of FPGA-based systems. FPGA
boards that deliver reasonable performance are very expensive. Roach, a Virtex 5 board used by the CASPER
radio astronomy community [8], costs approximately $5300, while the USRP N210, the most readily available
FPGA-based system for software-defined radio, costs $1700 [9]. The tools themselves are also very expensive:
the basic development environment that is used for all Xilinx FPGAs (known as Xilinx ISE) costs $2995 per
annum [10], while the MATLAB and Simulink tools required for developing systems for the CASPER boards
cost $52501 [11].
These high prices act as a barrier to entry to FPGA systems for smaller development teams and research groups
with limited budgets. Furthermore, many users of the MATLAB-Simulink environment in the CASPER community have complained about the long processing times when simulating their FPGA design, as well as the
instability of the development environment 2 , while the majority of USRP users never alter the gateware on
the USRP’s FPGA to better meet their application’s needs, due to the steep learning curve involved in FPGA
development.
From all the above mentioned reasons, one can only conclude that there is a clear need for an easy-to-use
FPGA-based system that is low-cost, but still delivers sufficient performance to be useful.
1
Prices were obtained directly from the relevant manufacturers, and were correct as of January 2011.
These remarks regarding the MATLAB-Simulink environment were made numerous times during working-group discussions at
the CASPER 2010 Workshop at the Harvard-Smithsonian Institute in Boston, USA in August 2010.
2
2
1.3 R HINO , A L OW-C OST FPGA B OARD
In order to meet this need, the concept for Rhino was developed. Rhino is an FPGA-based hardware processing
platform that primarily supports software-defined radio applications. The goal of Rhino is to aid research and
training in smaller university research groups and development teams with limited budgets. Rhino therefore
aims to provide sufficient performance to be useful in real-world applications, while keeping the costs low.
The original idea for Rhino was conceived by Dr Alan Langman, a researcher affiliated with the University of
Cape Town. His outline for the project, which shall be called the “customer specification”, stated that:
1. The board must contain both an FPGA and a processor, connected via a parallel bus. The architecture
for the board should follow the style of other CASPER boards (such as Roach [8]), whereby the FPGA
is used for data processing and the processor is used for control.
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3. Both the FPGA and processor must have RAM attached to them.
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2. The FPGA must be the largest Xilinx Spartan-6 available, and the processor must be an Texas Instruments ARM processor.
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4. An I/O interface (for connecting ADCs and DACs) and a high-speed network link (for shipping the data
off the board). must be connected to the FPGA.
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5. The processor must run BORPH, a Linux-based operating system that allows users to communicate
with externally connected FPGAs via the operating system’s file system [12].
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6. The processor must have an Ethernet connection to allow remote monitoring and control of the board.
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1.4 R HINO TARGET A PPLICATIONS
In order to keep the project focussed, three main applications were selected for the proposed Rhino system:
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1. Radar
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2. Radio astronomy
3. Bioinformatics
These three applications formed the focus of Rhino during the development process. All hardware design decisions were made by considering the effect it would have on these applications. Furthermore, the processing
requirements of these applications were used to determine the hardware requirements for Rhino. Each of these
applications are described in more detail below. Although the first two applications are often grouped under
the common heading of “software-defined radio”, they will be discussed separately here, as their processing
requirements do vary.
1.4.1 Radar
Radar works by transmitting a radio-frequency (RF) signal towards a desired target, and observing the echo
that is reflected back. This received echo signal needs to be processed before it can be of use. The processing typically involves down-conversion and matched filtering operations, which were traditionally performed
using analogue circuits or custom ASICs [13]. Due to the high costs of producing ASICs, the low production
3
volumes of radar equipment, and the desire for flexibility in radar systems (for research applications), analogue circuits and custom ASICs are not ideal. Furthermore, according to Andraka and Berkin [13], typical
radar digital signal processing (DSP) systems perform over 5 billion multiply operations per second, which is
far more than a standard microprocessor-based system can handle. Since FPGAs are parallel devices, they can
perform the large number of multiplies in parallel, and hence offer the performance of custom silicon, while
maintaining the economies and flexibility of the microprocessor-based solutions.
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In both radar and radio astronomy applications, an analogue-to-digital converter (ADC) is required to sample the received signal before it can be processed by the FPGA. The digital output of the ADC is typically
connected directly to I/O pins on the FPGA. In some cases, the ADC samples the received waveform directly
at the carrier frequency and the digital downconversion is performed in the FPGA, while in other cases an
analogue front-end performs the downconversion before the signal is sampled. Furthermore, radar systems
use digital-to-analogue converters (DAC) to generate the transmitted waveform. The digital inputs of the DAC
are too driven by the FPGA.
1.4.2 Radio Astronomy
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Radio astronomy can be regarded as the study of celestial bodies by detecting the radio waves that these bodies
emit. As opposed to optical astronomy, which uses lenses and mirrors to capture the light waves emitted by
celestial bodies, radio astronomy uses radio antennae to detect the radio waves.
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Much like radar, traditional “radio astronomy instrumentation is highly specialized, with custom, complex,
dedicated instruments being built for individual applications. Each instrument takes 3-5 years to design,
construct, and debug, and by the time it is deployed, it has usually been made obsolete by the Moores Law
growth of the electronics industry” [14]. Most radio astronomy applications require that several gigahertz
of bandwidth be processed in realtime. Since microprocessor-based systems are non-parallel in nature, they
would need a clock-rate higher than the datarate in order to process the data in real-time, which is not feasible.
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However, due to their parallel nature, FPGAs are able to process the data in realtime, at a much slower rate, by
splitting the data into a number of parallel processing paths. While this could also be done on a GPU, GPUs
have a number of drawbacks, as was discussed in Section 1.1. FPGAs are typically used in radio astronomy to
perform correlation, beamforming and wideband spectroscopy operations [14]. Such a FPGA-based wideband
spectrometer is described by Chang, Wawrzynek and Brodersen [15]. Here the spectrometer is implemented
using a polyphase filter bank (PFB), a corner turn and a Fast-Fourier Transform (FFT). The PFB is used to
split the input signal into a number of coarse frequency channels (typically a few thousand channels). The
output of the PFB is then recorded using a transpose matrix (called a corner turn), before it is fed into the
FFT. The FFT then performs the detailed spectral analysis of the signal, typically providing 1 Hz (or better)
resolution.
As was described in the previous section, the data is fed into the FPGA from an analogue-to-digital converter.
In addition, high-speed data links (10Gbps) are also often required between different FPGA boards, when
cross-correlation operations need to be performed, as described by Parsons, et al. [16].
1.4.3 Bioinformatics
Bioinformatics can be defined as the application of computer science and statistics to molecular biology. One
of the most important research areas in bioinformatics is sequence analysis, where one attempts to determine
the optimal alignment between two biological sequences (such as sequences of DNA nucleotides or sequences
of proteins) [17]. This typically involves calculating the elements in dynamic programming matrix. Since a
microprocessor can only calculate a single element at a time, while a FPGA can calculate multiple matrix
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elements simultaneously using multiple datapaths, FPGAs can provide significant computational speedups
over CPU implementations. Bioinformatics software tools that have been successfully accelerated on FPGAs
include BLAST and HMMER2, where speedups of over 500 times for BLAST (by The Technical University
of Crete [18]) and over 70 times for HMMER2 (by Derrien and Quinton [19]), have been recorded.
Obviously no ADCs or DACs are required for bioinformatics applications. However, a fast network is required
(usually 1Gbps or higher) to transfer the sequence data between the PC (which stores the database of sequences
on hard-disk) and the FPGA.
1.5 A NALYSIS OF THE R EQUIREMENTS FOR R HINO
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Now that the target applications for Rhino have been discussed, the exact requirements for such a low-cost
FPGA board can be determined. These requirements were obtained by interviewing a range of specialists in
the fields of radar, radio astronomy and bioinformatics from the University of Cape Town, SKA South Africa
and Stanford University. The results of these interviews are summarised in the Table 1.1.
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When reviewing these requirements, it is important to keep in mind that Rhino does not aim to provide the
highest possible computing performance. There are a number of FPGA boards already available that do
provide exceptionally high processing performance (such as the BEE3 [20]), but as a result are relatively
expensive (the BEE3 costs around $25 000 with an academic discount). Furthermore, there are a number
of FPGA development kits available from FPGA vendors that are reasonably cheap, and are very useful as
development and test platforms, but unfortunately do not provide sufficient performance to do useful science
in radio astronomy or achieve considerable speedups in bioinformatics applications. Instead, Rhino aims to
provide sufficient performance to be useful in real-world applications, while keeping the costs low enough
that it is affordable for smaller research groups and development teams with limited budgets.
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Table 1.1: Requirements for Rhino for Target Applications
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Performance
Radar
Synchronise
multiple boards to within
10ns; read two 12 bit
ADCs, each sampling
bandwidth of 400MHz;
1Gbps network.
I/O Interface
Minimum of 2 standardised interfaces for ADCs
and DACs
Ease of use
Simple, rugged physical
user interface (push buttons, etc.), as often used
in field.
Cost
Under $1800
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Radio Astronomy
20Gbps network for
inter-board
communication; read two 8
bit ADCs with bandwidth of 500MHz; 20
Gbps DDR SDRAM
interface3
Minimum of 2 standardised interfaces for
ADCs, so that boards
with different sampling
rates can be used
Simple toolchain that focuses on DSP aspects,
and not technical details (most users are
astronomers, not engineers)
Under $2000
Bioinformatics
1Gbps network to load
database into DRAM.
Minimum
1GB
of
DRAM.
None
Simple library support
for DRAM and network
access. No DSP support
required.
Less than $80004
No FPGA logic requirements, such as number of logic cells or DSP slices, have been given for each of the
target applications. This is because the client specification stated that the Spartan-6 FPGA with the largest
amount of logic resources must be used. It is therefore assumed that the largest device will have sufficient
logic resources for each of the target applications.
By combining the different requirements for the target applications for a low-cost FPGA board, a single set of
requirements can be produced. These combined requirements are shown in Table 1.2, and will be used later
to define the detailed specification for Rhino.
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In most cases, the combined requirements were determined by taking the maximum requirements in each
category. However, in the case of the I/O Interface (input/output interface that is used to connect ADCs and
DACs to the FPGA board), some calculations were required before the summarised requirements for Rhino
could be determined. These calculations are shown in Appendix A, and assumed that the ADCs and DACs
used I/Q sampling and LVDS data lines.
Table 1.2: Summary of Rhino Requirements
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Cost
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Ease of use
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Spartan-6 with largest amount of logic resources.
1GB of SDRAM with 20Gbps throughput.
20 Gbps high speed networking.
Synchronise clocks on multiple Rhino boards to within 10ns.
Two independent ADC/DAC interfaces with standardised connectors. Each interface
must support 32 LVDS pairs, and the FPGA must handle 400Mbps on each pair.
Minimalist physical user interface; simple toolchain that focusses on DSP application
rather than technical details; easy-to-use software libraries for hardware peripherals.
Under $1800
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FPGA resources
SDRAM
Networking
Synchronisation
IO Interface
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1.6 S COPE OF THIS T HESIS
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This thesis focusses on the design of the hardware for Rhino. This refers purely to the Rhino PCB itself, and
does not include the design of any ADC/DAC cards or adaptor boards.
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The software requirements were given in the preceding section, as they form part of the basic requirements
for Rhino. However, the operating system and toolchain are beyond the scope of this thesis. They will only
be discussed in so far as how they might influence the design of the hardware.
That said, low-level embedded software must still be run on the board to test the hardware and hence verify
the design. Therefore, this thesis does cover the basic board-support software that was written to ensure that
the hardware works correctly.
1.7 A N OTE ON N OMENCLATURE
Although Rhino can operate in standalone mode, more often than not it will be connected a desktop computer,
laptop or server via USB or Ethernet. In order to improve readability, the phrase “personal computer” will
be used to describe these computing platforms. Therefore, whenever the phrase “personal computer”, or the
abbreviation “PC”, appears in this thesis, it may refer to a desktop computer, a laptop or a server.
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SDRAM data rate must be higher than combined ADC data rate.
A typical commercial FPGA board for bioinformatics costs $16 000
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1.8 S TRUCTURE OF THE T HESIS
Now that the requirements for Rhino and scope of this thesis have been defined, a review of existing FPGA
boards that are used in software-defined radio applications is given in Chapter 2. Although the reviews focus
on the hardware architecture of each board, a short explanation of the relevant software environment is given
too. The FPGA boards that are included in this review are Roach, USRP N200 and BEE4. Although not
strictly used for software-defined radio, the Xilinx Spartan-6 Development Board (SP605) is also reviewed,
as it makes use of the Spartan-6 FPGA. Since none of these boards were found to meet the requirements for
Rhino, the reviews are followed by a summary of the pros and cons of each board, and how each of the pros
should be used, and each of the cons avoided, when designing a new FPGA platform.
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By combining the customer specification from Section 1.3 and the requirements from Section 1.5, with the
review of existing software-defined radio hardware in Chapter 2, a high-level architecture description for
Rhino is developed in Chapter 3. This description specifies the main hardware elements for Rhino, at a block
diagram level, without specifying which components will be used. The main hardware elements were found to
be an FPGA with two ADC/DAC interfaces, at least 1GB of SDRAM and a high-speed network connection.
The FPGA is connected to an ARM processor, via a bus, which contains USB, Ethernet and flash memory
peripherals. This architecture description can be regarded as the “detailed specification” for Rhino. A brief
description of the software architecture is given too, and how it affects the design of the hardware.
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The architecture description is then followed by a comparison of the different component options in the second half of Chapter 3. These comparisons take the form of trade-off analyses, where the advantages of
different component options are weighed up against each other. Analyses are done for digital and analogue
power supplies, as well as for NAND and NOR flash memory. In these trade-off analyses, analogue power
supplies were preferred over digital ones, and NAND flash memory was selected over NOR memory. The
different component options for the FPGA, the processor, and the ADC I/O interface are also compared. The
XC6SLX150T-4FGG676C was the chosen FPGA, the AM3517 was the chosen processor, and the FPGA
Mezzanine Card (FMC) standard was selected for the ADC/DAC interface.
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With the major components selected in Chapter 3, the detailed hardware design process can be described in
Chapter 4. A detailed sub-system diagram is first developed, describing the four major sub-systems within
Rhino (the FPGA sub-system, the processor sub-system, the debugging sub-system and the power management sub-system), and how they fit together. This sub-system diagram is then transferred to the schematics,
the details of which are also discussed in this chapter. In these hardware discussions, emphasis is placed on
how cost was minimised and testability was maximised at each stage in the design process. The chapter then
ends off with an overview of the clocking infrastructure for the Spartan-6 on Rhino.
Chapter 5 describes the PCB-level design for Rhino. This is described in a separate chapter to the schematiclevel design, as these represent two distinct design stages. Although the actual routing of the Rhino PCB did
not form part of this thesis (it was outsourced), the rules and requirements for the layout and routing needed
to be specified. This chapter therefore begins with a review of the theory behind the routing of high-speed
digital signals. This is followed by the description of the PCB stackup (a 16 layer stackup was used for
Rhino), and the routing rules that were defined. A discussion of the placement of the major components is
also given. Finally, the procedure for simulating the high speed board traces is described, and the results of
these simulations are given. These simulations showed acceptable signal integrity for all high-speed traces.
In order to verify that Rhino was designed and built correctly, a number of hardware and software tools were
developed. Chapter 6 therefore describes the test rig that was built and the test programs that were written to
check the hardware components on Rhino. These test programs took the form of standalone applications that
ran on the processor, and basic gateware designs that ran on the FPGA. However, before the software tests
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could be written, the basic board-support software needed to be developed. A discussion of the bootloader
software and the low-level drivers is therefore also given.
The results of this hardware verification process are given in Chapter 7. This includes photographs of the
completed Rhino PCB, the results of the testing that was performed during manufacturing, and the results of
the software-based tests. The manufacturing tests, which included PCB trace impedance measurements and
X-raying, all gave satisfactory results. All the software-based tests passed too, verifying that the board was
designed and manufactured correctly. As with any large design, a few inevitable bugs in the hardware were
uncovered during the testing process. These bugs are described, along with the hardware modifications that
were made to correct the faults. Finally, a manufacturing cost analysis of the board is given, with the predicted
cost sitting at $1635 for a complete Rhino system.
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Chapter 8 concludes this thesis with a summary of the entire design process for Rhino. It also compares the
final design to the original customer specification and requirements, showing that the board meets the cost,
usability and functionality prerequisites.
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In addition, Chapter 8 outlines the work that still needs to be done for Rhino. This is mainly the changes
that need to be made to the PCB to correct errors in the current revision, before the next revision is released.
Additional work that can be done to further reduce the board cost, such as reducing the number of PCB layers,
is also described. Finally, the specifications for a rack-mount enclosure, which still needs to be built for Rhino,
are given.
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Four appendices have also been included. Appendix A outlines the calculations for determining the I/O
requirements for Rhino, for each of the target applications. Appendix B gives the full Rhino schematics,
while Appendix C gives the proposed layout of the Rhino Hide, the rack-mount enclosure for the Rhino
board. Lastly, Appendix D lists the files on the attached CD.
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CH A P T E R 2
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R EVIEW OF E XISTING
S OFTWARE -D EFINED R ADIO
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Before designing a new, low-cost FPGA board for software-defined radio applications, it would be sensible to
investigate existing FPGA-based hardware that targets similar applications. The aim of such an investigation
would be to identify the strengths and weaknesses of existing hardware, and build on these previous designs
when developing a new system.
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This chapter therefore reviews three FPGA boards: ROACH, USRP N200 and BEE4. These three platforms
are all currently used for at least one of Rhino’s target applications. Although not typically used for any realworld applications, the Xilinx SP605 is also reviewed. The SP605 is Xilinx’s development board for Spartan-6
FPGAs, and hence contains many design elements that may be useful in a commercial Spartan-6 board.
2.1 ROACH
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Each of these four FPGA-based hardware platforms are reviewed below. While the emphasis of each review
is on the hardware architecture of each board, the software environment is also briefly described.
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ROACH is a Virtex-5 based platform, designed by SKA SA (the organisation responsible for building the
Square Kilometre Array in South Africa), primarily for radio astronomy applications. ROACH stands for
“Reconfigurable Open Architecture Computing Hardware”, and forms part of the collection of FPGA boards
used for signal processing by the CASPER radio astronomy community. CASPER is an international collaboration of radio astronomers who aim to “streamline and simplify the design flow of radio astronomy
instrumentation by promoting design reuse through the development of platform-independent, open-source
hardware and software.” [21]. A photograph of ROACH is given in Figure 2.1.
One of the main applications of ROACH is a packetised correlator. A standard radio astronomy correlator
requires a large number of interconnections between different receiver boards. To simplify these interconnections, a packetised correlator uses a high speed network switch (typically 10Gbps Ethernet switch) to connect
the FPGA boards together [22].
Since ROACH is aimed at large radio astronomy installations (such as the Greenbank Telescope1 and MeerKAT2 ),
1
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http://www.gb.nrao.edu/gbsapp/
http://www.ska.ac.za/meerkat/overview.php
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it has been designed to process high data rates on both the ADC I/O side and on the network side. Furthermore, these large radio astronomy installations are typically very expensive, due to the cost of the antennas
and the analogue electronics. Therefore, there has been little need to minimise the cost of ROACH.
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Figure 2.1: Photograph of a ROACH board
(Image courtesy of CASPER: http://casper.berkeley.edu/wiki/ROACH)
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The architecture of ROACH is shown in Figure 2.2. At the heart of ROACH lies a Virtex-5 FPGA, which
is responsible for performing all the data processing on the board. The FPGA uses two Z-DOK+ connectors
(each 40 differential data pairs) to interface with ADC and DAC cards. For networking, the board provides four
CX4 connectors, each supporting 10Gbps Ethernet, resulting in a maximum network throughput of 40Gbps.
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ROACH has both QDR II+ SRAM and DDR2 SDRAM connected to the FPGA. As stated on the ROACH
website [8], the quad data rate (QDR) SRAMs provide 9MB of high speed memory for performing the
previously-mentioned corner turn (matrix-transpose) operation that is used in radio astronomy designs. The
DDR SDRAM, on the other hand, provides higher latency, but larger capacity (typically 1GB) memory, mainly
for buffering. The FPGA also has a couple auxiliary SMA clock connectors, GPIO headers and LEDs.
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In addition to the Virtex-5, ROACH also contains a separate PowerPC chip. The PowerPC is used to both
program the FPGA and control the device once it has been programmed, via a parallel bus. Since the PowerPC
runs Linux, users can easily communicate with the processor via its Ethernet connection. Furthermore, the
PowerPC is running a modified version of Linux called BORPH, which allows users to access registers on
the FPGA by reading and writing virtual files within Linux [12]. In terms of memory, the PowerPC uses a
64MB flash memory chip to store the bootloader and operating system, while the (typically) 1GB of DDR2
SDRAM helps to keep the operating system running. Note that no actual DDR2 SDRAM is provided on the
ROACH board itself. Instead, DIMM (dual in-line memory module) sockets are connected to both the FPGA
and processor, allowing users to plug in as much DDR2 SDRAM as they require.
The processor provides both USB and RS-232 interfaces for additional I/O. Additionally there is an SD card
socket, allowing the PowerPC to load files off an SD card. However, the PowerPC does not natively support
the SD card interface, and so an additional CPLD is required to perform the protocol conversion.
Lastly, the power management and monitoring of ROACH is powered by an Actel Fusion mixed-signal FPGA.
This FPGA monitors all the voltages, currents and temperatures on the board. It also allows remote monitoring
of the the health of the board, and will automatically shutdown the board in the case of over-/under-voltage,
over-current or over-temperature.
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Figure 2.2: The architecture of ROACH
(Image courtesy of CASPER: http://casper.berkeley.edu/wiki/ROACH Architecture)
2.1.2 Software Environment
As it ships, the following software is installed on the flash memory on ROACH:
1. U-boot, a simple bootloader environment
2. BORPH, a custom Linux kernel
3. Busybox, a massively stripped-down filesystem for Linux.
Since the BusyBox file system includes only the most essential files, users typically load their full filesystem
over a network using NFS (a network filesystem protocol), from a USB flash drive, or off an SD card.
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Probably the biggest highlight of the ROACH software environment is BORPH. BORPH is an “operating
system that extends a standard Linux system with integrated kernel support for FPGA resources” [12]. This
allows users to run FPGA hardware designs from within Linux, as standard Linux processes. The advantage
of this is that the FPGA is able to access the Linux filesystem (via the bus between the FPGA and processor),
reading and writing virtual files, and hence providing users with a simple interface to registers on the FPGA.
Gateware designs for the ROACH board are usually developed in Simulink (part of MATLAB), using Xilinx
System Generator to convert the Simulink design into a bitstream that can be programmed onto the FPGA.
The advantage of using Simulink is that users can build systems by graphically connecting together processing
blocks, such as filters and FFTs. The disadvantage to this approach, however, is that large designs can become
very difficult to manage, due to the sheer number of graphically interconnected blocks.
2.1.3 Strengths of ROACH
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The following points can be regarded as the main strengths of the ROACH design:
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∙ The Virtex-5 FPGA provides good performance in terms of speed and number of logic slices. The
large volume of DDR2 SDRAM and QDR II SRAM means that ROACH should be able to meet the
processing requirements of most applications.
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∙ Having a separate processor on the board, running BORPH, provides the user with a simple interface
to monitor and control the hardware design running on the FPGA. This also allows the FPGA to be
programmed without the need for special JTAG programmers.
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∙ The real-time monitoring of temperatures, voltages and currents provides assurance that the board is
running correctly, and if not, it will turn off before any damage can be done.
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∙ Simulink provides an easy-to-use environment in which new hardware designs can be rapidly built, as
long as they are not too large or have multiple clock domains.
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2.1.4 Weaknesses of ROACH
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ROACH does however have a number of pitfalls, such as:
∙ The board is expensive, costing around $5300.
∙ It uses a non-standard ADC interface (the Z-DOK+ connectors). This means that only ADC/DAC
boards designed specifically for the ROACH can be used.
∙ The processor bootloader on the flash memory can only be programmed via JTAG. This means that if
the bootloader becomes corrupt (and reports on the CASPER mailing list confirm that this does happen),
a JTAG programmer is necessary to reprogram the bootloader.
∙ While using DIMM connectors gives users freedom regarding the amount of SDRAM used on the
board, it has been known to cause compatibility problems. Since ROACH has been designed to work
with specific memory timings, there have been reports of commercially-available DIMMs that do not
work with ROACH.
∙ A CPLD interface is required to connect the SD card to the PowerPC, making the design complex.
Furthermore, the PowerPC has no DMA support for the SD card.
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∙ The only method to ship large volumes of data in and out of the FPGA is via the CX4 connectors. This
means that even at low data rates (such as 1Gbps), expensive 10Gbps Ethernet hardware (switches and
PCI-Express cards for the PC) are required.
∙ ROACH has a complex “bringing up” process: the Atmel Fusion FPGA, the CPLD that interfaces
to the SD card, and the flash memory attached to the PowerPC need to be programmed using JTAG
programmers before the board can be used for the first time.
∙ The MATLAB, Simulink and System Generator tools are very expensive, costing $5250.
∙ Simulink is known to crash regularly, apparently on a daily basis for heavy users. Furthermore, the
graphical designs in Simulink become unwieldy if the design is large.
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2.2 USRP N200 AND N210
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The USRP (Universal Software Radio Peripheral) N200 and N210 are FPGA boards, designed by Ettus Research, specifically for software-defined radio applications. According to the USRP N200 series datasheet
[23], these applications include broadcast TV, mobile telephone network base-stations and satellite navigation, in both academic and industrial sectors. Both the N200 and N210 support a wide range of RF front-ends
(known as “daughterboards”), allowing the USRP to handle radio applications at any frequency up to 6GHz.
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Furthermore, the low cost of these devices (the N210 costs $1700), and the rugged, small form-factor enclosures (shown in Figure 2.3 below) make them popular development platforms in various software-defined
radio research fields. Note that most of the information provided here regarding the USRP N200 and N210
has been taken from the USRP N200 series datasheet [23].
Figure 2.3: The USRP N210
(Image courtesy of Ettus Research LLC: http://www.ettus.com/products)
2.2.1 Hardware Architecture
Both the USRP N200 and N210 are powered by Xilinx Spartan-3A FPGAs. The only difference between
these two devices is the resources available on the FPGA: the N200 contains a Spartan-3A XC3SD1800A
(with 37 000 logic cells), while the N210 contains a Spartan-3A XC3SD3400A (with 54 000 logic cells).
Both of these Spartan-3As are however still regarded as low-cost FPGAs. In both cases, the FPGA’s block
RAM (i.e. memory within the FPGA itself) is supplemented by a 1MB high-speed SRAM chip.
Looking at Figure 2.4, which shows the architecture for the USRP2 (which has the same architecture as
the USRP N200 series), one immediately notices the lack of a separate processor. This is one of biggest
differences between the USRP N200 series and the ROACH. The USRP N200 series uses a MicroBlaze softprocessor (i.e. a RISC processor programmed into the FPGA fabric) to manage Ethernet communications,
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configure the daughterboards, and control the flow of data within the FPGA pipeline. The soft-core can
also be used to perform true software processing of the data, by running C programs on the processor. The
advantage of the soft-core approach is that it keeps costs down (fewer components and simpler PCB) and
provides a more flexible interface between the FPGA datapath and processor. The disadvantage, however, is
that the MicroBlaze core uses approximately a third of the logic and memory resources on the FPGA, reducing
the amount of space available for signal processing.
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Figure 2.4: The USRP2 and USRP N200 series architecture
(Image courtesy of Amr El-Sherif, Qatar University:
http://confluence.qu.edu.qa/display/NPRPRESEARCH/USRP2+Testbed)
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The other difference to ROACH is that the ADCs and DACs are built onto the board itself, while only the RF
front-ends are placed on separate daughterboards. A large number of different RF front-ends are available,
with (in some cases, tunable) centre frequencies up to 6GHz. All of these daughterboards plug onto the
USRP mainboards using industry-standard PCI Mezzanine Card (PMC) connectors. On the receiver chain,
the analogue baseband signals are sampled by two 14-bit, 100MS/s ADCs on the USRP main board. Two
separate ADCs are provided to allow I/Q sampling. Similarly, two 16-bit, 100MS/s DACs on the USRP board
provide the signal source for the transmit chain.
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As mentioned previously, the Spartan-3A is a low-cost device with limited logic resources. Furthermore, a
third of the FPGA’s resources are consumed by the MicroBlaze soft-processor. This means that the FPGA
is not able to perform any complex signal processing [24]. Therefore, the FPGA on the USRP N200 series
typically just reads the ADCs, performs some basic filtering and sample-rate conversion, and then packetises
the data for transmission over the 1Gbps Ethernet link. The data is streamed to a personal computer for further
processing in software. The reverse occurs during data transmission.
Multiple USRP boards can be connected together using the MIMO expansion connector. This connector
provides a high speed serial link and a reference clock to synchronise multiple boards. The USRP N200 series
boards can also be clocked externally using the clock input SMA connectors on the front of the box, or can be
synchronised using the add-on GPS-disciplined oscillator module.
2.2.2 Software Environment
Typically, little processing other than the standard filtering and sample-rate conversion is done on the FPGA.
It has been reported that very few users modify the prebuilt FPGA design, due to its poor documentation and
lack of API (gateware libraries) for custom designs. Although it is easier to write custom firmware (C code)
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for the MicroBlaze, allowing the USRP to act as a standalone system, the USRP is still most commonly used
with a host PC.
In this configuration, the FPGA and MicroBlaze processor are programmed with the prebuilt software, and
the actual signal processing is done on the PC, within the free, open-source, GNU Radio framework. GNU
Radio allows users to develop a signal processing system by connecting together signal processing “blocks”
(such as filters, mixers, FFTs) using Python scripts [25]. GNU Radio also includes a number of easy-to-use
graphical interfaces for visualising the data.
The FPGA bitstream and custom processor firmware are stored on the flash memory on the USRP board. The
flash memory can be programmed over the network, making development a simple process.
2.2.3 Strengths of the USRP N200 Series
∙ The RF daughterboards use an industry-standard PMC connector.
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∙ Relatively low cost: the USRP N210 retails for $1700.
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∙ The USRP N200 series has a well-developed mechanism for synchronising multiple boards, using either
the 1PPS clock input, the MIMO cable or the GPS-disciplined oscillator.
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∙ The 1Gbps Ethernet support means that low-cost network hardware can be used.
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∙ The hardware integrates seemlessly with GNU Radio, providing a easy-to-use [24] Python environment in which users can develop software-defined radio applications. Furthermore, GNU Radio is a
completely free, open-source, software tool.
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∙ The FPGA and processor can be easily reprogrammed over the network.
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2.2.4 Weaknesses of the USRP N200 Series
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∙ The USRP N200 series of FPGA boards can only process 100MHz of bandwidth within the FPGA (the
ADCs sample at 100MS/s, with complex sampling).
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∙ Only 50MHz of signal bandwidth can be streamed to a PC for further processing, due to the bandwidth
limitations of the 1Gbps Ethernet link.
∙ The MicroBlaze soft-processor uses approximately 33% of the FPGA logic and memory resources.
Since the FPGA is a low-cost device, its total resources are limited, which means that only the most
basic signal processing can be performed on the FPGA.
∙ It can be difficult for the average user to develop their own custom FPGA and processor code, due to
the lack of documentation and libraries.
2.3 BEE4
BEE4 stands for “Berkeley Emulation Engine 4”. BEE was first developed as a processor emulation platform
to speed up the development of new processor architectures. It is described by Davis, Thacker and Chang
in the Microsoft Technical Report on BEE3 [26], as a platform where “researchers can rapidly prototype a
variety of architectures in a relatively short amount of time by using a repository of low-level component
designs” . The BEE platform was initially developed at the University of California, Berkeley, but the latest
iterations (BEE3 and BEE4) have been developed by BEEcube.
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Although the BEE platform was originally intended for processor emulation, people soon realised that it had
enormous potential for software-defined radio applications. Hence, software-defined radio variants of both
the BEE3 and BEE4 were released, named BEE3-W and BEE4-W, respectively. The BEE4-W (which shall
be discussed in this review) is a stackable, multi-FPGA based prototyping platform, with integrated ADC and
DAC modules, for applications such as radar, software-defined radio and communications [20]. The BEE4-W
is pictured below in Figure 2.5.
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2.3.1 Hardware Architecture
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Figure 2.5: The BEE4 FPGA board
(Original image courtesy of BEEcube: http://beecube.com/products)
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The BEE4 contains four Virtex-6 FPGAs (Xilinx’s latest family of performance FPGAs), interconnected via
a ring bus. Each FPGA has its own independent memory and I/O, resulting in a symmetrical architecture of
four identical processing cells, each containing an FPGA with its own resources. An Intel Atom processor is
used to configure the FPGAs and monitor the hardware, while datapath control is carried out by a Microblaze
softcore on one (or more) of the FPGAs.
The architecture of one of these processing cells is shown in Figure 2.6. Each cell contains a single Virtex-6
FPGA, connected to two DDR3 SDRAM DIMM slots. High-speed network access comes in the form of two
QSFP+ (Quad Small Form-factor Pluggable) connectors. Each of these connectors support Ethernet up to
20Gbps, providing a total network bandwidth of 40Gbps per FPGA. Each cell also contains an FMC (FPGA
Mezzanine Card) connector to interface to a single ADC or DAC card, supporting sample rates well over
2GS/s. Since FMC is an ANSI/VITA standard, there are a number of commercially available ADC and DAC
cards that can be used with the BEE4-W, such as the FMC110 dual ADC/DAC FMC card from 4DSP [27].
Each processing cell also contains a single 1Gbps Ethernet link for control and monitoring, and for data
transfer in applications where high-speed data rates are not required. A number of other peripherals (such as
RS232, LEDs and PCI Express) are also included in each processing cell, and are shown in Figure 2.6.
As mentioned, the BEE4-W contains four identical FPGA cells connected in a ring topology. This provides
the board with a total of 20 million configurable logic gates, 160Gbps network throughput and support for
up to 128GB of DDR3 SDRAM [28]. Each board is also able to support up to four FMC ADC/DAC cards.
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Figure 2.6: The architecture of a single FPGA processing cell on the BEE4-W
(Image courtesy of BEEcube)
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2.3.2 Software Environment
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Furthermore, the BBE4-W platform is scalable, allowing up to 80 boards to be interconnected via high-speed
QSFP+ data links. At $25 000, the BEE4-W is clearly a performance system, rather than a low-cost system.
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The development environment for the BEE4 is called BEEcube Platform Studio, or BPS. It is very similar to
that of ROACH, in that new systems are developed using the Simulink block diagram tool within MATLAB,
and the resulting FPGA bitstream is generated using Xilinx System Generator.
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According the BEEcube, “months of engineering tasks to convert complex DSP algorithms to implementation
can be achieved through BPS in a matter of days, all without requiring user knowledge of the low level FPGA
implementation details” [29]. This is facilitated by the large number of Simulink library blocks written by
BEEcube, for the SDRAM, network and I/O interfaces on BEE4. The user is also able to draw on the Xilinx
DSP blocks available within Simulink.
This means that creating a new design for the BEE4-W is as simple as connecting together graphical blocks
to carry out DSP, communication and I/O functions. However, like ROACH’s development environment, this
approach does result in unwieldy block diagrams when the designs are large.
2.3.3 Strengths of the BEE4
Some of the main strengths of the BEE4 are:
∙ The Virtex-6 FPGAs provide excellent performance (the logic can be clocked at up to 500MHz [20]),
and lots of logic resources (20 million gates per board).
∙ The BEE4-W uses an industry standard connector (FMC) to interface to the ADC and DAC cards. As a
17
result, the board can be used with a number of commercially available ADC and DAC cards.
∙ The board provides both 1Gbps and 20Gbps Ethernet interfaces, giving users more flexibility.
∙ The use of QSFP+ network interfaces, rather than CX4, is an advantage, as many network switch
manufacturers are no longer producing CX4-based hardware [30].
∙ The BEE4 can be fully operated and monitored remotely via Ethernet.
∙ The system is scalable: up to 80 boards can be connected together using the QSFP+ connectors.
∙ The use of a soft-processor (MicroBlaze) for datapath control, rather than a separate processor chip,
is advantageous in this case, as the FPGAs are so large that the logic used by the MicroBlaze core is
negligible. This approach simplifies the PCB design, as no external high-speed traces are required.
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∙ Simulink, together with the pre-written library blocks, provides users with a rapid application development environment.
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2.3.4 Weaknesses of the BEE4
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The BEE4-W does however have two very big pitfalls:
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∙ The main drawback of the BEE4 is the price. At approximately $25 000, it is accessible to only the
largest research and development teams.
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∙ Simulink is reportedly unstable at times and the block diagrams can become unwieldy for large designs.
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2.4 X ILINX SP605
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The SP605 is Xilinx’s evaluation board for the Spartan-6 FPGA. While it does not contain the fastest or largest
Spartan-6 FPGA, it does contain many features common to FPGA-based embedded systems, such as DDR3
SDRAM, Ethernet support and a PCI Express interface.
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Since the SP605 is not a software-defined radio platform, nor is it designed for real world applications, the
strengths and weaknesses of the board will not be evaluated. Rather, the basic architecture of the SP605 will
be described, as it serves as a base template for the design of other Spartan-6 based boards, including Rhino.
2.4.1 Hardware Architecture
The SP605 is shown in Figure 2.7. The core processing components of this board are a mid-range Spartan-6
(XC6SLX45T-3FGG484) FPGA and a 16-bit DDR3 SDRAM IC [31]. Since the Spartan-6 memory controller
supports only discrete memory components (i.e. separate memory chips, and not DIMMs), it would not have
been possible to place a DIMM connector on the board.
The SP605 has a wide range of peripherals to support a number of applications. These include an SFP
connector for high-speed Ethernet, an RJ45 connector providing 1Gbps Ethernet and an FMC connector to
support the use of ADC/DAC cards. The SFP and FMC connectors connect directly to the FPGA, while the
1Gbps Ethernet port is managed by a Marvell Ethernet PHY. There is also a DVI video connector, a USB
connector (which provides a virtual serial port), and a PCI Express finger.
The FPGA is typically programmed via JTAG, using the Xilinx IMPACT software.
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Figure 2.7: The Xilinx SP605 development board
(Image courtesy of Xilinx: http://www.xilinx.com/publications/prod mktg/sp605 product brief.pdf)
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2.5 O UTLINE FOR A N EW, I MPROVED , H ARDWARE P LATFORM
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Three commercially-available FPGA boards that target software-defined radio applications have been reviewed. However, none of these boards fully meet the requirement for a low-cost platform that has sufficient
performance to be useful in real-world radar, radio astronomy and bioinformatics applications. The ROACH
and BEE4 were both too expensive for smaller research and development teams, while the USRP does not
provide sufficient performance nor resources.
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Hardware guidelines:
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Even though none of these boards sufficiently meet the requirements, the reviews have provided useful information on what should be included and what should be avoided when designing a new FPGA-based platform.
This information is summarised below.
1. The FPGA should have sufficient logic resources, and speed grade, to meet the requirements of the
application. The FPGA must be able to do more than simple filtering and sample-rate conversion. The
Spartan-3A does not meet these requirements, while the Virtex-6 is too expensive for a low-cost board.
2. The board must also have a processor running Linux, providing users with a simple terminal interface
to the board. The processor should be a physical processor chip, and not a soft-core on the FPGA.
3. One must be able to program the FPGA without the need for special hardware (such as a JTAG programmer). One solution would be to run a data bus and configuration bus between the processor and
the FPGA, and use the processor to configure and control the FPGA. This could be extended further by
running BORPH on the processor.
4. The board should be powered by an off-the-shelf power supply, simplifying power supply requirements.
5. All voltages, currents and temperatures should be monitored in real-time, and if any of them reaches a
critical level, the board should be automatically switched off.
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6. The FPGA board should be cheap enough for small research groups and development teams. Due to the
popularity of the USRP with such groups, a price under $1800 would probably be appropriate.
7. The board should use an industry-standard connector for interfacing to ADC and DAC cards. For
example, if the FMC interface was used, the FPGA board would support the large number of third-party
cards available on the market.
8. Since the Spartan-6 (the specified FPGA for Rhino) supports only discrete SDRAM chips (and not
DIMMs), discrete SDRAM chips must be used on the board. The advantage is that this avoids all DIMM
compatibility problems. However, the SDRAM chips must provide sufficient capacity and throughput
to meet buffering requirements (especially for radio astronomy).
9. The board should have both 1Gbps and 10Gbps Ethernet interfaces. This gives the user the choice
between bandwidth and cost savings.
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10. The “bringing-up” process after the board is first powered up should be made as simple as possible.
This can be done my minimising the number of programmable devices on the board, and ensuring that
all FPGAs, CPLDs and processors can be programmed via a single Ethernet connection.
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11. There should be a well-managed mechanism for synchronising the clocks on multiple Rhino boards.
This could either be done by providing auxiliary clock inputs on each board, or by using a cable similar
to the MIMO one used on the USRP.
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12. If possible, QSFP+ (or at least SFP+) connectors should be used for the high speed networking interfaces, rather than CX4. This is due to network hardware manufacturers no longer producing CX4
10Gbps Ethernet switches.
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13. The new FPGA system must be scalable.
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Software guidelines:
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1. A software and gateware (FPGA logic) development environment should be provided with the board
that is both easy-to-use and contains many library modules. The environment should allow users to
simply plug together existing library blocks, facilitating rapid application development.
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2. The environment should not however be graphical in nature, but rather text based. This will make the
management of larger systems easier. One such possibility would be to use Python-based tools, such as
MyHDL for FPGA gateware development or GNU Radio for PC-based post-processing.
3. Good documentation and support libraries should be provided to facilitate the development of new
systems.
4. Free, open-source software should be used where possible.
5. Users must be able to fully monitor and control the board remotely. Users should be able to program
the FPGA and get results back without ever having to be in the same room as the physical hardware.
Three existing FPGA boards have been reviewed in this chapter, all of which had applications in the field of
software-defined radio. Although these boards varied in performance and cost, none of them met the specific
cost and performance requirements for Rhino. Therefore, the strengths and weaknesses of each board have
been combined to form the guidelines shown above. In the next chapter, these guidelines are combined with
the original customer specification and requirements to determine the architecture for Rhino.
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CH A P T E R 3
T HE A RCHITECTURE OF R HINO
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After reviewing a number of existing FPGA boards in the previous chapter, the guidelines for a new lowcost FPGA board were drawn up. These guidelines can be combined with the customer specification and
requirements from Chapter 1 to obtain a high-level block diagram for the proposed Rhino FPGA board. This
high-level block diagram can be regarded as the “detailed specification” for Rhino.
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Once the high-level block diagram has been developed, the major components for Rhino are selected in the
latter half of this chapter. This includes decisions such as processor selection, type of I/O interface connector
for ADC/DAC connectors and SDRAM architecture. These major components are then plugged back into the
high-level block diagram to obtain the detailed architecture diagram for Rhino.
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3.1 H IGH - LEVEL B LOCK D IAGRAM AND D ETAILED S PECIFICATION FOR R HINO
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The original customer specification (as described in Section 1.3) is now combined with the results of the
requirements analysis (from Section 1.5) and the review of existing FPGA boards to obtain a high-level block
diagram for Rhino. This diagram, which also shows the performance requirements for each component, is
shown in Figure 3.1.
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This diagram can be regarded as the “detailed specification” for Rhino. It is described in more detail below.
Note that each point in the detailed specification below can be traced back to either the customer specification,
the requirements analysis or the hardware guidelines that were obtained after reviewing similar FPGA boards.
To facilitate the traceability of the detailed specification, each point below is accompanied by one or more of
the following symbols: CS[1-6], RQ[1-7], HG[1-13] or SG[1-5]. They can be described as follows:
∙ CS[1-6] refers to the six customer specification points that were given in Section 1.3.
∙ RQ[1-7] refers to the seven requirements for a low-cost FPGA board that were summarised in Table 1.1.
∙ HG[1-13] refers to the thirteen hardware guidelines that were drawn up at the end of the previous
chapter, after reviewing existing FPGA boards.
∙ SG[1-5] refers to the five software guidelines that were drawn up at the end of the previous chapter.
The use of these symbols allows each of the points in the following detailed specification to be traced directly
back to either a customer specification, a performance requirement or a guideline.
21
Clock
synchronisation
mechanism
(to within 10ns)
FPGA SDRAM:
Discrete ICs
Capacity ≥ 1GB
Throughput ≥ 20Gbps
Power and temperature
monitoring and control
~ XILlNX·
Flash memory
Processor SDRAM
FPGA
FPGA-Processor Bus
Processor
Xilinx Spartan-6
Texas
Instruments
ARM
ADC/DAC
Interface (≥ 32
LVDS pairs)
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1Gbps Ethernet
ADC/DAC
Interface (≥ 32
LVDS pairs)
Other periperals
(UARTs, USB,
RTC, etc)
To
High speed
network interface
(≥ 20Gbps)
Ethernet for control,
programming and
monitoring
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Figure 3.1: Rhino high-level block diagram, indicating performance requirements
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∙ Architecture: Rhino contains an FPGA and a processor, connected via a parallel bus. The processor is
used for coordinating the flow of data in and out of the FPGA, as well as for programming the FPGA
[CS1, HG3].
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∙ FPGA: A Xilinx Spartan-6 FPGA, with the maximum amount of logic resources available. The FPGA
has sufficient I/O resources to support 64 LVDS pairs (connected to ADCs and DACs), each running at
400Mbps [CS2, RQ1, RQ5, HG1].
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∙ Processor: Any ARM processor (a physical processor, not a softcore on the FPGA), manufactured by
Texas Instruments, that is well supported by Linux [CS2, HG2].
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∙ Memory: 1GB of SDRAM connected for the FPGA, with minimum throughput of 20Gbps. The
SDRAM takes the form of discrete components, and not a DIMM. The processor has sufficient SDRAM
to run Linux [CS3, RQ2, HG8].
∙ Flash memory: The processor has flash memory on which the operating system, custom firmware for
the processor and FPGA configuration files can be stored.
∙ Networking: The FPGA has two types of network interfaces: a high-speed network connection with
a throughput of 20Gbps, as well as a slower 1Gbps Ethernet link. The processor also has an Ethernet
connection that allows remote control and monitoring of the board, and programming of the FPGA, but
it may run at any speed [CS4, CS6, RQ3, HG9, HG12].
∙ I/O Interface: Two separate 32-bit LVDS interfaces for ADCs and DACs, using an industry-standard
connector [CS4, RQ5, HG7].
∙ Clock Synchronisation: The Rhino board contains a mechanism to synchronise the clocks on different
boards to within 10ns of each other [RQ4, HG11].
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∙ Power and Temperature Monitoring: All the temperatures, voltages and currents on Rhino are monitored using a dedicated monitoring subsystem, and the results are reported to the processor. If any of
the readings exceed the safety limits, either the offending component will be automatically switched
off, or the board will shut down [HG5].
∙ Cost: Rhino must cost less than $1800 to manufacture [RQ7, HG6].
3.2 S OFTWARE A RCHITECTURE FOR R HINO
Although the software does not form part of this thesis, the proposed software architecture does in fact have
some influence on the design of the board. It is therefore described briefly. Note that the same referencing
symbols that were used in the previous section are used again here.
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The processor will be running BORPH, a Linux variant with FPGA support [CS5]. This will allow users to
remotely communicate with the board over the processor’s Ethernet connection [SG5]. The bootloader and
Linux kernel will be stored on the flash memory on the board, while the file system will most probably be
hosted on a network server and transferred to the board using the NFS (Network Filesystem) protocol.
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As has already been explained, BORPH allows users to program the FPGA with a given design/configuration,
and run it as a software process within Linux. This simplifies both the FPGA configuration/programming
process, and the communication between the FPGA and the processor [HG3]. The consequences of this is
that:
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a.) No provision needs to be made for dedicated JTAG interfaces for programming the FPGA.
b.) The processor must interface to the relevant programming pins on the FPGA, so that the FPGA programming process can be automated by BORPH.
c.) A parallel bus between the FPGA and processor is required for inter-device communication.
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The exact architecture of the toolflow has yet to be determined. However, whatever form it may take, it will
allow the user to focus on the signal processing aspects of the target applications, rather than on the technical
workings of Rhino. This should be achieved by providing the user with number of library blocks (both signal
processing and hardware I/O blocks) that can be simply connected together in a text-based environment, such
as MyHDL1 (a Python to VHDL/Verilog compiler) [RQ6, SG1-4].
For further signal processing on a host computer, GNU Radio will be used. A GNU Radio driver will be
developed that allows Rhino to look like just another software-defined radio peripheral. Besides providing a
simple framework for doing true software-based signal processing, GNU Radio will also allow the captured
data to be visualised in real-time on a computer monitor.
3.3 S ELECTION OF M AJOR C OMPONENTS
Now that the architecture of Rhino has been determined, the main components must be selected. This needs
to be done before the detailed hardware block diagram can be determined, as the choice of components can
impact the detailed architecture. In most cases, the selection of major components was done by performing a
trade-off analysis of the different options. The selection of the Spartan-6 FPGA, the ARM processor, the type
of ADC/DAC interface connector, the high-speed network interface, and the type of flash memory and power
supplies used is explained below.
1
http://www.myhdl.org
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3.3.1 Selection of Spartan-6 FPGA
There are number of devices in Spartan-6 family, each with varying amounts of logic resources, block RAM,
I/O pins and peripheral support. The Spartan-6 devices can be divided into two main groups: LX and LXT. LX
are general logic devices, while LXT are general logic devices with GTP transceivers. Since these transceivers
are required for high speed networking (anything above 1Gbps), only the LXT devices within the Spartan-6
family will be considered.
The customer specification stated that the FPGA with the largest amount of logic must be used for Rhino.
Therefore, the chosen FPGA will be the largest LXT device, the XC6SLX150T. The characteristics for this
device are shown in Table 3.1. This table was taken from the Spartan-6 Family Overview datasheet [32].
Table 3.1: Characteristic of the XC6SLX150T Spartan-6 FPGA
CLB FlipFlops
184 304
CLB
LUTs
92 152
DSP48A1
Slices
180
18kb BRAM
Blocks
268
Max MCBs
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CLB
Slices
23 038
4
Total I/O
Banks
6
To
Logic
Cells
147 443
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These characteristics are explained below:
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∙ Number of logic cells: The most basic programmable element in an FPGA. A logic cell contains a single
look-up table (LUT) and a single flip-flop [33]. This metric is rarely used anymore.
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∙ Number of CLB slices: A CLB is a configuration logic block, the preferred metric for measuring logic
resources. Each CLB is made up of two slices. A single CLB slice contains four look-up tables (LUTs)
and eight flip-flops, as this represents the physical structure within the FPGA die [32].
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∙ Number of DSP48A1 slices: These are the digital signal processing (DSP) resources within the FPGA.
Each DSP slice contains an 18x18 multiplier, an adder and an accumulator.
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∙ Number of BRAM blocks: Block RAM is the fast RAM built into the FPGA itself. Each block is 18kb
in size.
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∙ Maximum number of MCBs: An MCB (memory controller block) is specialised circuitry on the FPGA,
used for interfacing to external SDRAM ICs. Table 3.1 gives the maximum number of MCBs, as the
MCB pins can also be used as normal I/O interfaces.
∙ Number of GTP transceivers: A GTP transceiver is a serial transmitter and receiver pair that is capable of operating at frequencies up to 3.125Gbps. GTP transceivers are typically used for high speed
network interfaces. The number of GTP transceivers is not given in Table 3.1, as the actual number of
transceivers present depends on the physical package used.
∙ Number of I/O Banks: An I/O bank is a group of user I/O pins, powered off a common voltage rail.
Typically, the larger the number of I/O banks, the greater the total number of user I/O pins.
There are also a number of different physical packages for Spartan-6 FPGAs, and each in varying numbers of
pins. The package determines the number of I/O pins and the number of transceivers (a bigger package has
more I/O and more transceivers). The different package options are therefore shown in Table 3.2. Note that
CSGxxx describes a 0.8mm pitch BGA (ball grid array) package with xxx balls, while FGGyyy describes a
1mm pitch BGA package with yyy number of balls.
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Table 3.2: Spartan-6 XC6SLX150T Package Options
Package
Device
XC6SLX150T
CSG484
GTPs User I/O
4
296
FGG484
GTPs User I/O
4
296
FGG676
GTPs User I/O
8
396
FGG900
GTPs User I/O
8
540
Before an FPGA package can be selected, the number of I/O pins required to interface to each FPGA subsystem peripheral must be determined. This is shown in Table 3.3 below. Although the calculations are not
shown here, these values were determined by looking at similar FPGA boards (such as the boards reviewed in
Chapter 2) and counting the number of I/O pins required for each type of peripheral.
Table 3.3: FPGA I/O Requirements for Each Peripheral
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Notes
18 address lines, 16 data lines, 15 control lines
18 address lines, 16 data lines, 15 control lines
32 LVDS data pairs, 2 LVDS clock pairs, 8 control lines
32 LVDS data pairs, 2 LVDS clock pairs, 8 control lines
10 address lines, 16 data lines, 19 control lines
16 data lines, 12 control lines
16 GPIO, 8 LEDs, 8 clocks
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Number of Pins
49
49
76
76
45
28
32
355
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Peripheral
SDRAM 0
SDRAM 1
ADC Interface 0
ADC Interface 1
Processor-FPGA Bus
1Gbps Ethernet PHY
GPIO, LEDs, clocks
Total number of pins
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Although the Spartan-6 XC6SLX150T supports four memory controller blocks (and hence four SDRAM
chips), only two have been included in the calculations above. The reason lies in the fact that each MCB is
in a different I/O bank, and operates at the 1.5V SSTL signalling standard. Therefore, if all four MCBs were
used, four of the six I/O banks would operate at 1.5V, which is unusable voltage for all other peripherals.
Furthermore, the ADC interfaces can only be used on banks 0 and 2 (these are the only banks that support
LVDS) and almost completely occupy these banks in both the FGG676 and FGG900 packages, leaving very
few pins available for other peripherals. Therefore, only two MCBs are used.
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From the table above, it is clear that both the FGG676 and FGG900 packages meet the I/O requirements.
However, in order to keep manufacturing costs down (it is expensive and difficult to place large BGAs) and
simplify the routing of the board, the FGG676 package shall be used. Therefore, the final part number of the
Spartan-6 FPGA to be used is XC6SLX150T-4FGG676C.
3.3.2 Processor Selection
While the processor may not do any computationally-intensive processing, it is just as critical as the FPGA. It
is used for programming the FPGA, monitoring the status of the board, and providing a simple interface to the
FPGA logic. The requirements for the processor were given in Chapter 1, and are repeated here for clarity:
1. The processor must be an ARM device produced by Texas Instruments.
2. The processor must use external SDRAM.
3. The processor must have the necessary hardware to provide both an Ethernet connection (so that the
user can talk to the processor) and an interface to program the FPGA.
4. The processor must be well supported by Linux.
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Texas Instruments (TI) manufactures three types of processors with ARM cores: microprocessors, microcontrollers and DSPs. Since microcontrollers have on-chip RAM and program memory, their memory is generally very limited, while microprocessors use external memory components, allowing them to be supplied with
larger volumes of memory. Microprocessors also typically run at higher clock speeds than microcontrollers.
DSPs (such as the popular OMAP family), on the other hand, can use either microcontroller or microprocessor
cores, but have specialised processing hardware to perform DSP operations very quickly.
It should be clear that TI’s microprocessors are the only viable option for Rhino, as microcontrollers have
insufficient memory and performance, while the DSPs contain hardware that is of no use in this application,
and hence not financially economical. Table 3.4 (taken from the TI ARM Selection Guide [34]) shows the
different families of ARM microprocessors that TI produces, and the typical applications of each.
Table 3.4: Texas Instruments ARM Microprocessors
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Sitara
Cortex-A8
ARM9
The Sitara processors are highperformance, low power devices, with clock speeds up to a
substantial 1.5GHz. The devices
have extensive peripheral integration and are fully supported
by Linux.
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TMS570
Cortex-R4
Designed for safety
critical systems, such
as motor control.
Therefore
includes
a number of safety
features, such as dual
CPUs and built-in self
tests.
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Stellaris
Cortex-M3
Designed for low
cost, low power applications, such as
wireless sensor networks. No mainstream
Linux support (only
FreeRTOS).
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Family
ARM Core
Description
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From this table it is clear that the Stellaris family is not suitable, due to the lack of Linux support, nor is the
TMS570 family, since it sacrifices performance for reliability. Even though the Sitara family of devices are
more expensive than the other two families, their higher performance, extensive integrated peripherals and
excellent Linux support make the Sitara devices the obvious choice for Rhino.
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Only certain devices within the Sitara family have Ethernet support. Since this is obviously a critical interface
for the processor (as it allows remote access to the processor, and allows FPGA configuration files to be copied
to the board), only devices within the Sitara family with Ethernet support were considered for Rhino. The list
of possible devices is shown in Table 3.5 2 . Note that at the time of the project commencement, not all these
devices were available (indicated with a “No” in the “Available?” column). However, these devices which
have become available after the processor was selected have still been included in the table (albeit greyed out)
to show how rapidly technology advances within just 12 months.
Most of the entries in Table 3.5 should be self-explanatory. However, the “External Memory Interface” column
may require some explanation. The external memory interface is used for interfacing to the flash memory and
the FPGA. Sitara microprocessors offer two different types of memory interfaces: EMIF (External Memory
Interface) and GPMC (General-purpose Memory Controller). EMIF has limited configurability, and supports
only NAND flash, NOR flash and SRAM devices. GPMC, on the other hand, is fully configurable and can
interface to just about any type of memory or processing device. Also note that the values in the “MMC/SD”
columns in the table above indicate the number of SD card interfaces on the relevant device, while the values
in the “USB” column indicate the number of supported USB host ports.
2
Obtained by doing a parametric part search on the TI website (www.ti.com) on 22 February 2011.
26
Table 3.5: Texas Instruments Sitara Microprocessor Family (only devices with Ethernet support)
Available?
No
Core Frequency
1.5GHz
AM3892
No
1.5GHz
AM3517
Yes
600MHz
AM3505
Yes
600MHz
AM1808
Yes
456MHz
AM1707
Yes
456MHz
AM1705
Yes
456MHz
SDRAM Support
2x 32-bit (up to
DDR3-1600)
2x 32-bit (up to
DDR3-1600)
1x 32-bit (up to
DDR2-333)
1x 32-bit (up to
DDR2-333)
1x 16-bit (up to
DDR2-333)
1x 32-bit (up to
100MHz non-DDR)
1x 32-bit (up to
100MHz non-DDR)
External Memory
Interface
16-bit GPMC
Video
Output
Yes
Max Ethernet
Speed
1000Mbps
MMC/SD
USB
1
2
16-bit GPMC
Yes
1000Mbps
1
2
16-bit GPMC
Yes
100Mbps
3
3
16-bit GPMC
Yes
100Mbps
3
3
16-bit EMIF
No
100Mbps
4
2
16-bit EMIF
No
100Mbps
1
2
16-bit EMIF
No
100Mbps
1
1
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Device
Name
AM3894
C
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e
To
From Table 3.5, it is obvious that the AM1707 and AM1705 devices are not suitable, due to their slow SDRAM
interfaces. The AM35xx devices are preferable to the AM1808, as the GPMC interface is far more configurable than the EMIF interface, and hence there is a lower risk of compatibility problems when interfacing
to the FPGA. The ARM Cortex-A8 (used by the AM35xx devices) is also much newer and provides better
performance than the older ARM926E core (as used by the AM1808). The Cortex-A8 can run at 2000 DMIPS
(Dhrystone Millions of Instructions Per Second), while the ARM926E can only provide 200 DMIPS [35] [36].
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of
The only difference between the AM3517 and the AM3505 is that the AM3517 has an integrated 3D graphics
accelerator, while the AM3505 does not. While not a critical feature, it is possible that Rhino may be used for
video processing applications where the processor needs to do the final post-processing before outputting the
video to a display. Since the AM3517 costs only $4 more than the AM35053 , the minimal extra cost is worth
the increased functionality. The AM3517 shall therefore be the chosen processor for Rhino. However, since
the AM3505 and AM3517 are pin compatible, it is always possible to switch to the AM3505 in the future.
ni
v
The full feature set for the AM3517, which was taken from the AM3517 datasheet [37], is given in Table 3.6.
U
3.3.3 Selection of I/O Connector for ADC and DAC Cards
Rhino includes two I/O connectors for connecting to ADC and DAC cards. The type of connector chosen
affects the type of ADC/DAC cards that are compatible with Rhino, and is therefore an important decision.
The two options for such a connector are Z-DOK+ and FMC. Both of these connectors are described below,
and their relative advantages and disadvantages are compared.
ZDOK
The Z-DOK+ connector is a high-speed connector produced by Tyco Electronics, supporting 40 differential
pairs and 6 utility contacts for power rails [38]. It is used on all CASPER boards (such as ROACH) and
therefore compatible with CASPER ADC/DAC boards. The Z-DOK+ interface, as defined by CASPER, is
shown in Table 3.7.
The two differential clocks are outputs on the ADC/DAC card and inputs on the FPGA. Some of the differential
data pairs can be used for control, but there is no standard stating which pairs should be used for this.
3
As listed on www.digikey.com on 22 February 2011, for single quantities
27
Table 3.6: Feature Set of the AM3517
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To
e
3 interfaces
4 interfaces
4 ports
3 host interfaces, and 1 USB-OTG interface
12 32-Bit general-purpose timers
1.2V core, 1.8V or 3.3V I/O
ty
DMA
Video Ports
Graphics Accelerator
CAN
EMAC (Ethernet MAC)
MMC/SD
McBSP (Multi-channel
Buffered Serial Port)
I2C
McSPI (Multi-channel
Serial Port Interface)
UART
USB
Timers
Supply Voltage
ap
External Memory Interface
C
CPU Frequency
On-Chip L1 Cache
On-Chip L2 Cache
SDRAM Support
ARM Cortex-A8, with NEON SIMD and vector floating point coprocessors
600MHz
32 KB (ARM Cortex-A8)
256 KB (ARM Cortex-A8)
32-bit SDRAM Controller (SDRC), with support for LPDDR and DDR2
(up to DDR2-333), with 1GB address space
16-bit data, 26-bit address multiplexed (configurable) GPMC bus, with
glueless support for NOR flash, NAND flash, OneNAND, SRAM, and
easily configured to interface to an FPGA
32-Bit Channel SDMA
1 dedicated output,1 dedicated input, both capable of HD resolutions
POWERVR SGX graphics accelerator
1 interface
10/100Mbps Ethernet MAC
3 interfaces
5 ports
of
CPU
er
si
Table 3.7: The Z-DOK+ Connector Pins
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Pins
38 differential data pairs
2 differential clock pairs
5V 1.5A supply
3.3V 1.5A supply
2.5V 1.5A supply
1.8V 1.5A supply
Voltage
2.5V LVDS
2.5V LVDS
-
FMC
FMC, or FPGA Mezzanine Card, is a ANSI/VITA standard (VITA 57.1) developed by Xilinx, Curtiss Wright,
Samtec and a number of other electronics companies, for connecting peripheral cards to FPGA boards. It
defines the mechanical specifications for I/O cards (known as “mezzanine cards”) that plug onto FPGA boards
(known as “carrier cards”) [39]. In the case of Rhino, the mezzanine cards are ADC or DAC cards, while the
carrier card is the Rhino PCB. The FMC standard defines not only the mechanics of the mezzanine card, but
also the electrical interface and mechanical dimensions of the connectors that interface the two boards. These
connectors, manufactured by Samtec, are known as the FMC connectors.
There are two types of FMC connectors: low pin-count connectors (LPC connectors) and high pin-count con28
nectors (HPC connectors). LPC connectors contain 160 pins, while HPC connectors have 400 pins. However,
both connectors have identical form factors and are mechanically compatible; LPC connectors merely do not
have all the pins populated. The pins on the LPC connector are summarised in Table 3.8.
Table 3.8: The FMC LPC Connector Pins
Voltage
2.5V LVDS
2.5V LVDS
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
-
To
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n
Pins
34 differential data pairs
2 differential clock pairs
5 JTAG lines
SCL and SDA lines for I2C
Power good signal
3 mezzanine-to-carrier signals that indicate if card is present, and
address of EEPROM chip
3.3V 3A supply
12V 1A supply
3.3V 20mA auxiliary supply
Adjustable 2A supply (for differential data pairs, usually 2.5V)
C
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e
The FMC specification allows for some, or all, of the 34 differential data pairs to be used as single-ended
LVTTL signals. Although not shown in Table 3.8, the FMC LPC specification also defines two high-speed
serial data pairs (up to 10Gbps). Since all the GTP transceivers on the FPGA are used for the high-speed
network interface, there are no transceivers available for these two serial data pairs, and they are thus left
disconnected.
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of
The FMC HPC connector contains exactly the same pins as the LPC connector, in the same positions. The
specification just defines an additional 46 differential data pairs, an additional 2 differential clocks and an
additional 18 multi-gigabit high-speed serial data pairs.
Comparison of FMC and ZDOK
U
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The FMC connector is selected over the Z-DOK+ connector as the I/O connector of choice for Rhino, for the
following reasons:
∙ FMC is a well-defined ANSI/VITA specification, that defines the function of each and every pin on the
connector, while there is little standardisation of the Z-DOK+ interface (not even all the CASPER ADC
cards are pin compatible with each other).
∙ Since FMC is an industry-recognised standard, there are numerous FMC ADC and DAC cards available
from third-party manufacturers, such as Curtiss Wright and 4DSP [27]. Z-DOK+ ADC and DAC cards
are however only available from the CASPER community.
∙ The FMC specification has been drawn up by experts in the field, and as a result it provides guidelines
for dealing with most thermal and isolation issues [39].
However, it would still be beneficial for Rhino to be compatible with the Z-DOK+ connector too, as this would
allow Rhino to use the various CASPER ADC and DAC cards. This can be achieved by building an FMCto-Z-DOK+ adaptor board. This would essentially be an FMC card with no components other than an FMC
connector (which plugs onto Rhino) and a Z-DOK+ connector (which connects to the CASPER ADC/DAC
card). The one problem is that the Z-DOK+ interface defines 38 differential data pairs, while the FMC LPC
29
connector only provides 34 data pairs. To solve this, Rhino actually uses an FMC HPC connector to provide
the extra data pairs. Rhino uses the LPC pins on the HPC connector, and an additional 4 differential pairs (8
pins) from the HPC part of the connector. The 8 pins on the HPC part of the connector are only used for the
Z-DOK+ adaptor board; in all other cases Rhino uses only the LPC pins on the FMC connector.
3.3.4 Selection of High-speed Network Interface
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n
There are two types of connectors that can be used for the high speed (20Gbps) network interface on the
FPGA: CX4 and SFP+. In both cases, four XAUI (10Gbps Attachment Unit Interface) lanes, each running
at 3.125Gbps, connect the FPGA to the network connector. In a CX4 connector, these four XAUI lines are
connected directly to separate copper wires within the cable. SFP+ (Small Form-factor Pluggable Plus), a
newer standard, instead uses a PHY on the board to convert the four XAUI lanes to a single 10Gbps lane,
which is wired to the connector. Furthermore, the connector on the cable itself usually contains a transceiver
module that converts the single 10Gbps lane into a single copper or optical fibre line. Since SFP+ requires a
PHY and a transceiver, while CX4 is just plain copper wires, the SFP+ option is obviously more expensive.
e
To
While it is tempting to use the latest technologies, in this case the increased cost does not outweigh the benefit.
Furthermore, since Rhino is targeting smaller research groups, many of these groups have older CX4-based
network switches, and due to the price of 10Gbps Ethernet hardware, do not have the funds to purchase new
SFP+ switches. Rhino therefore uses CX4 connectors for the high-speed networking.
of
3.3.5 Selection of SDRAM for the FPGA
C
ap
Note that a single CX4 connector supports speeds up to 10Gbps only. Since the required network bandwidth
for Rhino is 20Gbps (see Table 1.2), two CX4 connectors are required.
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The detailed specification at the beginning of this chapter states that Rhino should have 1GB of SDRAM
attached to the FPGA, with a maximum throughput greater than 20Gbps. The specification also states that
discrete SDRAM ICs must be used, and not DIMMs, as the memory controller blocks (MCBs) on the Spartan6 FPGA support only discrete memory components.
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Since only two of the four MCBs on the XC6SLX150T Spartan-6 FPGA can be used in this design (refer to
Section 3.3.1 for the explanation of why the other two MCBs cannot be used), and each MCB only supports
a single SDRAM IC, only two SDRAM ICs can be connected to the FPGA. The MCBs each support data bus
widths up to 16-bits and memory clock speeds up to 400MHz (DDR3-800). The SDRAM ICs used on Rhino
shall therefore be 16-bit DDR3 devices, to provide maximum memory bandwidth.
Micron SDRAM ICs were selected for use on Rhino due to the availability of low quantities of individual ICs 4
(many other SDRAM manufacturers only sell ICs in quantities of tens of thousands) and their good reputation
for quality in the memory industry. The largest commercially available DDR3 SDRAM components from
Micron, with 16-bit data buses, have a density of 2Gb 5 . If two of these devices are connected to the FPGA,
the total density (size) becomes 4Gb, or 512MB.
Unfortunately, 512MB is only half the memory capacity that was specified for the FPGA at the beginning
of this chapter. However, there are presently no larger devices with 16-bit data buses available from any
manufacturer, nor can the other two MCBs on the Spartan-6 be used. Therefore, for now at least, Rhino
is unable to meet the requirement for 1GB of FPGA SDRAM. Fortunately, Micron is currently providing
4
Micron SDRAM ICs can be bought online from www.micron.com, www.digikey.com and www.arrownac.com
This was determined by performing a parametric component search on the Micron website (www.micron.com) on 24 February
2011
5
30
samples of 4Gb DDR3 SDRAM ICs with 16-bit data buses. Hopefully these devices will enter production
soon and can therefore be used on future builds of Rhino, providing the FPGA with the full 1GB of RAM. To
make provision for this, Rhino will be compatible with both the 2Gb and 4Gb SDRAM components, allowing
either component to be populated once the 4Gb devices become available.
The maximum throughput of the two DDR3-800 SDRAM ICs (they are actually DDR3-1066 devices that
are run slightly slower, as DDR3-800 is the highest speed that the Spartan-6 supports) can be calculated as
follows:
Throughput = (Memory clock) * DDR * 16 bits * (2 ICs)
= 400MHz * 2 * 16 * 2
= 25.6Gbps, which meets the Rhino FPGA memory specification of ≥ 20Gbps
w
n
3.3.6 Selection of Flash Memory Technology for the Processor
To
There exist two main flash memory technologies: NAND flash and NOR flash. NAND memory is typically
used for multimedia storage, as it provides fast sequential access, but slow random access. NOR memory is
typically used code storage, due to its fast random access times.
C
ap
e
Therefore, it may seem counter-intuitive that NAND memory shall be used for code storage for the AM3517
on Rhino. The main reason for choosing NAND over NOR is that the AM3517 uses a common address/data
multiplexed bus to communicate with the memory device. Since most NOR memory devices use separate
buses for address and data signals, they are not compatible with the AM3517.
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of
Spansion does however make a NOR memory device with a common address/data multiplexed bus (ORNAND) [40]. The problem with these devices is that their maximum capacity is 64MB. It therefore appears
that NAND memory would be a better option, as the larger capacity allows bigger Linux distributions and
more FPGA bit files to be stored in the memory. The AM3517 also has considerable cache memory which
should hide most of the NAND access delays.
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3.3.7 Comparison of Analogue and Digital Power Supplies
U
When building a complex circuit board, it is crucial that the power supply system is carefully designed. Rhino
is no exception to this rule, especially since the FPGA requires five different supply voltages and the processor
three supply voltages.
In order to maximise power efficiency, switch-mode power supplies are used. There exist two main types of
switch-mode power supply modules: digital supplies and analogue supplies. Analogue supplies are the most
common and use an analogue feedback loop to regulate the switching of the supply. Digital supplies, however,
use a microprocessor with an ADC to monitor the supply output and regulate the switching accordingly. This
is a much newer technology and allows greater control over the supply switching.
Table 3.9 shows a comparison of these two different power supply technologies, with respect to the Rhino
hardware design. In the purely analogue design, four analogue switch-mode power supplies and a single lowdropout (LDO) linear regulator are used to power the FPGA, while a 3-channel analogue switch-mode supply
(TPS65023) powers the three processor voltage rails. A separate INA219 (voltage and current monitor IC) is
used to monitor the power on each supply rail.
The digital power supply design uses four digital switch-mode power supplies and a single LDO supply
to power the FPGA. These four digital power supplies are controlled and monitored by a single UCD9240
31
controller IC. The same 3-channel analogue switch-mode supply that was used in the analogue design to
power the processor, is used again in this design. These analogue supply rails are once again monitored using
INA219 power monitors.
As one can see from the table, the efficiency is almost identical for both the analogue and digital supplies
(in the case of Rhino’s power requirements). The main advantage of the digital supply option is actually the
component count: a single UCD9240 power supply controller is able to monitor and control four independent
supplies (both voltage and current monitoring), without the need for any external instrumentation amplifiers
or ADCs. It is also able to control two fans, based on temperature readings. This reduced component count
leads to reduced costs.
The advantage of the analogue approach is simplicity: there is no digital controller IC that requires programming. Routing is also simpler, as each voltage/current monitor can be placed directly at each current-sensing
resistor. Furthermore, there are many more analogue supplies available on the market than digital ones.
To
w
n
The trade-off is therefore between cost and simplicity. As a result, it was decided that analogue power supply
modules would be used, as greater simplicity means lower risk of design errors. However, as digital supplies
become more abundant and easier to use, future revisions of the board may use digital supplies instead.
e
3.4 U PDATED H IGH - LEVEL B LOCK D IAGRAM
of
C
ap
Now that all the major components have been selected for Rhino, the high-level block diagram can be updated
to reflect these decisions. This updated diagram is shown in Figure 3.2. Note that even though the SDRAM is
represented as DIMMs in the diagram, these are actually discrete memory ICs.
Power and temperature
monitoring and control
2x 256MB DDR3 SDRAM
1Gbps Ethernet
256MB DDR2 SDRAM
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er
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ty
Clock
synchronisation
mechanism
(to within 10ns)
FPGA
FPGA-Processor Bus
Xilinx Spartan-6
XC6SLX150T
Processor
ARM Core
Texas
Instruments
AM3517
256MB NAND Flash
2x FMC Connectors
100Mbps Ethernet for
control, programming
and monitoring
2x 10Gbps CX4 Connectors
Figure 3.2: Updated Rhino high-level block diagram
This updated block diagram (and hence more detailed architectural description of Rhino) meets all of the
specifications that were drawn up at the beginning of this chapter (see Section 3.1), with the exception of
the SDRAM capacity for the FPGA (1GB). As has been already explained, there are no DDR3 SDRAM
32
components currently available that are big enough to meet this requirement. However, these components
should become available soon and be incorporated into future revisions of Rhino.
With the main components selected, and the detailed architecture of Rhino determined in this chapter, the
block diagram in Figure 3.2 needs to be fleshed out to a greater level of detail. This shall be done in the next
chapter, after which the detailed design will be transferred to schematics.
Table 3.9: Comparison of Analogue and Digital Power Supplies for Rhino
Mixed Digital and Analogue
4x Digital Supply Modules
1x Analogue Supply Modules
1x Analogue Processor Supply Device
2x FPGA LDO Supply
1x UCD9240
5x INA219 Power Monitors
1x 4-channel Temperature Monitor
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n
Analogue
5x Analogue Supply Modules
1x Processor Supply Device
2x FPGA LDO Supply
9x INA219 Power Monitors
1x 4-channel Temperature Monitor
1x 2-channel Fan Controller
To
Component Count
ap
$90.60
2x FPGA
(TPS51200)
9x INA219
$6.30
C
Analogue
Supplies
(3x
PTH08T230W,
2x
PTH08T240W)
Processor Supply (TPS65023)
$8.75
of
Supply
ty
LDO
er
si
Cost
$49.95
$9.86
$2.00
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Temp. Monitor (MAX1668)
Fan Controllers (TC654)
Efficiency (at full
load)
Complexity
Total:
4x Digital Power Supplies
4x Analogue Power Supplies
7x Monitoring ICs
Digital
Supplies
(2x
PTD08A006, 2x PTD08A010)
e
Total:
8x Power Supplies
11x Monitoring ICs
Total
89.9%
$167.46
Factory Setup
Simple enable line to switch each supply on/off. Easy to route, as monitor
can be placed directly at supply
None
Available Supply
Sizes
1A, 3A, 4A, 6A, 10A, 16A, 30A, 50A,
amongst others.
33
$67.76
Analogue
Supplies(1x
PTH08T230W)
Processor Supply (TPS65023)
$16.52
2x FPGA LDO Supply
(TPS51200)
1x UCD9240
5x INA219
Temp. Monitor (MAX1668)
$6.30
Total
90.3%
$148.60
$8.75
$11.66
$27.75
$9.86
PMBus commands used to switch each
supply on/off. 8 lines must be routed
between each supply and the UCD9240
UCD9240 needs to be programmed via
I2C interface before board can be used.
6A, 10A, 15A, 20A only
CH A P T E R 4
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n
S CHEMATIC - LEVEL H ARDWARE D ESIGN
OF R HINO
ap
e
To
The previous chapter described the hardware architecture for Rhino. This architectural description forms the
basis for the sub-system diagram, which is developed in this chapter. This diagram details all the different
sub-systems that together form Rhino. Only once this detailed sub-system description is complete, can the
design can be transferred to schematics.
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C
Each of the schematic pages can be found in Appendix B. Since browsing through pages of schematics can
be tedious, a discussion of the major components on each schematic page, and relevant design decisions that
were made, has been included in the second half of this chapter.
ty
4.1 D ETAILED H ARDWARE S UB -S YSTEM D ESCRIPTION FOR R HINO
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si
The final hardware architecture diagram (see Figure 3.2) is now expanded to form a detailed sub-system
diagram. This diagram, shown in Figure 4.1, shows all the different sub-systems that together form Rhino.
These sub-systems can be loosely grouped into four categories: the FPGA and its peripherals, the processor
and its peripherals, the debugging sub-system, and the power generation and monitoring systems. The FPGA
sub-systems are on the left-hand side of the diagram, the processor sub-systems on the right-hand side of the
diagram, the debugging sub-systems in the top-right corner, and the power systems in the rest of the upper
half of the diagram.
4.1.1 FPGA and its Peripherals
The main component of Rhino, the Spartan-6 XC6SLX150T FPGA, is aptly represented by the largest block
in the sub-system diagram. Connected to the FPGA are two FMC connectors, each with 34 LVDS data pairs,
2 LVDS clock pairs and a couple control wires (including I2 C). The FPGA network support takes the form
of two CX4 connectors (each with four XAUI lanes, providing a total bandwidth of 10Gbps per connector)
and one RJ45 connector for the 1Gbps Ethernet. The 1Gbps link does however require a PHY to convert the
parallel GMII (Gigabit Multimedia Independent Interface) bus into the necessary serial signals that can be
sent down a CAT6 Ethernet cable.
Two 2Gb DDR3 SDRAM ICs provide large capacity memory for FPGA applications that need to buffer large
volumes of data. These two ICs each have a 16-bit data bus, running at 400MHz DDR (i.e. 800Mbps per data
line). This results in a total theoretical memory throughput 25.6Gbps.
34
~
--.
35
0
•
LJ
'---J"--J
~
-
1
1
1
1
-.---J
1
1
1
1
1
1
1
1
--
IEEE1588
Synchro. Clocks
100MHz
Sys Clock
FPGA Config
Level Translator
To
w
n
--
.i- / ---,1
1
1
1
1
1
1
1
-,
1
1
1
1
1
1
I
1
1-Bit Slave Serial
CPU/FPGA Prog. Bus
DDR2
3V3
EMIF
IEEE1588
Synchro. Clocks
SPI
Texas
Instruments
AM3517
(Optional)
48MHz
USB Clock
2
3V3
(Optional)
Interface
3V3 DVI
USB PHY
Debug/
Serial1
Debug/
Serial0
I2C Power
Management Bus
Audio Codec
3V3
10/100Mb
PHY with
IEEE1588
synchro.
3V3
IEEE1588
Synchro. Clocks
GPIO
32kHz Timer
Clock
491-pin sPBGA
Package
26MHz
Sys Clock
EMIF
GPMC
JTAG
NAND
Flash
(2Gbit)
1Gb (16bit)
1V8
1Gb (16bit)
DDR2
,____ =-,.---------r-~ [
1
1
1
1
Figure 4.1: Sub-system diagram of Rhino
156.25MHz
GTP Ref
(nX)
Bus data rate:
~1.3Gbps @ 83 MHz
,
Alan Langman
Simon Scott
UCT SDR Research Group
JTAG
/
J
PHY 1Gb
2V5
/
l- - 1
1
1
1
1
1
1
1
RJ45
,,-'
XAUI 8 pair (4 x GTP)
11
XAUI 8 pair (4 x GTP)
e
-- - - -
1
1
1
1
1
1
1
Processor-FPGA Bus:
16 bits wide
,-----, ~--J
F(G)G 676 Package
396 user IO
180 DSP48A1 slices
8 GTP transceivers
ap
--1
CX4
?
1V8
11
3V3 for Optical Cable
-II-T~:--I-TT---.--~~-~L--J
1fI
*~ ,-Xilinx Spartan-6
XC6SLX150T
Data rate:
~2 x 5.3Gbps
@
166MHz
l
I2C
C
__ J
34 diff pair (LVDS)
Data rate:
~2 x 12.8Gbps
@
400MHz
2x DDR2:
16 bits wide
2Gb
Processor Power
Supply
Debug/
Config/
Test/
Interface
RJ45
LED
UART
Header
RTC
I²C
Audio
In/Out
DVI
SD/MMC
USB0/1
USB OTG
1
1
CX4
FMC LPC
Vita 57.1
"J
2V5
3V3
12V
,.J
34 diff pair (LVDS)
DDR3
I
2Gb (16bit)
1V5
l _____
2x DDR3:
16 bits wide
4Gb
,-------
FMC LPC
Vita 57.1
DDR3
1V5
2Gb (16bit)
1V5
PROC_5V0
I2C
JTAG
SERIAL1
SERIAL0
--
Address/Data/Cntrl - Diff
of
18/16/9 - 3
18/16/9 - 3
V/I Monitoring
TEMP0
TEMP1
TEMP2
Case
Fans
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: !
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r
1 1
2V5
3V3
12V
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Power, temp Monitoring
Fan Control
Front Panel Input
0V75 - VTT
1-------
16 GPIO
AM3517 I2C
FPGA/Processor/Peripheral
Power Generation
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Status LEDs
Power SW
PWR_ON
FAN0
FAN1
1_ _ _ _ _ _ _
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GPIO Header
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Front Panel IO
Monitor/Management
Subsystem
I2C Power
Management Bus
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8 LED
FMC RF Supply
12V
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1
1
2V5
AC/DC
Support for wider input
range for battery source
FMC_3V3
FMC_12V
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12V
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FPGA_3V3
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PROC_5V0
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1V2
1V8
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VDD_CORE_1V2
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VDDA_3V3
1
1
The FPGA is connected to the processor via a parallel bus (which connects to the GPMC interface on the
processor side). This parallel bus allows BORPH to read and write registers on the FPGA [12]. This bus is not
however used for programming/configuring the FPGA. That instead takes place via the Serial Configuration
Interface on the FPGA, which is driven by a SPI port on the processor. The FPGA can also be programmed
via a JTAG header, or via the board-wide JTAG bus (which shall be described later).
For debugging purposes, the FPGA is also supplied with 8 LEDs and a 16-bit GPIO header. Clocking takes
the form of a 100MHz system clock and a 156.25MHz GTP reference clock. Furthermore, the clock lines on
the FMC connector can also be used to clock the FPGA.
4.1.2 Processor and its Peripherals
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The AM3517 processor is depicted by the large green block on the right-hand side of the diagram. Its two
1Gb DDR2 SDRAM ICs are wired in parallel and connected to the 32-bit EMIF (External Memory Interface).
Each of these ICs have a 16-bit interface, running at 166MHz DDR (i.e. 333Mbps per line).
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Both the NAND flash memory and the FPGA are connected to the GPMC (General Purpose Memory Controller) interface on the processor. This interface has 16 data lines (which can be multiplexed to act as address
lines too), 10 dedicated address lines and a large number of control lines. This bus can be configured to support a number of different bus protocols, allowing glueless interfacing to both the NAND flash and the FPGA.
As was mentioned previously, the FPGA is programmed using one of the SPI interfaces on the processor, via
a 3.3V to 2.5V level translator.
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The processor uses a DP83640 Ethernet PHY to provide 100Mbps Ethernet access. A PHY is essentially a
transceiver that converts the parallel RMII (Reduced Media Independent Interface) signals from the Ethernet
MAC (on the processor) to serial signals that can be transmitted down an Ethernet cable. One advantage of
using this particular PHY is that it supports the IEEE1588 Precision Time Protocol (PTP). PTP allows the
clocks on a number of devices (i.e. Rhinos), connected via a local network, to be synchronised to within 10ns
of each other. This PHY therefore satisfies both the processor Ethernet support and the clock synchronisation
requirements for Rhino.
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Other major processor peripherals include the SD card (Secure Digital card) interface, the two USB host ports
and the USB On-the-Go port. The processor is able to boot from any one of these peripherals, as well as the
previously mentioned flash memory and Ethernet interface, without requiring any special firmware. Just like
the Ethernet interface, the two USB host ports also each require a transceiver (or PHY).
The processor also has a video output interface (using a High Definition Multimedia Interface, or HDMI,
connector); three audio connectors for line-in, line-out and headphones; a real-time clock chip; an RS-232
connector for communicating with devices like GPRS modems; and two LEDs for debugging. While none
of these peripherals are critical, and Rhino would still meet all the requirements identified in Chapter 1 if
none of these peripherals were used, they have been added to improve the usability and versatility of Rhino.
Furthermore, this has been done at minimal extra cost, as all these hardware peripherals are natively supported
by the AM3517 processor.
The processor is clocked by three different oscillators: a 26MHz system clock that is multiplied internally to
generate the various CPU clocks; a 48MHz oscillator that clocks the USB sub-system on the processor; and a
32kHz clock that is used in low-power modes.
36
4.1.3 Debugging Sub-Systems
The FTDI USB-to-UART/JTAG/I2 C converter IC (shown in top-right corner of the sub-system diagram) provides most of the debugging facilities on Rhino. This single device has a USB port, which when connected to
a personal computer (PC), creates two virtual serial ports, a virtual JTAG port and a virtual I2 C port. Applications running on the PC can read and write to these virtual ports as if they were separate physical ports on the
computer. The two serial ports on the FTDI chip are wired to UARTs on the AM3517 processor. The JTAG
port drives the board-wide JTAG chain on Rhino. Lastly, the I2 C port connects to the I2 C power management
bus on Rhino, allowing all the power rails to be monitored from a PC, without needing the AM3517 processor.
4.1.4 Power Generation and Monitoring Sub-Systems
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The power generation and monitoring sub-systems are shown in the top half of Figure 4.1. The two dark
orange blocks represent the FPGA and processor power supplies. The lighter orange block at the very top
depicts the monitoring sub-systems, which are responsible for monitoring all the power supplies, temperatures
and fans.
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The power generation and monitoring sub-systems are shown in more detail in Figure 4.2. Power is supplied
to the board by an external 12V power supply, which directly powers all the on-board switch-mode power
supplies. The large light-orange block on the left of the diagram (labelled “FPGA and FMC Power Generation”) shows the four switch-mode power supplies for the 1.2V, 1.5V, 2.5V and 3.3V rails for the FPGA
and FMC mezzanine cards. The 0.75V and 1.2V supplies (for the DDR3 SDRAM termination resistors and
GTP transceivers, respectively) take the form of LDO (low drop-out) regulators to minimise ripple, and are
powered off the 1.5V switch-mode supply. The FMC cards are not powered directly off the FPGA supplies,
but via load-switches that allow the cards to be turned on only when needed. These load switches, along with
the switch-mode supplies and LDO regulators are switched on and off by enable lines connected to GPIO pins
on the AM3517 processor.
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The processor is powered by a single 3-channel switch-mode power supply IC (TPS65023). This IC generates
the 1.2V (core), 1.8V (SDRAM) and 3.3V (I/O) necessary to power the AM3517 processor [41]. Since this
power supply cannot be powered directly off the input 12V, a secondary switch-mode power supply is used to
step the input 12V down to 5V. This 5V is also used for powering the USB host ports.
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All the power supplies on Rhino are monitored using INA219 power monitor ICs. These devices are able to
monitor both the output voltage and current (using a current-sensing resistor) of a single supply, and report
these results over an I2 C interface [42]. A 3-channel temperature monitor allows the temperature of the FPGA
heatsink, the processor heatsink and the ambient air to be continuously measured and reported over I2 C. Lastly,
a fan controller IC is used to both control and measure the speed of two case fans. All these board monitoring
devices (power, temperature and fan) are shown in the light-purple block at the bottom of Figure 4.2, and are
connected to a common I2 C bus, which is controlled by the AM3517 processor.
In a typical use-case scenario, the processor would read all the power supply voltages and currents once a
second, and if it detected an error condition (such as over-voltage or over-current), it would shut down the
offending power supply and log a fault to the SD card. The processor would also measure the temperatures
once every five seconds, and if a device was running too hot, it would increase the fan speeds. If this did not
help sufficiently, it would then switch the offending component off.
Lastly, a push-button controller is used to manage the power-up and power-down sequences on the board. This
controller enables the processor 5V supply when the user presses the main power switch, hence booting the
37
100240V
En
External supply or
power brick
AC/DC
1V2
Supply
6A
En
1V5
Supply
6A
Vin
Vin
12V in
0V75 - VTT
LDO 3A
1V2 - MGT
LDO 1.5A
Vin
FPGA Supplies
Incoming & Proc
Supply
FPGA and its Peripherals
I2C
SMBus
ARM
Heatsink
Sensor
FET
Switch
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Ambient
Temperature
Sensor
Vcc
-
--
12V
I2C
SMBus
12V
En
GPIO Out
GPIO Out
AM3517 ARM
Processor and
Peripherals
Multi-channel Supply
(TPS65023)
1V2: 1.7A
1V8: 1A
3V3: 1A
I2C
Vin
Interface
3V3
1V2
2
Last Rev. 10/02/2011
Alan Langman
Simon Scott
UCT SDR Research Group
USB Host Port (x2)
I C Power
Management Bus
5V0
Processor Power Generation
5V Supply
6A
Vin
I2C
SPI
Interrupt In
I2C Power
Management Bus
Monitor/Management
Subsystem
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SPI I/O
Expander
Figure 4.2: Power generation and management for Rhino
I2C
Case Fan
Connector 1
To
Fan controller: 2 channels
PROC 3V3
I2C
SMBus
Case Fan
Connector 0
~
PROC 3V3
Vcc
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FET
Switch
FMC LPC Connector (x2)
of
Temperature Monitor: 3 channels
FPGA
Heatsink
Sensor
FET
Switch
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Enable Out
Kill In
Interrupt
--
Voltage/Current/Power Monitor: 10 channels
En
3V3
Supply
10A
Vin
12V
Push-button
Controller
Status LEDs
~'--
PROC 3V3
En
2V5
Supply
10A
Vin
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FPGA and FMC Power Generation
Vin
Button Press
Power SW
Front Panel IO
J
Vcc
FMC
Supplies
1V5
Vin
1V2
38
1V2
1
J
2V5
12V
Reconfigurable Hardware Interface for Computation and Radio
Rhino
r--'
3V3
~ '------'
12V
~ '-----
0V75
'r--'
1V5
J
2V5
1
1V2
:[
L:(
r-
~
3V3
2V5
H
3V3
]
5V0
l
12V
- 1-+1
3V3
-
~
12V
~
2V5
~
1V8
~
5V0
l_~
processor. If the user initiates a shutdown from within Linux, the processor would send a kill signal to the
push-button controller, which in turn switches the processor supply off. If, however, the user switches off the
board by pressing the main power button again, the processor is sent an interrupt signal, informing it that it
has 4 seconds to save all data and gracefully shutdown before the supply is switched off.
4.2 T HE R HINO S CHEMATICS
Now that the design of Rhino has been sufficiently detailed at a sub-system level, the design is transferred to
schematics. The schematics, which have been included in Appendix B, were drawn up using Altium Designer.
It should be mentioned that these schematics are hierarchical in nature. The first schematic sheet is the toplevel sheet which contains component blocks (called sub-sheets), representing other lower-level schematic
sheets. These schematics sheets can in turn contain other sub-sheets, creating a schematic hierarchy. The
sub-sheets are shown as rectangular boxes (usually green in colour) with input and output ports that can be
connected to other sub-sheets that occur in the same top-level sheet.
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An example of this hierarchical schematic system is shown in Figure 4.3. Each of the dashed black boxes
represents a separate schematic sheet. The top level schematic sheet contains two sub-sheets: switches and
leds. Each of these two sub-sheets have two ports, which are connected together in the top level sheet. The
inner workings of these two sub-sheets are shown on two separate schematic pages, with the same names:
switches and leds. On the switches schematic, the two ports, sw1 and sw2 are outputs, while the two ports,
led1 and led2 are inputs on the leds schematic sheet. Note that the top level schematic is at a higher level in
the schematic hierarchy than the other two schematic sheets.
leds
sw1
led1
sw2
led2
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switches
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top_level schematic
3V3
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switches schematic
leds schematic
3V3
U1A
led2
S1
SW-PB
5
S2
SW-PB
6
54AC11034FK
U1B
sw1
R1
100k
GND
led1
sw2
R2
100k
4
7
54AC11034FK
R3
120
R4
120
D1
GND
GND
D2
GND
Figure 4.3: An example of Altium’s hierarchical schematic structure
This hierarchical nature of Altium Designer simplified the process of converting the sub-system diagram to
schematics. Each block in the sub-system diagram was drawn as a “block” (or sub-sheet) in the top-level
39
schematic, with the appropriate input and output ports. The internal workings of each of these sub-sheets
were then later described in lower-level schematic sheets.
This section is best read in conjunction with the actual schematics in Appendix B. It explains the functions
implemented by each schematic sheet and how the different sheets link together. It also aims to explain the
reasoning behind the major design decisions that were made on each sheet.
4.2.1 Cover Page, Table of Contents and Rhino Power Distribution and Monitoring
Both the architectural block diagram and power generation diagram have been repeated on the first few pages
of the schematics. A table of contents has also been included allow the reader to quickly find the pertinent
schematic sheet. Note that the page numbers in the table of contents refer to the schematic sheet numbers (in
the title box in the bottom right corner of each schematic sheet) and not the dissertation page number.
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4.2.2 Rhino Overview
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The Rhino Overview page is the top level schematic sheet for the entire schematic project. It has been drawn
so that it mirrors the sub-system diagram as closely as possible (see Figure 4.1). Each block in the sub-system
diagram has now been replaced with a sub-sheet, as represented by each of the coloured rectangles in the
Rhino Overview schematic. For example, the purple Xilinx Spartan-6 block in the sub-system diagram has
been replaced by the large, purple-pink spartan6 sub-sheet block on the left-hand side of the Rhino Overview
schematic.
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As has already been explained, each of these blocks, or sub-sheets, represent actual schematic sheets lower
down the schematic hierarchy. The schematic for the spartan6 sub-sheet is shown on page 5 of the schematics.
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The main differences between the original sub-system diagram and the Rhino Overview schematic are:
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∙ The debugging sub-system is represented by the usb to jtag rs232 sub-sheet.
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∙ To clearly illustrate how all the devices connect together to form the JTAG chain, a separate jtag chain
sub-sheet has been created. There is no such block in the sub-system diagram.
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∙ There is only one sub-sheet for both of the processor’s DDR2 SDRAM ICs, while the sub-system
diagram had two separate blocks.
∙ All of the power generation and management blocks in the sub-system diagram have been replaced by
the single pwr supply management sub-sheet. The reason for this is that the power nets are all global,
and hence do not need to be represented by connections on the top-level schematic.
4.2.3 Spartan-6 (top-level)
This is the schematic for the spartan6 sub-sheet in the top-level schematic. It itself contains a further 10
sub-sheets, represented by the 10 green boxes. These sub-sheets are for the six I/O banks, the configuration
interface, the multi-gigabit transceivers (MGT), the power supply pins and the supply decoupling capacitors.
The ports (yellow and blue hexagons on the left and right edge of the schematic) represent the ports on the
spartan6 sub-sheet block on top-level schematic, which are wired to the different FPGA peripherals. On this
schematic page, these ports are now wired directly to their relevant I/O bank, configuration interface or the
transceivers.
40
It is useful to note that there are three types of connections (nets or wires) shown on this schematic page:
thin blue wires, thick dark-blue wires and thick pale-blue wires. The thin blue wires are single nets. The
thick, dark-blue wires are buses, which contain a number of wires with identical functions. An example of
such a bus is the 8-bit USER LED[7..0] bus, which drives the FPGA LEDs. The third type of connection is
the thick, light-blue wires called harnesses. Harnesses are used to group together nets that perform related,
but not identical functions. The FPGA CONFIG BUS harness is shown in the bottom left-hand corner of
the page. This harness contains five different nets (DONE, PROGRAM B, etc) that together form the FPGA
configuration interface.
4.2.4 Spartan-6 Bank 0
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The data bus for the second FMC connector (FMC1) is connected to I/O Bank 0 on the FPGA. Since the FMC
interface uses LVDS, there are actually two separate buses: FMC1 LA P[33..0] and FMC1 LA N[33..0]. The
eight pins on the HPC part of the FMC connector that are used purely for the FMC-to-Z-DOK+ adaptor board,
are also connected to I/O Bank 0.
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The Spartan-6 I/O Bank 0 contains eight global clock pins, indicated by “GCLK” in the pin name. These
global clocks are connected to bits 0, 1 and 17 of the FMC bus, as the FMC specification states that these
lines can be used for source-synchronous clocking. The 100MHz system clock, which is used for clocking
the FPGA fabric, is also connected to one of the global clock inputs.
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4.2.5 Spartan-6 Bank 1
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Bank 1 has a myriad of peripherals connected to it, with the main one being the FPGA-processor bus. The
signals that make up this interface are shown in the FPGA PROC BUS harness at the centre of the page (the
large, pale-blue rectangle). The harness contains a 10-bit address bus, a 16-bit data bus, and a number of
control signals.
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There are also a number of FMC control signals wired to Bank 1 for the I2 C interface. As has been mentioned,
bits 0, 1, 17 and 18 of the FMC data bus can be used for source-synchronous clocking. However, the dedicated
clock lines, FMC0 CLK[1..0] M2C [N/P], can also be used to transmit the clock from the FMC card to the
FPGA. Unfortunately, due to a shortage of differential global clock inputs on the FPGA, these differential
signals must first converted to single-ended CMOS signals (by the dual lvds receiver0 block) before they are
connected to FPGA global clock inputs. The details of this differential-to-single-ended converter are shown
on the next page of the schematics.
As was explained in Section 4.1.2, the DP83640 Ethernet PHY is used for the 100Mbps processor Ethernet,
as it supports the Precision Time Protocol. The 1Hz precision output clock of the PHY is connected to Bank
1 of the Spartan-6 (1588 CLK). Furthermore, the Ethernet PHY has four GPIOs that can be programmed to
signal events at certain times. These four lines (1588 GPIO[3..0]) are also connected to Bank 1.
4.2.6 Dual LVDS Receiver 0
This schematic shows the inner workings of the dual differential-to-single-ended converter that was used for
the FMC clock signals on the previous schematic sheet. Two MAX9111 LVDS receivers are used to convert
the two LVDS signals to two 3.3V CMOS signals. Since the MAX9111 is rated for clock signals up to
250MHz, it does place a limitation on the maximum frequency of the FMC mezzanine-to-carrier (M2C) clock
signals. If data is transmitted on both the rising and falling edges of the clock, this allows data rates up to
500Mbps. Since the requirements for Rhino, in Table 1.2 of Chapter 1, state that the maximum data rate on
the FMC interface is 400Mbps per line, this limitation should not however cause any clocking problems.
41
4.2.7 Spartan-6 Bank 2
The Spartan-6 I/O Bank 2 is nearly identical to Bank 0. Connected to Bank 2 are the data bits of the first FMC
connector, FMC0. Again, bits 0, 1 , 17 and 18 of the FMC data bus are connected to global clock inputs on
the FPGA. However, only four of the eight extra lines for the Z-DOK+ adaptor board are connected to Bank
2, as some of the bank’s pins are used for the serial configuration interface (the interface used to program
the FPGA). The configuration pins CONF CCLK, CONF DIN and CONF INIT B are all connected to the
FPGA CONFIG harness on the Spartan-6 (top-level) schematic (sheet 5), while the rest of the configuration
pins are either pulled high or low with resistors.
4.2.8 Spartan-6 Bank 3
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Bank 3 contains the GMII interface to the 1Gbps Ethernet PHY, the 8 User LEDs, the 16 GPIO lines, and
the remaining four Z-DOK+ adaptor lines that did not fit into Bank 2. Since Bank 3 of the FPGA does
not have internal termination for LVDS signals, external termination resistors are required for these four
FMC 0 ZDOK [P/N][1..0] lines.
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The Gigabit Multimedia-Independent Interface (GMII) contains 8 data lines that carry data from the FPGA to
the PHY (TXD[7..0]), and 8 data lines that carry data in the reverse direction (RXD[7..0]), allowing full duplex
communication. The TX CLK and RX CLK clock signals are inputs to the FPGA, and are therefore connected
to global clock pins. The slower, serial, management data interface used for controlling the Ethernet PHY is
also connected to Bank 3. This interface consists of the MDIO, MDC, INT, RESET and COMA signals.
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Just like in Bank 1, the two dedicated FMC clock pairs, FMC1 CLK[1..0] M2C [N/P], pass through a differentialto-single-ended converter before being tied to global clock inputs on the FPGA. Note that in Bank 1, the dedicated clock lines were for FMC connector 0, while in Bank 3 they are for FMC connector 1. Even though there
are unused global clock inputs on Bank 3, the FMC clocks must still be converted to single-ended signals, due
to restrictions on the routing of differential clocks within the FPGA. These restrictions will be explained in
more detail later in this chapter.
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4.2.9 Dual LVDS Receiver 1
Same as Dual LVDS Receiver 0.
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4.2.10 Spartan-6 Bank 4 and Bank 5
In order to simplify the interfacing to external SDRAM devices, the Spartan-6 contains four Memory Controller Blocks (MCBs). The blocks take the form of special circuitry within the FPGA itself that is able to
interface directly to external SDRAM components, via dedicated FPGA pins. Bank 4 of the Spartan-6 FPGA
contains the connections for MCB 4 (which connects to DDR3 SDRAM 0), while Bank 5 contains the connections for MCB 5 (for DDR3 SDRAM 1). The SDRAM interface (represented by the DDR3 BUS harness),
consists of a 16-bit data bus (DQ[15..0]), a 14-bit address bus (A[13..0]), 3 bank address lines (BA[2..0]), 2
differential data strobes (xDQS [P/N]), a differential clock (CK [P/N]) and 8 control lines.
4.2.11 Spartan-6 Multi-Gigabit Transceivers
The high-speed GTP transceivers on the Spartan-6 are often referred to simply as MGTs (Multi-Gigabit
Transceivers). The XC6SLX150T-4FGG676C has 8 such transceivers, each consisting of a single transmitter and a single receiver. Since each of the transceivers runs at 3.125Gbps, differential signalling is used to
minimise noise and improve signal integrity.
42
Four of the transceivers are connected to CX4 connector 0 (indicated by the top MGT BUS harness), while the
other four are wired to CX4 connector 1 (indicated by the bottom MGT BUS harness). Capacitors are placed
on all the receive lines to remove any DC offset that may have been injected by a network switch.
Since all the transceivers run at the same speed, only two reference clocks are used (see the MGT CLKS IN
port), each running at 156.25MHz.
4.2.12 Spartan-6 Configuration
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The preferred method of programming the Spartan-6 FPGA on Rhino is via the Serial Configuration Interface.
The serial clock and data pins (CONF CCLK and CONF DIN) are actually part of I/O Bank 2, and were
discussed earlier in this chapter. These pins are driven by an SPI port on the ARM processor. The DONE
pin, which is shown on this schematic page, goes high when the FPGA is correctly programmed. This signal
connects to both an LED (which is ON when the FPGA is not configured) and to the processor. The ARM
processor pulls PROGRAM B 2 to clear the FPGA and begin a new programming sequence. This pin is also
pulled low by the temperature sensor (see RESET port) if the FPGA gets too hot, thereby resetting the FPGA.
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The FPGA can also be configured using JTAG. This can either be done via the main JTAG chain, or via the
dedicated FPGA JTAG header (connector J10 on this schematic page). A 4-bit, 2-to-1, bus selector is used to
select either the JTAG chain or the JTAG connector as the source for the JTAG interface on the FPGA. The
selector is controlled by a jumper (P1) on the Rhino PCB. The dedicated FPGA JTAG header is a fail-safe
mechanism that allows the FPGA to be configured even if the board-wide JTAG chain is not working and the
processor is not running. The JTAG header therefore helps to reduce risk and aid debugging.
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4.2.13 Spartan-6 Power and Supply Decoupling Caps
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The Spartan-6 Power schematic page shows all the power supply pins on the FPGA. I/O Bank 0 (with power
supply pins VCCO 0) and I/O Bank 2 are both powered with 2.5V, as these banks connect to the LVDS data
pairs on the FMC connectors. I/O Bank 1 runs at 3.3V so that it can interface with the processor’s GPMC bus,
while I/O Bank 3 runs at 2.5V so that it can interface with the 1Gbps Ethernet PHY. I/O Banks 4 and 5 are set
to 1.5V for interfacing with the DDR3 SDRAM ICs.
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The supply decoupling capacitors are shown on the following schematic page. These are placed directly
underneath or around the FPGA on the PCB, as close to the power supply pins as possible.
4.2.14 DDR3 RAM
The FPGA’s large capacity memory takes the form of two 2Gb DDR3 SDRAM ICs. These two ICs are shown
on sheets 18 and 19 of the schematics. The DDR3 BUS harness is identical to the harness of the same name
that was described on the Spartan-6 Bank 4 schematic (sheet 12): 14 address (A) lines, 3 bank address (BA)
lines, 16 data (DQ) lines and a number of control signals.
Since DDR3 technology supports on-die termination (ODT) for the data signals, no external termination
resistors are needed for the DQ[15..0] bus. External termination resistors are however needed for the address,
bank address and high-speed control lines.
The dotted red boxes placed around certain net names on the schematic sheet are PCB directives: rules that
define how the nets must be routed on the PCB itself. Generally these rules are used to indicate that certain
nets must be routed as traces with a specified impedance. The other type of PCB directive that is used in the
schematics is shown in Figure 4.4. This symbol indicates that two nets must be routed as differential pairs.
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Figure 4.4: The PCB directive for a differential pair
4.2.15 FMC HPC Connector
The schematics for the FMC HPC connectors are shown over sheets 20 to 27. Note that each sheet is shown
twice, as there are two FMC connectors. Even though the two copies of each schematic sheet may look
identical at first glance, the component designators (C265, J17, etc) are in fact different.
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The FMC HPC Connector (top level) schematic is the only FMC schematic of interest; the rest simply show
the FMC HPC x harnesses being trivially wired to each of the rows on the FMC connector. On the FMC HPC
Connector (top level) schematic, one can see that the 34-bit data bus (LA P[33..0]) is connected to rows C, D,
G and H. These four rows form the LPC part of the connector. The other six rows, A, B, E, F, I and J form
the HPC part of the FMC connector. There are also connections for power, I2 C, JTAG and the CLKx M2C
dedicated clock lines, all of which are on the LPC part of the connector.
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4.2.16 CX4 10Gbps Ethernet Connector
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The additional four data pairs for the FMC-to-Z-DOK+ adaptor board are connected to row E, which lies
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Again, there are two copies of the CX4 connector schematic (sheets 28 and 29), as there are two separate CX4
connectors on the board. The main component on the CX4 schematic page is the CX4 connector itself, shown
on the upper half of the sheet. The connector has 16 signal pins, allowing 8 differential pairs, or 4 XAUI lanes
(containing both a transmitter and a receiver pair) to be connected. PCB directives have been included on the
schematic to show that these signals must be routed as differential pairs with 100 ohms differential impedance.
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The lower half of this schematic page contains the circuitry necessary to power any CX4-to-optical adaptors
that may be plugged into Rhino. This circuit was adapted from the datasheet for the Fujistu o-microGiGaCN
device [43], one such CX4-to-optical adaptor. These adaptors have a standard CX4 connector that can plug
into Rhino. However, laser diodes and detectors are placed directly inside the connector, and the copper cable
is replaced with four optical fibre lines, allowing the cable to be as long as 300m.
In order to power these devices, four of the ground pins on the CX4 connector are reassigned to serve as
power and control signals for the optical adaptor. One such pin is G7, which acts as a type-sense signal.
When an optical adaptor is plugged into this socket, the adaptor sets this pin to approximately 1.66V. When
the TYPE SENSE net is at this voltage, both comparators in IC U66 are switched on, activating the 2A load
switch, U67, which provides 3.3V to pin G8 on the CX4 connector, hence powering the optical adaptor.
It is important to note that this circuit is fully compatible with standard CX4 cables. If a standard CX4 cable
is connected, the optical power is automatically switched off. A green status LED indicates when the optical
power is switched on, while a red LED indicates if there is an optical fault.
4.2.17 1 Gbps Ethernet PHY
The Marvell 88E1111, depicted by the large yellow rectangle in the centre of the schematic, is the Gigabit
Ethernet transceiver of choice for Rhino. The transceiver, also known as a PHY, is connected to the Spartan6 FPGA by the Gigabit Multimedia Independent Interface (GMII), which consists of an 8-bit transmit bus,
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an 8-bit receive bus and a number of clocks and control lines. Both the transmit bus and receive bus have
source termination series resistors to help improve signal integrity. The optimum values of these resistors
were determined by performing signal integrity simulations, which will be described in Chapter 5.
The transceiver converts these two 8-bit buses into four differential signals (MDI0 to MDI3) that can be
transmitted down a Gigabit Ethernet cable. These four differential signals are connected to the RJ45 Ethernet
jack on the right of the schematic. The transformers/magnetics on the MDIx lines, which are required for
isolation and common-mode noise rejection, are integrated into the RJ45 connector itself.
The Marvell 88E1111 also has a number of LED outputs that can be programmed to perform different functions. The circuit has been designed with the following settings indicated in Table 4.1 in mind.
Table 4.1: LED Settings for the Marvell 88E1111 Gigabit Ethernet PHY
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Function
On if link up (at any speed), off if link down
Don’t care
On if link running at 1000Mbps, off if any other speed
Don’t care
Idle high, pulse low if Ethernet packet received
Idle high, pulse low if Ethernet packet transmitted
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LED
LED LINK10
LED LINK100
LED LINK1000
LED DUPLEX
LED RX
LED TX
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The LEDs do not perform these functions by default; the PHY must be correctly programmed by the FPGA,
using the serial management data interface (pins MDC and MDIO), before the LEDs will function as intended.
The LED LINK1000, LED RX and LED TX pins connect to LEDs on the PCB, while the LED LINK10
drives the green LED on the RJ45 connector. The LED RX and LED TX signals are also OR’ed together
using diodes so that they flash the yellow LED on the connector if a packet is transmitted or received.
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The Marvell 88E1111 PHY includes 7 configuration pins (CONFIG0 to CONFIG6) that are used to set certain
hardware settings at power-up. By tying these configuration pins to 2.5V, ground, or one of the six LED pins,
each CONFIG input can be set to one of eight values. These hardware settings are explained in the Marvell
88E1111 datasheet [44]. The settings for Rhino’s PHY are given in the “General Notes” box at the bottom of
the schematic sheet.
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The JTAG pins connect to the board-wide JTAG chain on Rhino, although this interface should never need
to be used. The Marvell PHY also contains two debug pins, HSDAC+ and HSDAC-, whose output voltage
indicates the type of fault that has occurred. These two signals are connected to test-points on the PCB.
4.2.18 Spartan-6 GPIO Header and LEDs
A GPIO header connector has been included on Rhino. This connector contains 16 GPIO lines that connect
directly to 2.5V FPGA I/O pins. All pins are protected against short-circuits by 100 ohm series resistors,
against ESD spikes by ESD protectors (ESDA5V3SC6), and against over-voltage inputs by 3.3V zener diodes.
There are also 8 yellow LEDs, connected directly to FPGA pins, to provide a simple debugging interface for
FPGA gateware designs.
4.2.19 Spartan-6 Clocks
Besides the clocks on the GMII interface, the processor bus and the FMC cards, all of which can be used to
clock the FPGA fabric, two dedicated oscillators are also used. The top oscillator on the Spartan-6 Clocks
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schematic page (U57) runs at 156.25MHz and is used for clocking the GTP transceivers on the Spartan-6.
Since two clock signals are required to clock all eight transceivers, a clock splitter (U36) is used to split the
clock into two separate signals. These LVPECL clock signals are appropriately terminated and AC-coupled,
as specific in the Spartan-6 GTP Transceivers User Guide [45].
The second oscillator is a 100MHz LVDS-output device that should be used for clocking most of the logic on
the FPGA. All the clock signals are routed as 100 ohm, differential traces.
4.2.20 AM3517 (top-level)
This is the main schematic for the AM3517 ARM processor. It is represented by the large green sub-sheet on
the top-level schematic (sheet 4). The AM3517 schematic contains four sub-sheets, which represent the different parts of the processor: am3517 periph a, am3517 periph b, am3517 power and am3517 decoupling.
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Most of the ports on the left- and right-hand edge of schematic connect directly to ports on the appropriate
AM3517 sub-sheet. There are, however, certain ports that are not directly mapped and require some explanation. The first ones are the FPGA PROC BUS and NAND ports. Since these two devices both connect to the
GPMC (General Purpose Memory Controller) interface on the processor, the FPGA PROC BUS and NAND
harnesses are expanded and both connected to the GPMC harness.
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Since the real-time clock, audio codec, and front-panel PCB are all connected to the same SPI (serial peripheral
interface) port, their data and clock lines are tied together. Each device obviously has its own chip-select line.
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The last set of signals that require some explanation are the warning signals in the bottom-left corner of the
schematic. Due to lack of processor pins, these signals are all connected to the SYS BOOT pins on the
processor. The SYS BOOT input pins are used to specify booting options, such as which memory device
from which to boot and which clock sources to use. Since the warning signals have unpredictable state, they
obviously cannot be connected to the SYS BOOT pins at startup. The warning signals are instead buffered
before being wired to the SYS BOOT pins, and this buffer is disabled at boot time.
4.2.21 AM3517 Peripherals (Part A)
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This schematic shows most of the parallel interfaces on the processor. The SDRC (SDRAM Controller) bus
consists of a 32-bit data bus, a 14-bit address bus, a 3-bit bank address bus, and a number of control signals.
This bus is wired directly to the two DDR2 SDRAM ICs.
The GPMC interface is also shown, and has already been explained. The DVI (Digital Video Interface) harness
is shown on the left of the schematic, and connects to a video transmitter IC. Both the DVI and the SDRC
interfaces have 22 ohm source series termination resistors, to help prevent overshoot at the receiver.
The other smaller interfaces shown on this schematic include the FPGA configuration interface, which is
connected to SPI port 2 and is used for programming the FPGA; the SD card interface; debug UART 1 which
is connected to the FTDI USB-to-UART converter; and the UART for the modem serial port (RS232 DATA).
4.2.22 AM3517 Peripherals (Part B)
Most of the processor pins on this schematic page are used as GPIOs to control peripherals. The few pins
that are used to perform other functions include the three I2 C interfaces (I2C PWR MAN, DDC I2C and
FMC I2C); the 100Mbps Ethernet RMII interface (ETHER RMII); the JTAG pins (PROC JTAG); the two
USB host ports (HS USB1 and HS USB2); and the multi-channel buffered serial port (McBSP2) which
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streams audio samples to the audio codec (AUDIO DATA).
The SYS BOOT pins, which were described in Section 4.2.20, are also shown on this schematic page (bottomright corner). Since the buffer for the warning signals is switched off at boot time, the levels of these pins
are determined by the pull-up and pull-down resistors alone. The levels of SYS BOOT3 and SYS BOOT5
can however be set using two switches (S1), allowing the boot device order to be changed by the user. These
two switches allow either the NAND flash memory, the MMC/SD card or the Ethernet link to be set as the
preferred boot device. Once the processor has booted, the SYS BOOT pins become normal GPIO pins, and
the warning signal buffer is enabled.
4.2.23 AM3517 Power and Supply Decoupling Caps
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The processor core runs at 1.2V, the SDRAM interface at 1.8V and the I/O pins at 3.3V. Just like with the
FPGA, a large number of supply decoupling capacitors are required to keep the supply stable. These capacitors
are placed directly underneath or around the processor on the PCB, as close to the supply pins as possible.
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4.2.24 AM3517 DDR2 RAM (top level)
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The processor has two 1Gb DDR2 SDRAM ICs connected to it. Each of these two ICs, which are represented
by the two green sub-sheet blocks on this schematic, have a 16-bit data bus. The data buses of these two
RAM chips are combined to form a single 32-bit data bus, which connects to the processor’s SDRC (SDRAM
Controller) interface. All the control signals (except the data masks, UDMx and LDMx, and the data strobes,
UDQSx and LDQSx) and address signals are common for both SDRAM ICs.
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4.2.25 DDR2 RAM
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This schematic shows the internal workings of the ram ddr2 sub-sheets on the previous page. There are two
DDR2 RAM schematic pages, as there are two RAM chips. At the centre of this schematic page is the Winbond
1Gb DDR2-800 SDRAM IC. Although this device is capable of running at DDR2-800 speeds, the processor
is only able to clock the SDRC interface at DDR2-333 speeds.
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The RAM chip has a 16-bit data bus, a 14-bit address bus, a 3-bit bank address bus, and a number of control
lines. Although the AM3517 processor supports on-die termination for DDR2 SDRAM ICs, the data sheet
still recommends that external source series termination is used on all data, address and control lines [37].
Therefore, 22 ohm series resistors have been placed on the address and control lines directly at the processor,
while the series termination resistors on the data lines are placed directly at the RAM chip itself.
All DDR2 RAM traces are routed with 50 ohms characteristic impedance; or 100 ohm differential impedance
in the case of the differential pairs.
4.2.26 NAND Flash
The Micron 256MB NAND flash chip is typically used for storing the processor bootloaders and Linux kernel,
but may also be used for storing FPGA configuration files. The flash device connects to the processor GPMC
interface, as was described in Section 4.2.20. It is interesting to note that the NAND flash memory does not
have any address lines, just an asynchronous data interface (IO[15..0]) and control lines. The 16-bit data
interface is multiplexed within the device to transfer commands, address and data as efficiently as possible.
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4.2.27 100Mbps Ethernet PHY
A National Semiconductor DP83640 Ethernet PHY provides the physical layer interface between the ARM
processor and the Ethernet cable. The PHY communicates with the processor over the Reduced Media Independent Interface (RMII), which consists of a two-bit transmit and a two-bit receive bus. A management data
interface (MDIO and MDC) has also been provided to allow the processor to configure the PHY.
On the physical layer side of the device, two differential pairs (one transmit, one receive) connect to the RJ45
Ethernet jack. Again, the magnetics necessary for isolation and common-mode noise rejection are integrated
into the RJ45 jack. The PHY also has three LED outputs: LED LINK (indicates that link is up), LED SPEED
(on if link running at 100Mbps) and LED ACT (indicates network activity).
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As has been mentioned, this particular Ethernet PHY supports the IEEE1588 Precision Time Protocol. The
purpose of this protocol “is to synchronize the time between different nodes on an Ethernet network” [46],
with an accuracy of 10ns or less. The DP83640 Ethernet PHY has an internal clock that is synchronised
to a master clock using the Precision Time Protocol, which is achieved by sending special packets over the
Ethernet link. This internal, synchronised clock is used to generate the 1 pulse-per-second (PPS) clock output,
which can be used to clock either the FPGA or the processor (see the 1588 CLK1 and 1588 CLK2 output
ports in the top-right corner of the schematic). The Ethernet PHY can also be programmed, by the master
clock, to generate an event at a particular time. This event is indicated by one of the GPIO outputs on the PHY
(see output port 1588 GPIO[3..0]), which are connected to both the processor and the FPGA.
4.2.28 RS-232 Header for Peripherals
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The PHY also includes a JTAG interface for debugging. The interface is connected to the Rhino board-wide
JTAG chain, but it is not expected to ever be used.
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In order to allow hardware peripherals with RS-232 interfaces (such as GPRS modems) to be connected to
Rhino, a RS-232 serial port has been included. This serial port may be useful in network radar applications,
where the easiest way to communicate with each node is via GPRS. The serial port supports the full RS-232
protocol, with hardware flow control and modem signals. A MAX3243 level converter is used to convert the
3.3V signals from the processor to RS-232 level signals that can be sent down a serial cable.
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Due to lack of space along the connector edge of the Rhino PCB, no 9-pin D-SUB (DB-9) connector is
included on the Rhino PCB. Instead, the signals are connected to a 10-pin header. The intention is that a
panel-mount DB-9 connector will be installed on the back plate of the Rhino enclosure, and this connector
will be connected directly to the PCB header with a ribbon cable.
4.2.29 AM3517 Clocks
Three oscillators are used to clock the AM3517 processor. The 26MHz system clock is used to clock the
processor core and most of the on-chip peripherals; the 32kHz clock is used when the processor is in standby
mode; and the 48MHz oscillator clocks the USB on-chip hardware on the AM3517.
4.2.30 USB On-the-Go
USB On-the-Go (OTG) is an extension of the USB 2.0 specification, that allows devices to act as both USB
hosts and USB peripherals [47]. It also allows two OTG devices to be connected directly to each other with
a standard USB cable, without needing a hub. This is useful in the case of Rhino, as it allows a Rhino to
communicate with a PC at maximum USB speeds (480Mbps). It also allows two Rhinos to be connected
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directly together with a simple USB cable, if network hardware is not available.
The AM3517 has an on-chip USB On-the-Go PHY, allowing a direct connection from the processor pins to
the USB connector. A ESD protector has however been added to protect the processor from electro-static
discharges. The processor is, however, not able to provide the 5V supply for the USB port. This is achieved
using a high-side load switch (U56), which can be switched on and off by the processor.
4.2.31 USB Host Transceivers
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Rhino is equipped with two USB Type-A host ports. This allows USB flash drives, keyboards and USB
modems to be attached to the board. The processor has two high-speed (480Mbps) USB host controllers,
but requires external transceivers before it can interface to USB peripherals. These transceivers (USB3320
devices manufactured by SMSC) interface to the processor via a 8-bit bi-directional data bus, running at
60MHz (60MHz * 8 bits = 480Mbps). This 8-bit data bus, together with the bus clock and three control
signals, conform to the UTMI+ Low Pin Interface (ULPI) standard.
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Besides converting the 8-bit parallel ULPI interface into the serial USB bus, the transceivers also handle the
low-level USB protocol details, such as negotiating the link speed with the peripheral. Both transceivers are
connected to the same dual-port stacked USB connector (J11). No external ESD protectors are required, as
the transceivers contain both ESD and over-voltage protection circuitry. The USB power is provided by a
dual-channel high-side load switch (U52), which is controlled by the transceivers. The load switch provides
over-current protection, and the over-current warning signals, USB1 OC and USB2 OC, are connected to
GPIO pins on the processor.
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4.2.32 SD Card and Real-time Clock
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The SD card connector allows SD (or MMC) cards, up to 32GB, to be plugged into Rhino. The SD card
will typically contain the Linux filesystem and FPGA configuration files. However, it may also contain the
bootloaders and Linux kernel, as the processor can be set to boot from the SD card using the boot switches.
Since the AM3517 processor contains an internal SD card transceiver, no external circuitry other than the
physical connector is required.
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A real-time clock (RTC) has been included to provide the processor with the current date and time, in cases
where there is no GPS or network clock available. This may be useful when Rhino is used in remote locations
and the recorded data needs to be time-stamped. The processor communicates with the real-time clock over
SPI. In order to ensure that the clock does not lose time when the Rhino board is unpowered, a 1.5 Farad
super-capacitor provides backup power for the clock. This capacitor should be able to keep the clock running
continuously for over a month if no other power is available.
4.2.33 HDMI Video Transmitter
As has already been discussed, the AM3517 contains a graphics accelerator and video output port, which in
the case of Rhino, may be used for video signal processing applications. If a keyboard and mouse are plugged
into the USB host ports on Rhino, then the video output port may also allow Rhino to act as a standalone
computer with a graphical user interface.
A TFP410 video transmitter is required to serialize and encode the RGB (red, green, blue) pixel data streams.
The transmitter connects to the processor via a 24-bit pixel bus (DATA0 to DATA23), with 8-bits per colour.
The IDCK, VSYNC and HSYNC timing signals are used to align the pixel bitstream to form video frames.
These three 8-bit buses are serialised and TMDS (transition minimised differential signalling) encoded to
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form three serial signals (TX0 to TX2) and one clock signal (TXC), that are transmitted to the monitor via the
HDMI (High Definition Multimedia Interface) connector (J14).
The HDMI connector also supports the Display Data Channel (DDC) protocol, which allows the monitor
to inform the processor which display modes it supports. The data and clock signals for the DDC protocol
(DDC SDA and DDC SCL) connect to an I2 C port on processor, after being level shifted from 5V to 3.3V.
4.2.34 Audio
Rhino is equipped with line-out, line-in and headphone audio jacks. Audio samples are streamed between the
processor and the TLV320AIC23 audio codec (U10) over an Inter-IC Sound (I2 S) interface (AUDIO DATA
port in the schematic). The I2 S interface connects directly to a Multi-channel Buffered Serial Port (McBSP)
on the processor. An additional SPI port (AUDIO CTRL) is used for changing settings such as the headphone
volume and the sample rate. The ADCs and DACs within the codec support sample rates up to 96kHz.
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External resistor-capacitor circuits are used to filter the analogue inputs and outputs. The 1nF capacitors on
the LINE IN input remove any high-frequency noise above 100kHz, while the 2.2uF capacitors block any DC
components in the signal. The RC circuits for both the PHONES channels and the LINE OUT channels act as
high-pass filters, removing any DC offset and noise below 30Hz. These filter circuits were tuned using SPICE
simulations.
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4.2.35 USB to JTAG/I2 C/RS-232
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The FT4232 IC from FTDI is a USB to JTAG/I2 C/RS-232 converter. It contains a USB interface that is
typically connected to a PC, and four independent ports that can be configured for JTAG, I2 C or UART
operation. When connected to a PC, four virtual JTAG, I2 C or RS-232 ports are created to which application
software can read or write. Drivers on the PC perform the translation from JTAG, I2 C or RS-232 to USB,
while the FTDI chip on Rhino translates the data it receives on the USB back to JTAG, I2 C or RS-232.
On Rhino, the USB pins on the FT4232 IC are connected to a USB Type-B connector, similar to that used in
printers. This allows the USB port to be connected to a PC with a standard USB printer cable.
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The four multi-function ports on the FTDI chip (A, B, C and D) are shown on the right-hand edge of the IC
symbol in the schematic. Port A is configured as a JTAG master; port B is configured for I2 C, and allows the
power management I2 C bus to be monitored from the PC; and port C and D are both configured as UARTs and
connected to the processor. The I2 C port aids board testability, as it allows the power management devices to
be monitored even if the processor is not running correctly. The JTAG port also includes two GPIO pins that
are used for switching the FPGA on, so that it can be programmed via JTAG.
Since the four ports are, by default, configured as UARTs at power up, and not as JTAG or I2 C interfaces,
buffers are used to prevent port A and port B causing bus contention on either the JTAG chain or I2 C power
management bus, while they are still configured as UARTs. Only once the device has been connected to a PC,
and the correct driver has been installed, will the driver on the PC pull the JTAG EN line low and the I2C EN
line high, enabling both buffers (U58 and U59).
An EEPROM chip, on which is stored the USB “device name” and other settings, is connected to the FTDI
IC. Four orange LEDs have also been connected to the transmit and receive lines of the two UART ports,
allowing traffic to be monitored.
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4.2.36 JTAG Chain
This schematic contains seven JTAG harnesses, representing the seven devices on the Rhino JTAG chain.
The JTAG master port, shown on the left, is connected to the JTAG port on the FTDI USB-to-JTAG/I2 C/RS232 converter. The first two devices on the JTAG chain are the FPGA and processor, both of which can be
programmed via JTAG. The next two devices are the FMC connectors. However, since it is possible that
no FMC mezzanine card may be connected, two 1-bit bus selectors (U17 and U18) are used to selectively
add or remove each FMC card from the JTAG chain, depending on whether the card is present or not. This
is determined by looking at the FMC x PRSNT signals. The last two devices on the JTAG chain are the
100Mbps and the 1Gbps Ethernet PHYs.
4.2.37 Configuration Interface Level Translator
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The Serial Configuration Interface on the FPGA is used for programming/configuring the FPGA. It is connected to an SPI port on the AM3517 processor. However, the FPGA configuration interface runs at 2.5V,
while the processor’s SPI port is at 3.3V. Therefore, voltage translators are used to perform the conversion. A
description of each of the configuration signals is given in Table 4.2.
Table 4.2: FPGA Serial Configuration Interface Signals
Description
Programming clock
Programming data
Indicates that programming is about to begin
Indicates that FPGA has been correctly configured/programmed
Processor can pull low to delay programming
FPGA can pull low to indicate that a CRC error occured
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Proc to FPGA
Proc to FPGA
Proc to FPGA
FPGA to Proc
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CCLK
DIN
PROGRAM B
DONE
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4.2.38 Power Supply Management
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This is the top level sheet for all the power supply and monitoring schematics. The four green boxes in middle
of the page are the four power supply sub-sheets. The large green box on the right-hand side is the sub-sheet
for power monitors, while the smaller sub-sheet beneath it is for the temperature monitors and fan controllers.
The sub-sheet on the far right contains the power LEDs.
This schematic sheet also contains the push-button controller, shown in the top-left corner, which switches
the processor on and off when the power push-button is pressed. When the board is switched off, and the
push-button is initially pressed, the controller enables the processor power supply. If the push-button is later
pressed for 200ms or longer, an interrupt (INT output) is sent to the processor, instructing the processor to
prepare for shutdown. Once the processor has completed its shutdown tasks, it acknowledges the interrupt
by pulling the PWR KILL port low, and the controller switches the processor supply off. If, however, the
processor does not respond to the interrupt within 4.4 seconds, the controller assumes that the processor has
crashed, and it is switched off anyway.
The SUPPLY EN port on the left of the schematic is a harness containing all the power supply enable lines.
These enable lines are all connected to the processor, allowing the processor to switch off parts of the board
when they are not needed, hence conserving power. There are also two FPGA power suppy enable lines
coming from the FTDI USB converter (FTDI SUPPLY EN port). These allow the USB converter to power up
the FPGA so that it can be programmed. A dual OR gate has been used to combine the FPGA power enable
signals from the processor and the USB converter.
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The warning outputs of each supply and power/fan/temperature monitor are placed on the PWR WARNS
harness in the top right corner of the schematic. This is wired to processor GPIO pins. Below this, test points
have been added for each power supply rail, to aid debugging and improve testability.
Lastly, the front panel connector is shown in the bottom left corner. This header connector contains pins for
the power push-button, reset button, power LED, and I2 C and SPI buses to control front panel LEDs.
4.2.39 Spartan-6 Power Supplies
The four switch-mode power supplies for the FPGA and its peripherals are shown: 1.2V for the FPGA fabric,
1.5V for the DDR3 SDRAM; 2.5V for the FMC cards and the 1Gbps Ethernet PHY; and 3.3V for the FMC
cards and processor interface.
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The calculations to determine the current requirement for each supply are shown in Table 4.3. The last two
columns will be explained in the next section. Although analogue switch-mode power supplies are available
in many different current ratings, the most common values are 3A, 6A and 10A. Therefore, 6A supplies were
selected for the 1.2V and 1.5V rails, while 10A supplies were used for the 2.5V and 3.3V.
Table 4.3: Power Requirements for the FPGA and its Peripherals
Spartan-6 XC6SLX150T
Micron MT41J128M16HA
N/A
N/A
Marvell 88E1111
N/A
1.2V
4000
1.5V
2500
551
630
630
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381
4000
6381
6000
7350
630
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1.2V MGT
1000
500
250
4250
Supply Current (mA)
2.5V 3.3V 0.75V VTT
2000 800
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DDR3
DDR3 Termination
CX4 Optical
1Gbps Eth PHY
FMC Connectors
Total Current
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4.2.40 Spartan-6 LDO Power Supplies
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Besides the four main switch-mode power supplies that power the FPGA, an additional two low-dropout
(LDO) regulators are also used. A 0.75V LDO regulator provides the DDR3 SDRAM termination voltage,
while a 1.2V regulator powers the multi-gigabit transceiver circuitry on the FPGA. The current requirements
for these two LDO regulators are shown in the last two columns of Table 4.3.
An LDO regulator, rather than switch-mode power supply, has been used for the DDR3 termination voltage, as
an LDO is cheaper than a switch-mode supply, and efficiency is not critical when the current is small. Since the
multi-gigabit transceivers require a supply with extremely low ripple, the existing 1.2V switch-mode supply
was not suitable, and a separate LDO has been used instead.
4.2.41 FMC Power Supply Switches
The FMC mezzanine-cards require four different power supplies, as shown in Table 4.4. High-side load
switches are used to selectively enable or disable each power rail.
The 3.3V auxiliary 2.5V supplies are switched using a commercial load switches (TPS22924C). However, this
switch is only rated for 3.6V up to 2A, and therefore cannot be used for the 3.3V (3A) and 12V (1A) power
rails. These power rails are instead switched using a MOSFET circuit, the details of which appear on the next
few pages. The MOSFET circuit is represented on this schematic using SI6463BDQ switch sub-sheets.
52
Table 4.4: FMC Mezzanine Card Power Requirements
Supply Voltage
2.5V
3.3V
3.3V auxiliary
12V
Supply Current
2A
3A
20mA
1A
Purpose
ADCs/DACs and LVDS data bus
ADCs/DACs and control
EEPROM chip
RF circuitry (if present)
4.2.42 Si6463BDQ FET Load Switch
A Si6463BDQ MOSFET is used to switch the 3.3V and 12V FMC power rails. To allow the P-channel
MOSFET to be switched using 3.3V logic levels, an NPN transistor is used. Since the MOSFET requires a
minimum load current to operate correctly, a 10k burden resistor has been connected to the output.
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There are four copies of this schematic, as there are two FET load switches per FMC card. The operation of
this circuit has been verified using SPICE simulations.
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4.2.43 AM3517 Power Supply
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Texas Instruments, the manufacturers of the AM3517 processor, also manufacture a companion 3-channel
switch-mode power supply for this processor. This power supply (TPS65023) has three output channels [41]:
1.2V @ 1.7A, 1.8V @ 1A and 3.3V @ 1A. Unfortunately, Rhino’s 12V DC input is above the maximum input
voltage that this device can tolerate; therefore, a second switch-mode supply is used to convert the input 12V
down to 5V (U21). The 5V is also used for powering the USB ports.
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In order to ensure that this 3-channel power supply can deliver sufficient current to the AM3517 and all its
peripherals, the power requirements need to be determined. These requirements are summarised in Table 4.5.
From this table, it is clear that the TPS65023 power supply will meet the power requirements, with at least
8% headroom on each output.
Sub-System
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Table 4.5: Power Requirements for the Processor and its Peripherals
U
ARM Processor
DDR2 SDRAM
NAND Flash
Ethernet PHY
USB Transceiver
USB Host and OTG Port
Video Transmitter
Audio Codec
USB Converter
Total Current
Component
TI AM3517
Winbond W971GG6JB
Micron MT29F2G16AADWP
National Semiconductor DP83640
SMSC USB3320
N/A
TI TFP410
TI TLV320AIC23B
FTDI FT4232H
Supply Current (mA)
1.2V 1.8V 3.3V 5V
1500 300
300
502
45
100
58
34
1500
250
36
70
100
1500 930
865
1500
If one then calculates the power consumption for each rail (including the 5V), and adds them together, the total
power consumption for the processor sub-system can be determined (15.4W, assuming 90% supply efficiency).
Furthermore, this means that the 5V switch-mode power supply must be able to handle 3.1A. Although one
could probably use a 3A supply to provide the 3.1A, the supply would run hot and shorten its lifespan. Hence,
a 6A switch-mode power supply is used to provide the 5V.
53
The power-up sequence of the processor power supply works as follows:
∙ The user presses the power push-button, which is detected by the push-button controller (on the Power
Supply Management schematic), and the PROC SUPPLY EN port (on this sheet) goes high.
∙ This switches on the 5V switch-mode supply, which provides power to the TPS65023 supply inputs
(VINDCDCx) and control circuitry.
∙ Channel 3 (DCDC3) turns on immediately, providing 1.8V to the SDRAM and processor.
∙ Channel 2 turns on 5ms after Channel 3, providing 3.3V to the processor’s I/O circuitry and other
peripherals.
∙ Channel 1 switches on 5ms later, supplying the processor core with 1.2V.
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∙ Finally, the two LDO regulator channels turn on 5ms after Channel 1, providing 1.8V to the digital PLL
circuitry within the processor, and 3.3V to the USB circuitry within the processor.
ap
e
The sequencing of the power supplies is not arbitrary; the processor has very strict requirements regarding the
sequence in which its supplies must be powered up [37]. The 5ms delays in the sequencing of each supply
were achieved using RC delay circuits at the supply enable inputs (DCDCx EN and LDO EN).
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The processor power requirements in Table 4.5 can be combined with the FPGA power requirements in Table 4.3 to determine the board’s total power consumption. Again, these calculations assumed that the power
supplies were 90% efficient, as per the calculated efficiency that was given in Chapter 3 (see Section 3.3.7).
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Table 4.6: Rhino Power Consumption
15.4W
23.4W
57.1W
95.8W
38.7W
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Processor and peripherals
FPGA and peripherals (excluding FMC)
FMC mezzanine cards
Total power (with FMC)
Total power (without FMC)
4.2.44 Power Monitors
Both the voltage and the current of all power rails within Rhino are monitored. This is achieved by placing
5 milli-ohm current sensing resistors on the output of each power supply, and then using INA219 power
monitors to measure the output voltage, and the voltage across the current sensing resistor. Even though each
INA219 can measure only one supply rail, this is actually an advantage, as it allows the INA219 to be placed
directly at the current sensing resistor at the power supply output.
The processor communicates with the INA219 power monitors over a common power-management I2 C bus.
Each INA219 can be programmed with the value of the current sensing resistor, allowing it to calculate the
actual current and power.
4.2.45 Temperature Monitor and Fan Controller
A 4-channel temperature monitor is used to measure the temperature of the FPGA, the processor and the ambient air. Since neither the FPGA nor the processor contain internal temperature diodes, external temperature
54
sensors must be glued onto the FPGA and processor heatsinks. A third temperature sensor must be placed inside the box, near the air inlet, to measure the ambient air temperature. All three of these temperature sensors
connect to the board with standard two-pin Molex KK-style connectors.
The processor is able to read the temperatures, and program warning conditions, via the common powermanagement I2 C bus. By design, the processor should program the temperature monitor, on power-up, to
generate a warning condition if the FPGA temperature rises above 70∘ C. If such a condition does occur, the
ALERT output pin goes low, resetting the FPGA.
The TC654 2-channel fan controller is used to control two 12V case fans. It uses slow pulse-width modulation
(at approximately 30Hz) to control the fan speed, which can be set by the processor using the common powermanagement I2 C bus [48]. The fan controller measures the actual fan speed by counting current pulses, which
the processor can read using the same I2 C bus. If a fault, such as a locked rotor, does occur, the fan controller
immediately alerts the processor using its FAULT output, which is wired to a processor GPIO pin.
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4.2.46 Power LEDs
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To
Five power LEDs are used to indicate whether the four FPGA switch-mode power supplies and the processor
5V supply are turned on. Furthermore, two power LEDs are connected to the “power good” outputs of the two
FPGA LDO regulators (see schematic sheet 55). This allows the user to immediately determine which power
supplies are on and which are off.
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4.2.47 Mounting Holes and Fiducials
of
The micro-ATX PCB mounting holes and the FMC mezzanine card mounting holes are shown on this schematic.
The fiducials used to align the PCB layers have also been shown for completeness.
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4.3 C LOCKING THE S PARTAN -6 FPGA
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The Spartan-6 has special, dedicated, clock pins (called “global clocks”) that should be used for all clock input
signals. These pins are connected to special global clock buffers within the FPGA (BUFGMUXs), which drive
the clock signals onto low-latency clock routing networks [49]. This ensures that the clock signal experiences
minimum skew as it travels through the FPGA.
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A list of all the clock input signals to the FPGA is given in Table 4.7. Note that each FMC interface has six
clock lines, as four of the data pairs (0, 1, 17 and 18) can also be used as source-synchronous clocks. As one
can see, there are 13 differential clocks. However, the Spartan-6 can only support 8 simultaneous differential
clocks, due to limitations on clock routing within the FPGA, as will be explained later. Therefore, some of
the differential clocks are converted to single-ended clocks (see fourth column in the table).
Even though the Spartan-6 has 32 global clock inputs (GCLKs), not all of these clocks can be used simultaneously. The reason for this lies in how the global clock signals are routed within the FPGA. Each global clock
is routed to four clock multiplexers (BUFGMUXs). The clock signal is then routed from the output of the
BUFGMUX, via a low-skew clock network through FPGA, to the user logic. This is illustrated in Figure 4.5.
The GCLK pins are shown at the top of the diagram, with their connections to the BUFGMUXs on the righthand side. This diagram shows the connections for just I/O Banks 0 and 1. A similar routing network exists
for Bank 2 and 3. No GCLKs are available on I/O Banks 4 and 5. Since this means that there are a total of
just 16 BUFGMUXs, only 16 of the 32 global clock inputs (GCLKs) can be used at once.
Furthermore, each GCLK is wired to only four BUFGMUXs, meaning that only certain combinations of the
55
Table 4.7: List of Clock Inputs to the Spartan-6 FPGA on Rhino
Differential?
Yes
Yes
Yes
Yes
Yes
Yes
Convert to Single-Ended?
No
No
No
No
Yes
Yes
FMC1
FMC1
FMC1
FMC1
FMC1
FMC1
FMC1
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
Yes
Yes
Yes
System Clock
SYS CLK
Yes
No
PTP Clock
IEEE1588 CLK
No
Processor Bus
PROC BUS CLK
No
1Gbps Eth PHY
GMII TX CLK
GMII RX CLK
-
C
ap
e
LA 0 CC
LA 1 CC
LA 17 CC
LA 18 CC
CLK0 M2C
CLK1 M2C
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Clock Signal
FMC0 LA 0 CC
FMC0 LA 1 CC
FMC0 LA 17 CC
FMC0 LA 18 CC
FMC0 CLK0 M2C
FMC0 CLK1 M2C
To
Sub-System
FMC0
-
of
No
No
-
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GCLKs can be used at once. For example, by looking at Figure 4.5, it is clear that global clocks GCLK19 and
GCLK11 can never be used at the same time, as they are both connected to the same horizontal clock lines,
and hence are connected to the same input pins of the same BUFGMUXs. In fact, in turns out that no more
than 8 differential clocks can be used at once, as the differential clocks are always routed using the “positive”
GCLK pin, and there are always BUFGMUX conflicts if more than 8 “positive” GCLK pins are used. Hence
Rhino only used 8 differential clocks; the rest are converted to single-ended.
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Tables 4.8 and 4.9 shows how the clock sources on Rhino have been connected to the GCLK pins, so that
there is no conflict in routing to the BUFGMUXs. Note that all 16 BUFGMUXs are used on Rhino. Also note
that GCLK 20, in Table 4.9, has two clock sources: FMC1 CLK1 M2C or FMC1 LA 18 CC. Due to a lack
of BUFGMUXs, only one of these clock sources can be used at a time. The choice is made by selectively
installing 0 ohm resistors. However, this should not cause any problems, as it is highly unlikely that both
FMC1 CLK1 M2C and FMC1 LA 18 CC will be used as clock lines simultaneously by the same FMC card.
All the information regarding the Spartan-6 clocks that was presented in this section is summarised in the
block diagram in Figure 4.6. This diagram shows all the clock sources connected to the appropriate global
clock (GCLK) pins on the FPGA.
The reader should now have a full understanding of the schematic-level design of Rhino. This chapter began
by developing the detailed sub-system diagram for Rhino. This diagram explained the four major sub-systems
within Rhino (FPGA, processor, debugging and power management), and how they fit together. This subsystem diagram was then transferred to the schematics, the details of which were also discussed. This chapter
then ended off with an overview of the clocking infrastructure for the Spartan-6 on Rhino.
56
Chapter 1: Clock Resources
A graphical representation of the conflicting BUFGMUX inputs is shown in Figure 1-2 and
Figure 1-3.
X-Ref Target - Figure 1-2
GCLK4
GCLK5
BUFIO2_X3Y11
GCLK6
BUFIO2_X3Y10
GCLK7
BUFIO2_X3Y13
GCLK9
GCLK8
BUFIO2_X3Y12
BUFIO2_X4Y18
BUFIO2_X4Y19
GCLK10
GCLK11
BUFIO2_X4Y21
BUFIO2_X4Y20
GCLK12
BUFIO2_X4Y27
GCLK13
GCLK14
BUFIO2_X4Y26
BUFIO2_X4Y29
GCLK15
Bank 1
BUFIO2_X4Y28
GCLK16
GCLK17
BUFIO2_X2Y27
GCLK18
BUFIO2_X2Y26
BUFIO2_X2Y29
BUFIO2_X2Y28
GCLK19
Bank 0
BUFGMUX_X2Y1
To
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n
BUFGMUX_X2Y2
BUFGMUX_X2Y3
BUFGMUX_X2Y4
BUFGMUX_X3Y5
BUFGMUX_X3Y6
e
BUFGMUX_X3Y7
ap
BUFGMUX_X3Y8
UG382_01_121709
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Figure 4.5: InternalFigure
routing1-2:
of GCLKs
to BUFGMUXs
the Spartan
6, for1 Bank 0 and Bank 1
BUFGMUX
Connectionswithin
for Bank
0 and Bank
(Image taken from the Xilinx Spartan-6 FPGA Clocking Resources Guide [49])
Bank 0
GCLK 19: FMC1 LA 0 CC
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BUFGMUX
BUFGMUX X2Y1
BUFGMUX X2Y2
BUFGMUX X2Y3
BUFGMUX X2Y4
BUFGMUX X3Y5
BUFGMUX X3Y6
BUFGMUX X3Y7
BUFGMUX X3Y8
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Table 4.8: Shared BUFGMUXs for Global Clocks on Banks 0 and 1 on Rhino
GCLK 10: 1588 CLK
GCLK 17: FMC1 LA 1 CC
GCLK 15: FMC1 LA 17 CC
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Bank 1
GCLK 8: PROC CLK
GCLK 6: FMC0 CLK0 M2C
GCLK 13: SYS CLK
GCLK 4: FMC0 CLK1 M2C
Table 4.9: Shared BUFGMUXs for Global Clocks on Banks 2 and 3 on Rhino
14
BUFGMUX
BUFGMUX X2Y9
BUFGMUX X2Y10
BUFGMUX X2Y11
BUFGMUX X2Y12
BUFGMUX X3Y13
BUFGMUX X3Y14
BUFGMUX X3Y15
BUFGMUX X3Y16
Bank 2
GCLK 3: FMC0 LA 0 CC
Bank 3
GCLK 26: GMII TX CLK
GCLK 1: FMC0 LA 1 CC
GCLK 31: FMC0 LA 17 CC
www.xilinx.com
GCLK 29: FMC0 LA 18 CC
GCLK 24: GMII RX CLK
GCLK 22:
FMC1FPGA
CLK0
M2C Resources
Spartan-6
Clocking
UG382 (v1.2) January 4, 2010
GCLK 20: FMC1 CLK1 M2C
or FMC1 LA 18 CC
57
Spartan-6 FPGA
FMC1_LA_0_CC_N/P
GCLK19
FMC1_LA_1_CC_N/P
FMC1_LA_17_CC_N/P
GCLK15
~
GCLK6
r-
~
FMC0_CLK0_M2C_N/P
Diff to
single
FMC0_ CLK1_M2C_N/P
PROC_CLK
of
C
GCLK8
FMC1
e
1588_CLK
GCLK10
FMC0
Bank 1
To
GCLK4
Diff to
single
w
n
SYS_CLK_N/P
GCLK13
ap
Bank 0
GCLK17
FMC0_LA_0_CC_N/P
FMC0_LA_1_CC_N/P
FMC0_LA_17_CC_N/P
FMC0_LA_18_CC_N/P
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GCLK1
GCLK31
GCLK29
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v
Bank 2
ty
GCLK3
U
l
-
GCLK22
GCLK20
Bank 3
GCLK26
GCLK24
~ -
Diff to
single
FMC1 _M2C_CLK0_N/P
Diff to
single
FMC1 _M2C_CLK1_N/P
Diff to
single
FMC1 _LA_18_CC_N/P
GMII_TX_CLK
GMII_RX_CLK
KEY
1:=
Differential clock
Single-ended clock
Figure 4.6: Rhino’s clock sources, and how the connect to the FPGA
58
1
CH A P T E R 5
R HINO PCB L AYOUT AND R OUTING
e
To
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The previous chapter described the schematic-level design of the Rhino hardware. All the components, and
the connections between them, were defined in the schematics, and the reasons for the main design decisions
were explained in the text. However, this only constitutes half of the design of a PCB. The second half of
the design process involves placing those components in appropriate places on a PCB, and routing the traces
between them in such a manner that signal integrity is maximised and interference is minimised.
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It should be mentioned at this point that the actual routing of the Rhino PCB was outsourced to SunCad
Designs, a professional PCB design company 1 . The main reason for this was to accelerate the design process,
as they are well experienced in PCB design and hence able to route a PCB very quickly. The result was that
Rhino went from concept to working system in just 12 months.
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Even though the actual routing of Rhino was outsourced, much other PCB-level work was required to ensure
that the routing went as planned. The board stackup and routing rules had to be defined, and the major
components had to be placed, before the design could be handed over to SunCad, who were responsible
purely for the fairly mechanical job of routing the board. Furthermore, once the board was fully routed,
signal integrity simulations had to be performed on all high-speed buses to ensure overshoot, undershoot and
crosstalk were within limits. This chapter attempts to describe all these PCB design processes that took place
before the design was handed over to SunCad, and after it was received back.
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5.1 T HE T HEORY BEHIND ROUTING H IGH -S PEED D IGITAL S IGNALS
Rhino contains a number of high-speed buses, as listed in Table 5.1. Since one normally only considers
transmission line effects when the PCB trace is a significant fraction of a wavelength, most of these buses
(with the exception of the CX4 traces) do not seem fast enough to warrant concern over high-frequency
effects. The second fastest bus is the DDR3 SDRAM data bus, which runs at 800MHz, giving a wavelength
is 375mm, much longer than the PCB itself. However, one must remember that these are digital signals, and
not analogue signals. Therefore, it is the switching times (also known as rise/fall times) that determine the
high-frequency components of the signal, and not the square-wave frequency [50]. These switching times, and
the corresponding effective frequencies and wavelengths, are shown in Table 5.1 too. Since these effective
wavelengths are similar to the expected PCB trace lengths, transmission line effects must in fact be considered
when routing Rhino.
1
http://www.suncad.com
59
Table 5.1: Rhino High-Speed Digital Buses
Sub-System
DDR3 SDRAM
DDR2 SDRAM
FMC
1Gbps Eth PHY
CX4 10Gbps Eth
Processor-FPGA Bus
Bus
Data
Address
Data
Address
Data
GMII
XAUI
All
Bus Frequency
800MHz
400MHz
333MHz
166MHz
400MHz
125MHz
3.125GHz
83MHz
Switching Time
0.3ns
0.3ns
0.9ns
1.8ns
0.5ns
1ns
200ps
2ns
Eff. Frequency
3.3GHz
3.3GHz
1.1GHz
555MHz
2GHz
1GHz
5GHz
500MHz
Eff. Wavelength
44mm
44mm
132mm
261mm
72mm
144mm
29mm
289mm
5.1.1 What Happens at High Frequencies?
e
To
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At high frequencies, traces on a PCB no longer act as simple conductors, but rather exhibit transmission line
properties. According to Hall, Hall and McCall [50], this occurs if the signal trace is more than 10% of the
wavelength of the signal. At an effective frequency of 1GHz, 10% of the wavelength is just 14mm, shorter
than most PCB traces. If the PCB is not carefully designed, the high frequency effects can cause a number of
problems which degrade the signal integrity, such as reflections, overshoot, cross-talk and switching noise.
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ap
While designing Rhino, much
care
wasExample
taken to2.2:
match
characteristic
impedance
traces reflections
to input and
Figure
2.13:
Lattice
diagram used
to calculateofmultiple
for output
an
underdriven transmission
impedance of ICs. The characteristic
impedanceline.
of a PCB trace is defined as the ratio of the voltage and
current waves at any point
along the trace [50], and is determined by the width and height of the trace and the
The response of the lattice diagram is shown in the lower corner of Figure 2.13. A computer
distance to the nearest simulation
ground orofpower
plane. isIfshown
the characteristic
of theNotice
tracehow
is not
the response
in Figure 2.14impedance
for comparison.
thematched to
reflections
give
"stair-step" appearance
at the
evenoccur.
thoughThe
the result
the output impedance of
the driver
IC,theorwaveform
the inputaimpedance
of the receiver
IC,receiver,
reflections
unloaded
output
of
the
voltage
source
is
a
square
wave.
This
effect
occurs
when
the
source
is a distorted square wave, with overshoot, undershoot, stair-step or ringing characteristics. If the stair-step
impedance Zs is larger than the line impedance Zo and is referred to as an underdriven
(seen in Figure 5.1) or transmission
ringing (shown
line.in Figure 5.2) is large or continues for a long period of time, it may also
cause the receiver to incorrectly detect the logic 1 or 0.
Figure 2.14: Simulation of transmission line system shown in Example 2.2, where the
linewaveform
impedancethat
is less
thanifthe
impedance is
(underdriven
transmission
line).
Figure 5.1: The stair-step
occurs
thesource
line impedance
less than the
source impedance
(Image taken from [50])
However, incorrect impedance matching is not the only cause of signal integrity degradation when dealing
with high-speed digital
signals.2.3:Crosstalk
is the coupling
energy from
one conductor
Example
Multiple Reflections
for anofOverdriven
Transmission
Line. to another, due
to their electromagnetic fields interacting with one another [50]. Crosstalk has two detrimental effects on
60
-.
Figure 2.15: Example 2.3: Lattice diagram used to calculate multiple reflections for an
overdriven transmission line.
".
u.
,
~
••
~
-"
1., _
•g•
-
....
..
'.0 •
•
,;
•
,•
'"
••
_i.O •
'-!.loodi
;
•
••
rlm •• ~
(Image taken from [50])
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Figure 5.2: The
Figure 2.16: Simulation of transmission line system shown in Example 2.3 where the
impedance
greaterifthan
the source
impedance
(over-driven
line).
ringing line
waveform
thatisoccurs
the line
impedance
is greater
than thetransmission
source impedance
ap
e
To
Next, consider the transmission line structure depicted in Figure 2.17. The structure consists
of two segments of transmission line cascaded in series. The first section is of length X and
has a characteristic impedance of Zo1 ohms. The second section is also of length X and has
an impedance of Zo2 ohms. Finally, the structure is terminated with a value of Rt. When the
neighbouring traces: it induces noise onto those traces and can even change their characteristic impedance.
signal encounters the Zo1/Zo2 impedance junction, part of the signal will be reflected, as
However, these impedance
changes
signalcoefficient,
pattern dependent.
Since
the
patterns as
aregoverned
generally
governed
by the are
reflection
and part of the
signal
willsignal
be transmitted,
by the
transmission
coefficient: changes. However, one special case is differential signals,
unknown, it is impossible
to predict
the impedance
C
where the two signals always have opposite phase. In this case, the exact effective characteristic impedance
(called the odd-mode impedance) can be calculated.
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of
A final cause of signal integrity problems in high-speed circuits is split-planes. Split-planes occur when a PCB
power layer is divided up into a number of copper fills (or planes), and each of these planes are connected to a
different supply voltage. If this split-plane layer is used as a reference plane, and a trace on an adjacent layer
traverses the split, then the characteristic impedance of the trace will be changed. Hall, Hall and McCall [50]
explain that this is because the return current, which is induced in the power plane as the signal current travels
down the trace, is unable to traverse the gap, and is forced to find an alternative path, changing the impedance
in an unpredictable way. Therefore, split power planes are never used as reference planes on Rhino.
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5.1.2 How can these Problems be Avoided?
There are a number of industry-recognised “good practices” that help to minimise reflections and crosstalk in
high speed digital systems. The main rules of thumb that were followed when developing the routing rules
for Rhino are described here. If the source of the guideline is not specified, then it was taken from Hall, Hall
and McCall’s book on high-speed digital design [50]. Due to the additional cost of manufacturing a PCB with
impedance-controlled traces, these guidelines were only followed for the high-speed signals on Rhino (those
listed in Table 5.1). Slow signals were routed as ordinary, non-impedance-controlled traces.
Match Trace Impedance to Termination Resistors
The output impedance of the driver IC must match the trace characteristic impedance to minimise reflections
at the source. Similarly, the receiver termination impedance (either inside or outside the receiver IC package)
must match the characteristic impedance to minimise reflections at the load.
In the case of differential pairs, the effective characteristic impedance (i.e. the odd-mode impedance) must
be calculated, and the pair terminated with a single resistor between them, with impedance equal to twice the
odd-mode impedance of each trace.
61
Reduce Drive Strength
In cases where exact impedance matching is difficult, source termination resistors can be used to reduce drive
strength. This reduces the switching times of the signal, and hence reducing the high-frequency component
of the signal. This helps to prevent overshoot, undershoot and crosstalk, but it is not always practical.
Use Differential Signals where Possible
Critical nets, such as clocks, should be differential signals. These nets must be routed close together to ensure
strong coupling, which reduces EMI and improves noise immunity.
Avoid Split Planes
w
n
Impedance-controlled signals should never cross splits in the reference plane, as this breaks the current return
path. If split planes are used, they should be arranged so that no signals on adjacent layers cross the splits. If
this cannot be avoided, then capacitors must be used to stitch the split planes together, but this is not ideal.
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Ensure Adequate Trace Separation
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The general rule of thumb when routing single-ended signals is that the edge-to-edge spacing between the
traces should be twice the trace width, in order to keep crosstalk down to an acceptable level [51]. This is
commonly known as the 3w rule, as the centre-to-centre spacing of the traces is three times the trace width (w).
C
Minimise Distance between Trace and Reference Plane
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Reduce Coupling between Layers
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Another method of minimising crosstalk is to reduce the distance between the trace and the reference plane,
by making the dielectric material as thin as possible [52]. This approach is however limited by manufacturing
capabilities.
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v
To avoid coupling between traces on different layers, critical signal layers should be separated by ground or
power planes. If this is not possible, then traces on adjacent signal layers should be routed orthogonally to
each other.
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5.1.3 Calculating Characteristic Impedance
In order to match the characteristic impedances of the traces to the source and load terminations, the impedance
of the traces need to be calculated. Different formulas are used for microstrip traces (traces on external layers)
and stripline traces (traces on internal layers). Furthermore, if a signal is routed as a differential pair, the
coupling between the traces decreases the effective odd-mode impedance, which also needs to be calculated.
The formulas shown here are taken from the IPC handbook IPC-D-317A, Design Guidelines for Electronic
Packaging Utilizing High-Speed Techniques [53], although their derivation has not been shown. All images
are courtesy of Mantaro Product Development Services [54].
Note that in all the formulas Z0 is characteristic impedance; Zd is differential impedance (which is twice oddmode impedance); w is trace width; t is trace thickness; h is trace height above/below reference plane; d is
distance between inner edges of a differential pair; and 𝜀r is relative dielectric constant (typically 4.3 for FR-4
PCB).
62
Impedance of a Microstrip
87
𝑍0 = √
ln
𝜀𝑟 + 1.41
(
5.98ℎ
0.8𝑤 + 𝑡
)
Figure 5.3: Parameters used when calculating the characteristic impedance of a microstrip
5.98ℎ
0.8𝑤 + 𝑡
)(
(
))
𝑑
1 − 0.48 exp −0.96
ℎ
To
(
of
C
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e
174
𝑍𝑑 = √
ln
𝜀𝑟 + 1.41
w
n
Impedance of a Differential Microstrip
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si
60
𝑍0 = √ ln
𝜀𝑟
(
1.9(2ℎ + 𝑡)
0.8𝑤 + 𝑡
)
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Impedance of a Stripline
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Figure 5.4: Parameters used when calculating the odd-mode impedance of a differential microstrip
Figure 5.5: Parameters used when calculating the characteristic impedance of a stripline
Impedance of a Differential Stripline
120
𝑍𝑑 = √ ln
𝜀𝑟
(
1.9(2ℎ + 𝑡)
0.8𝑤 + 𝑡
)(
(
1 − 0.347 exp −2.9
63
𝑑
2ℎ + 𝑡
))
Figure 5.6: Parameters used when calculating the odd-mode impedance of a differential stripline
5.2 P LACEMENT OF M AJOR C OMPONENTS
To
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n
The first step in the PCB design process was to position the major components on the board. These included
the FPGA, processor, SDRAM ICs and all the connectors. These components were placed in such a way
as to minimise trace length and reduce the crossing-over of traces. Minimising trace length helps to reduce
crosstalk on buses, while reducing the number of crossovers helps to lower the layer count, making the PCB
cheaper to manufacture.
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The PCB was designed to meet the microATX motherboard specification. As a result, the PCB measures
244mm by 244mm, with all the connectors placed along one edge, and the mounting holes in the appropriate
positions. The placement of the major components is shown in Figure 5.7.
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In this diagram, the PCB has been divided up into 5 different regions: the four edges and the centre. In each of
the edge regions, the components may be placed in any order along that edge, but they must be placed along
the specified edge. Similarly, the components in the centre region may be placed anywhere near the centre of
the board. The placement of the major components was specified using regions, rather than absolute positions,
in order to give SunCad as much flexibility as possible for the placement and routing, while still ensuring that
the placement of connectors was compatible with the proposed enclosure design (which shall be discussed in
Chapter 8). Note that all components and the microATX PCB have been drawn to scale, showing their correct
relative sizes; however, the relative distances between components is meaningless in this diagram, as the final
placement shall be decided by SunCad.
The advantage of this particular arrangement is that it minimises the crossing of PCB traces (which are called
nets before they are actually routed). With the FPGA aligned with the centre of the two FMC connectors, the
nets between the FMC connectors and the FPGA can be routed with minimal crossing. This is important, as
the two FMC buses account for more PCB traces than any other bus. This particular placement of the FPGA
(halfway between front and rear, and slightly to the left) also allows for easy routing to the rear connectors.
Since all the FPGA connectors (1Gbps Ethernet and CX4) are on the left half of the PCB rear edge, traces can
be routed between the FPGA and these connectors without crossing any processor traces.
The placement of the processor similarly has many advantages. By placing it near the FPGA, the processorFPGA bus traces can be kept very short. Most of the processor connectors are on the right half of the rear edge
(HDMI video, three audio jacks, USB host ports, USB On-the-Go, RS-232 header), allowing easy connection
from the processor to these connectors without crossing any FPGA nets. Lastly, by placing the FPGA and
processor SDRAM ICs along the outer edges of the FPGA and processor respectively, the SDRAM traces can
be kept short, and away from FMC and other connector nets. For these exact reasons, SunCad decided to keep
the relative positions of components exactly as was suggested, with only the distances between neighbouring
components changing for the final layout.
64
~
i n D DDnnnnn~D, i
Fujitsu
microGiGaCN
CX4
Pulsejack
100mbps
RJ45
Belfuse
0826-1X1T
Gigabit
Ethernet
FCI
1002944
9 HDMI
Fujitsu
microGiGaCN
CX4
Tyco
Stacked
USB-A
Tyco
USB-B
Conn
Molex MiniAB OTG
(3x) CUI SJ-3523
Stereo jack
Sullins 5x2
Header (RS-232)
I
I Place along rear edge
I
I
------------------------------------------------
D
D
2
Processor
LEDs
DDR2
SDRAM
DB
D
D
FPGA Temp
Sensor Header
Proc Temp
Sensor Header
D
Molex Fan
Header
D
Molex Fan
Header
D
Amb Temp
Sensor
Header
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Place in centre of board
DDR2
SDRAM
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DDR3
SDRAM
AM3517
ARM
Processor
Spartan-6 FPGA
D
Molex 039281043
Minifit Jr
To
~
DDR3
SDRAM
Place along side edge
8 User
LEDs
-------------------------------,
Place along side edge
-------
of
C
Place along front edge
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FMC HPC Connector
(leave enough space between
connector and PCB edge for
mezzanine card, as per spec)
1mm
apart
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FMC HPC Connector
(leave enough space between
connector and PCB edge for
mezzanine card, as per spec)
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Kyocera 5638 SD
Card Connector
[--r---[----u---i
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Molex 7x2
Front Panel
Header
microATX PCB (244mm x 244mm)
I
I
I
I
I
Component sizes and board dimensions are
accurately scaled. However, the relative distances
between components are not accurate.
Molex 10x2
GPIO
Header
7 Power
Supply
LEDs
Sullins 7x2 Header
(JTAG)
Place anywhere on the board
L _____________
I
I
I
I
I
..J
Figure 5.7: Diagram showing placement of major components on the Rhino PCB
5.3 T HE PCB S TACKUP
The Rhino PCB consists of 16 layers, of which half are ground and power planes. This was done to ensure that
every high-speed trace was sandwiched between two ground planes, guaranteeing tight impedance control and
65
hence good signal integrity. The complete PCB stackup is shown in Figure 5.8. In the stackup diagram, the
top and bottom layers are coloured orange, the internal high-speed signal layers are green and the non-critical
layers (i.e. layers with no high-speed traces) are yellow. Ground and power planes have been left white. As
per standard PCB construction methods, core and prepreg (both shown in grey in the diagram) are alternatively
placed between the copper layers. Core is a solid sheet of FR-4 fibreglass with copper stuck to both sides,
while prepreg (short for pre-impregnated) is a fibreglass weave with an uncured resin bonding agent that sticks
the core layers together, both of which are dielectric materials.
Looking at the “Net Classes to Route on Layer” column in Figure 5.8, it is evident that a number of different
types of impedance-controlled traces are used in the Rhino PCB, each with different impedance requirements.
To make the design of the PCB simpler, the nets were arranged into different net classes, as shown in Table 5.2.
Table 5.2: Rhino Net Classes for PCB Routing
Impedance Requirement
No impedance control.
50 ohm single-ended impedance.
100R DIFF
100 ohm differential impedance. No
single-ended impedance requirement.
50R SNGL 100R DIFF
100 ohm differential impedance AND
50 ohm single-ended impedance. The
differential requirement takes priority.
90 ohm differential impedance. No
single-ended impedance requirement.
Nets in the Class
All other nets
DDR3 SDRAM address and data. All
DDR2 SDRAM nets. GMII bus to
1Gbps Ethernet PHY.
DDR3 SDRAM clocks and strobes.
CX4 10Gbps Ethernet data traces.
Traces to the RJ45 Ethernet connectors
and HDMI video connector.
FMC connectors.
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To
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Class
UNCONTROLLED
50 OHM
Data nets (DM and DP) to all USB connectors.
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90R DIFF
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The 50R SNGL 100R DIFF class used for the FMC connectors is an interesting one. Since the FMC data lines
can be used as either single-ended or differential signals, the nets are required to have 50 ohm characteristic
impedance when operating in single-ended mode and 100 ohm differential impedance when operating in
differential mode. However, this is not actually possible. If the traces have 50 ohms impedance when operating
in single-ended mode, then when they operate in differential mode, the odd-mode impedance will be less than
50 ohms (due to coupling between the pairs), resulting in a differential impedance of less than 100 ohms.
To solve this, the pairs are moved slightly further apart so that the impedance change in differential mode
is reduced, and the trace widths and heights are chosen to minimise the combined impedance error for both
single-ended and differential modes.
As has been mentioned, all internal high-speed signal layers are sandwiched between two ground planes.
Therefore, to calculate the trace width, spacing and dielectric thickness to give the required characteristic
impedances shown in Table 5.2, the formulae given in Section 5.1.3 were used. Note that the microstrip
formulae were used for the top and bottom layers, while the stripline formulae were used for the internal
layers. The reference planes used in each calculation are shown in the “Reference Plane” column of the
stackup diagram (Figure 5.8). Once the trace width and spacing were determined to the nearest mil, the actual
characteristic impedance was calculated and given in the last column. For example, all differential pairs in the
100R DIFF class on layer 3 must be routed as 4mil wide traces with a 7mil gap between the traces. This will
give a calculated differential impedance of 101.2 ohms.
66
67
L16
L15
L14
L13
L12
L11
L10
L9
L8
L7
L6
L5
L4
L3
L2
Components; 90 ohm pairs
L1
Total board thickness (mils)
Components; solder side; 90 ohm pairs
Prepreg 3.5mil
Ground plane
Core 6.5mil
100 ohm pairs; 50 ohm single ended
Prepreg 6.5mil
Ground plane
Core 6.5mil
100 ohm pairs; 50 ohm single ended
Prepreg 6.5mil
Ground plane
Core 3mil
Power plane
Prepreg 3.5mil
Non-critical nets, power nets
Core 3.5mil
Non-critical nets, power nets
Prepreg 3.5mil
Power plane
Core 3mil
Ground plane
Prepreg 6.5mil
100 ohm pairs; 50 ohm single ended
Core 6.5mil
Ground plane
Prepreg 6.5mil
100 ohm pairs; 50 ohm single ended
Core 6.5mil
Ground plane
Prepreg 3.5mil
Description
Layer
To
w
n
4
4
4
5
50R_SNGL_100R_DIFF
100R_DIFF
50_OHM
5
4
4
4
5
4
4
4
90R_DIFF
50_OHM
100R_DIFF
CX4
50R_SNGL_100R_DIFF
50_OHM
100R_DIFF
50R_SNGL_100R_DIFF
e
UNCONTROLLED
ap
C
5
50_OHM
4
4
UNCONTROLLED
4
5
50_OHM
100R_DIFF
4
100R_DIFF
50R_SNGL_100R_DIFF
4
5
50_OHM
4
4
100R_DIFF
CX4
4
50R_SNGL_100R_DIFF
4
90R_DIFF
Track Width (mil)
50R_SNGL_100R_DIFF
Nets Classes to Route on Layer
Figure 5.8: Stackup of the Rhino PCB
95.1
1.4 L13
3.5
1.4
6.5
0.7 L11, L13
6.5
1.4
6.5
0.7 L9, L11
6.5
1.4
3
1.4
3.5
1.4
3.5
1.4
3.5
1.4
3
1.4
6.5
of
0.7 L4, L6
6.5
1.4
6.5
0.7 L2, L4
6.5
1.4
3.5
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Reference Plane
1.4 L2
Material Thickness (mil)
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1 oz Copper Foil
1 oz
0.5 oz
1 oz
0.5 oz
1 oz
1 oz
1 oz
1 oz
1 oz
1 oz
0.5 oz
1 oz
0.5 oz
1 oz
1 oz Copper Foil
Copper Thickness
6
6
4
7
7
6
7
6
7
6
7
7
6
6
6
4
Diff Pair Spacing (mil)
49.3R single
100.1R diff
100.1R diff, 55.1R single
92.6R differential
49.5R single
101.2R diff
101.2R diff
99.1R diff, 54.9R single
49.5R single
101.2R diff
99.1R diff, 54.9R single
49.5R single
101.2R diff
99.1R diff, 54.9R single
49.5R single
101.2R diff
101.2R diff
99.1R diff, 54.9R single
49.3R single
100.1R diff
100.1R diff, 55.1R single
92.6R differential
Calculated Impedance
There is however scope for cost reduction in this stackup. Layer 6, a ground plane, has been placed adjacent
to layer 7, a power plane. The reason that these two reference planes were placed on adjacent layers is that
layer 7 is a split power-plane. Since a number of the high-speed signals on layer 5 cross the split on the plane,
there might have been signal integrity problems. To prevent this, a ground plane was inserted between layers
5 and 7. The same goes for the split power-plane on layer 10 and the high-speed signals on layer 12 (here, the
ground plane was inserted on layer 11).
However, if some of the power planes on layers 7 and 10 were moved to non-critical layers 8 and 9, and one
or two of the existing ground plane layers were converted to solid power plane layers, it would be possible
to convert the split power-planes on layers 7 and 10 to solid power planes. This would allow layers 7 and 10
to be used as reference planes for signal layers 5 and 12, allowing layers 6 and 11 to be removed from the
stackup. Based on the quotes that were received for the Rhino PCB, reducing the layer count from 16 down
to 14 layers should reduce the PCB manufacturing cost by at least 20%.
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5.4 D EFINING THE ROUTING RULES FOR R HINO
To
Before the board was routed by SunCad Designs, a number of trace width, length and spacing rules were
defined. This was done to ensure minimal crosstalk, minimal volt drop on the power lines and a no cuttingedge manufacturing requirements (which can be expensive).
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5.4.1 Minimum Trace Width
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All traces must be 4 mils or wider. If a trace is less than 4 mils wide, the manufacturing costs increase
dramatically, due to the difficulty in manufacturing such thin traces. The exact width of impedance-controlled
traces are specified in the stackup diagram, and the exact width of the power nets is discussed in the next
section. For all non-impedance-controlled and non-power nets, 4 mils was chosen as the standard trace width.
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5.4.2 Widths of Power-Carrying Traces
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Although all the power supply rails were implemented as split planes on layers 7 and 10 of the PCB, sometimes
standard nets are required to carry substantial amounts of current (e.g. the output of the fan controllers).
Therefore, all nets in the Rhino PCB that carry more than 50mA of current were defined as power nets. The
acceptable voltage drop for each power net was then determined (usually 10mV). From this, the required trace
width for the power net could be calculated, by ensuring that:
a.) the temperature rise along the trace did not exceed 10∘ C
b.) the voltage drop along the trace was within the defined limits
The voltage drop and temperature rise along each trace were determined from the relevant plots in IPC-2221A,
Generic Standard on Printed Board Design [55].
5.4.3 Inter-trace Spacing
Figure 5.9 shows a typical setup of traces on a PCB. The green lines indicate differential pairs, while the red
lines indicate single-ended nets.
The dimensions in the diagram can be defined as follows:
A = Distance between the P and N traces in a single differential pair
B = Distance between adjacent differential pairs
C = Distance between a differential pair and a neighbouring single-ended net
D = Distance between adjacent single-ended nets
68
A
B
C
D
Figure 5.9: Definition of the inter-trace dimensions (A, B, C and D) on a PCB
To
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Note that all these dimensions refer to inside-edge to inside-edge spacing between traces, and not centre to
centre spacing. The following rules were defined for the inter-trace spacing on Rhino. These follow the
industry “best practices” that were discussed earlier to minimise the crosstalk between nets:
B=2xA
C=3xA
D = 4mil (for slow net) or 8mil (for high-speed net)
e
The high-speed nets for dimension D are those that were identified in Table 5.1 at the beginning of this chapter.
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5.4.4 Trace Length Matching
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A number of length-matching rules were defined for synchronous busses to ensure that these buses met the
necessary timing constraints. These rules stated that the average trace length of the data bus must match the
length of the clock trace to within certain limits. Rules were also defined that limited the length difference
between the longest and shortest data trace. These rules were defined for the DDR2 SDRAM, DDR3 SDRAM,
1Gbps Ethernet GMII and FMC buses. For brevity’s sake, the actual rules will not be given here; however
most rules required that the length of the data traces be within 300 mils of the length of their clock trace.
5.5 V ERIFICATION OF PCB L AYOUT AND ROUTING
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As has been mentioned, the placement of the majority of the components and the actual routing of the Rhino
PCB was outsourced to SunCad Designs. The final routed PCB has been included on the attached CD. See
Appendix D for instructions on how to view this file.
However, all work was checked by the author to ensure that it complied with the defined rules and specifications. Although most of this checking was done manually, two tools were used to automate part of the
process. Firstly, 3D models of all components were created to check for footprint problems and collisions between components. Secondly, the HyperLynx simulation tool was used to perform signal integrity simulations
on all high-speed traces. These automated PCB verification processes are described in more detail below.
5.5.1 3D Models to Check Footprints
Since all footprints were drawn by hand from the datasheet, the possibility of errors in the footprints always
existed. In order to minimise this risk, Wiebke Toussaint from the UCT Mechanical Engineering Department
was hired to create 3D models of all components used on the Rhino PCB, using Pro Engineer. Since Altium
Designer allows one to import these 3D models directly into the footprint file, the 3D model of the component
could be placed directly onto the footprint, ensuring that the pads and holes were all in the correct positions.
An example of one such 3D model, the Fujitsu CX4 connector, is given in Figure 5.10. Note that the pins on
the connector are silver in colour, while the pads on the PCB are copper in colour.
69
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Figure 5.10: 3D model of the Fujitsu CX4 connector, as shown from the rear
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5.5.2 Signal-Integrity Simulations
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Mentor Graphics HyperLynx is a signal integrity simulation tool that allows users to check for signal integrity
problems on a PCB before it is manufactured. It is able to calculate the reflections on a trace due to impedance
mismatches, as well as determine the crosstalk from neighbouring traces by performing a field simulation.
Furthermore, HyperLynx is able to plot the actual signal waveform as seen by the receiver, allowing users to
easily measure overshoot, undershoot, ringing and crosstalk.
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In order to check for signal integrity problems, the Rhino PCB file, with all the components placed and the
traces routed, was imported into HyperLynx. IBIS models were used to describe the input and output buffers
of each IC that was involved in the simulations. The IBIS models specify attributes such as high/low output
levels, slew rate, input/output impedance, and input thresholds. Simple models were also used to describe any
external termination resistors. By providing HyperLynx with the exact positions of components, the geometry
of the traces, the board stackup and the input/output characteristics of the ICs, HyperLynx is able to calculate
the impedance of each trace, the reflections on those traces, and the interference between traces.
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In the case of Rhino, only the high-speed traces mentioned at the beginning of this chapter were simulated.
This consists of all DDR2 SDRAM traces, all DDR3 SDRAM traces, the FMC data and clock traces, and
the GMII traces for the 1Gbps Ethernet PHY. The CX4 traces (for 10Gbps Ethernet) could not be simulated,
as standard IBIS models are not well suited for multi-gigahertz signals. The results of these signal integrity
simulations are shown below. Note that all plots show the signal waveform at the pin of the receiver IC.
DDR2 SDRAM
All the DDR2 SDRAM traces, for both SDRAM ICs, were simulated together, as the two ICs share common
address and control lines. The results of these simulations are shown in Table 5.3 below. Note that the safe
overshoot and undershoot limits were taken from the datasheet for the Winbond DDR2 SDRAM IC.
Table 5.3: Signal Integrity Simulation Results for the DDR2 SDRAM
Signal Group
Address & Control
Data
Normal Voltage Range
0V – 1.8V
0V – 1.8V
Avg Simulated
Overshoot
20mV
60mV
70
Max Simulated
Overshoot
72mV
169mV
Max Acceptable Overshoot/Undershoot
900mV
900mV
As is quite clear, the maximum overshoot on any of the DDR2 SDRAM lines is 169mV, well below the 900mV
specified limit. A full crosstalk analysis was also performed, the results of which are shown in Table 5.4. Note
that for the crosstalk analysis, HyperLynx first does a quick analysis to determine if any nets have “noticeable”
crosstalk. If so, HyperLynx will then perform a detailed simulation to quantify that crosstalk. The maximum
crosstalk in this case is only 72mV, which is not nearly enough to cause a false signal detection.
Table 5.4: Crosstalk Simulation Results for the DDR2 SDRAM
Number of nets with “noticeable” crosstalk
Average crosstalk of these “noticeable” nets
Maximum crosstalk of these nets
38 out of 70
35mV
72mV
To
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Average case and worst case plots for each of the signal groups that were simulated (Address & Control
and Data) are given below. It is important to remember that these plots show the actual signal at the receiver.
Figure 5.11 shows an average case for the address and control signals, while Figure 5.12 shows the signal with
the worst overshoot. Similarly, Figure 5.13 shows an average case for the data bus, while Figure 5.14 shows
the data signal with the worst overshoot/undershoot. Note that the dashed blue lines in each plot represent the
receiver high/low input thresholds.
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1800.0
ap
1600.0
1400.0
1000.0
800.0
of
Voltage (mV)
C
1200.0
600.0
ty
400.0
0.00
2.000
4.000
6.000
8.000
10.000
Time (ns)
12.000
14.000
16.000
18.000
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0.00
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200.0
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Figure 5.11: Signal integrity simulation for net A1 on the DDR2 bus. The line is being toggled at 166MHz,
and exhibiting 16mV overshoot and 28mV undershoot (TYPICAL CASE).
1800.0
1600.0
1400.0
1200.0
Voltage (mV)
1000.0
800.0
600.0
400.0
200.0
0.00
0.00
1.000
2.000
3.000
4.000
5.000
6.000
7.000
8.000
9.000
Time (ns)
Figure 5.12: Signal integrity simulation for nets CK P and CK N on the DDR2 bus. The clocks are running
at 166MHz, and exhibiting 72mV overshoot and 52mV undershoot (WORST CASE).
71
1300.0
1200.0
1100.0
1000.0
Voltage (mV)
900.0
800.0
700.0
600.0
500.0
400.0
0.00
1.000
2.000
3.000
4.000
5.000
6.000
7.000
8.000
9.000
Time (ns)
To
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Figure 5.13: Signal integrity simulation for the DQ2 net on the DDR2 1 bus. The data line is toggling at
333MHz, and exhibiting 29mV overshoot and 37mV undershoot (TYPICAL CASE).
3000.0
e
2500.0
ap
2000.0
1500.0
C
Voltage (mV)
1000.0
500.0
of
0.00
ty
-500.0
-1500.0
0.00
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-1000.0
1.000
2.000
3.000
4.000
5.000
6.000
7.000
8.000
9.000
Time (ns)
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Figure 5.14: Signal integrity simulation for the DQ8 net on the DDR2 0 bus. The data line is toggling at
333MHz, and exhibiting 142mV overshoot and 169mV undershoot (WORST CASE).
In all these plots, the signals are switching cleanly with only minor ringing. The reason that signal DQ2 in
Figure 5.13 does not reach the 0V and 1.8V rails is due to the volt drop across the 22 ohm series resistor. This
resistor was recommended by the AM3517 datasheet to reduce EMI [37].
DDR3 SDRAM
The DDR3 SDRAM traces were simulated separately for each IC, as they are routed separately. The results
of these simulations are shown in Table 5.5 below. Note that the safe overshoot and undershoot limits were
taken from the datasheet for the Micron DDR3 SDRAM IC.
The maximum overshoot on any of the DDR3 SDRAM lines is 224mV, well below the 400mV specified
limit. A full crosstalk analysis was also performed on both SDRAM ICs together and the results are shown in
Table 5.6. The maximum crosstalk for the DDR3 SDRAM is only 57mV, which is not nearly enough to cause
a false signal detection.
It is clear from Table 5.5 that the results are very similar for both SDRAM ICs. Therefore, plots are only
72
Table 5.5: Signal Integrity Simulation Results for the DDR3 SDRAM
Signal Group
DDR3 0 Address &
Control
DDR3 0 Data
DDR3 1 Address &
Control
DDR3 1 Data
Normal Voltage Range
0V – 1.5V
Avg Simulated
Overshoot
150mV
Max Simulated
Overshoot
220mV
Max Acceptable Overshoot/Undershoot
400mV
0V – 1.5V
0V – 1.5V
40mV
150mV
63mV
224mV
400mV
400mV
0V – 1.5V
60mV
122mV
400mV
Table 5.6: Crosstalk Simulation Results for the DDR3 SDRAM
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46 out of 86
30mV
57mV
To
Number of nets with “noticeable” crosstalk
Average crosstalk of these “noticeable” nets
Maximum crosstalk of these nets
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shown for DDR3 1. Again, average case and worst case plots are given for each of the signal groups that
were simulated (Address & Control and Data). Figure 5.15 shows an average case for the address and control
signals, while Figure 5.16 shows the signal with the worst overshoot. Similarly, Figure 5.17 shows an average
case for the data bus, while Figure 5.18 shows the data signal with the worst overshoot/undershoot. Note that
the dashed blue lines in each plot represent the receiver high/low input thresholds.
of
1600.0
1400.0
ty
1200.0
600.0
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Voltage (mV)
800.0
er
si
1000.0
400.0
U
200.0
0.00
-200.0
0.00
1.000
2.000
3.000
4.000
5.000
6.000
7.000
8.000
9.000
Time (ns)
Figure 5.15: Signal integrity simulation for net A4 on the DDR3 1 bus. The line is being toggled at 400MHz,
and exhibiting 139mV overshoot and 164mV undershoot (TYPICAL CASE).
In all these plots, the signals are switching cleanly with only minor ringing. As was explained earlier, this
ringing is caused by the trace impedance being slightly larger than the source impedance.
FMC Connectors
In order to simulate the FMC traces, a “signal source” was required. In keeping with the use-case scenarios
from Chapter 1, a Texas Instruments 500MS/s LVDS-out ADC (ADS5463) was used as the source. Therefore,
the FMC connector was replaced in the simulations by a typical ADC that one can expect to find on an FMC
card connected to Rhino. Both FMC connectors were simulated together, as their traces cross over, and the
results are shown in Table 5.7. Note that on-die termination was enabled on the FPGA for all simulations.
73
1600.0
1400.0
~
./
/
r
1200.0
I
1000.0
I ~ "-
h
\
Voltage (mV)
800.0
600.0
\
\
400.0
200.0
/
"\
0.00
-200.0
0.00
500.0
1000.0
1500.0
j
V
'\
2000.0
2500.0
I
\/
3000.0
3500.0
4000.0
4500.0
Time (ps)
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Figure 5.16: Signal integrity simulation for nets CK P and CK N on the DDR3 1 bus. The clocks are
running at 400MHz, and exhibiting 224mV overshoot and 224mV undershoot (WORST CASE).
To
1600.0
1400.0
~
1200.0
I
\
600.0
\
\
J
of
400.0
200.0
1000.0
1500.0
2000.0
~/
2500.0
3000.0
I
3500.0
4000.0
4500.0
Time (ps)
er
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500.0
ty
0.00
-200.0
0.00
I
C
Voltage (mV)
800.0
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\
1000.0
/
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Figure 5.17: Signal integrity simulation for the DQ3 net on the DDR3 1 bus. The data line is toggling at
800MHz, and exhibiting 57mV overshoot and 77mV undershoot (TYPICAL CASE).
U
1600.0
1400.0
~
1200.0
~
/
1000.0
1\
Voltage (mV)
/
>\
800.0
600.0
400.0
~
/
\
j\
/ I""
"-
~
200.0
0.00
-200.0
400.0
600.0
800.0
1000.0
\
1200.0
1400.0
1600.0
--
1800.0
/
2000.0
\
/
2200.0
Time (ps)
Figure 5.18: Signal integrity simulation for the LDQS N and LDQS P nets on the DDR3 1 bus. The data
strobe is clocking at 800MHz, and exhibiting 120mV overshoot and 122mV undershoot (WORST CASE).
74
Table 5.7: Signal Integrity Simulation Results for the FMC Signals
Signal Group
Normal Voltage Range
0V – 3.3V
FMCx CLKx M2C
(single-ended)
FMCx LA P/Nxx and 1V – 1.6V
FMCx CLKx M2C P/N
FMCx ZDOK P/Nxx
1V – 1.6V
Avg Simulated
Overshoot
80mV
Max Simulated
Overshoot
91mV
Max Acceptable Overshoot/Undershoot
500mV
5mV
8mV
60mV
6mV
37mV
60mV
To
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The overshoot on the single-ended clock lines (FMCx CLKx M2C) was initially very high. The source series
termination resistors on the output of each MAX9111 LVDS-to-CMOS converter was then changed from 22
ohms to 49.9 ohms, and the signal integrity improved drastically. One will also notice that the overshoot on
the ZDOK differential lines is higher than the overshoot on the standard data (LA) differential lines. This
is because the ZDOK lines are connected to an FPGA bank that does not support on-die termination; hence
external 100 ohm termination resistors must be used, resulting in higher overshoot. However, the overshoot is
still within specification.
ap
e
A full crosstalk analysis was also performed on both connectors together, and the results are shown in Table 5.8. The cross talk for the data and ZDOK lines is extremely low, as these lines are routed as differential
pairs, and hence have high crosstalk immunity.
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Table 5.8: Crosstalk Simulation Results for the FMC Signals
Average Crosstalk
20mV
None
None
Maximum Crosstalk
56mV
2mV
1mV
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Signal Group
FMCx CLKx M2C (single-ended)
FMCx LA P/Nxx and FMCx CLKx M2C P/N
FMCx ZDOK P/Nxx
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Since the average case and worst case are very similar for the FMC signal integrity simulations, plots will
only be given of the “worst” quality signals. Figure 5.19 shows the single-ended FMC clock with the worst
overshoot; Figure 5.20 shows the differential data signal with the worst overshoot; and Figure 5.21 shows the
ZDOK data signal with the worst overshoot.
3900.0
3400.0
2900.0
2400.0
Voltage (mV)
1900.0
1400.0
900.0
400.0
-100.0
-600.0
1.000
2.000
3.000
4.000
5.000
6.000
7.000
8.000
9.000
10.000
Time (ns)
Figure 5.19: Signal integrity simulation for the FMC1 CLK0 M2C single-ended net. The clock is running at
300MHz, and experiencing 11mV overshoot and 91mV undershoot (WORST CASE).
75
1500.0
1300.0
1100.0
900.0
700.0
Voltage (mV)
500.0
300.0
100.0
-300.0
0.00
2.000
4.000
6.000
8.000
10.000
12.000
14.000
16.000
18.000
To
Time (ns)
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-100.0
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Figure 5.20: Signal integrity simulation for the FMC0 LA P/N21 net. The positive and negative signals are
shown (in orange and blue), as well as the difference between these two signals (in red). The signal is
toggling at 400MHz, and experiencing 8mV overshoot and 8mV undershoot (WORST CASE).
1500.0
C
1300.0
of
1100.0
ty
900.0
Voltage (mV)
500.0
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300.0
er
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700.0
100.0
U
-100.0
-300.0
0.00
2.000
4.000
6.000
8.000
10.000
12.000
14.000
16.000
18.000
Time (ns)
Figure 5.21: Signal integrity simulation for the FMC0 ZDOK P/N0 net. The positive and negative signals
are shown (in orange and blue), as well as the difference between these two signals (in red). The signal is
toggling at 400MHz, and experiencing 37mV overshoot and 37mV undershoot (WORST CASE).
The LA and ZDOK traces are toggled at 400MHz, equivalent to alternating pattern of 1s and 0s being transmitted at 400Mbps. This was the maximum I/O data rate specified in Chapter 1. The single-ended clock
signal, FMC1 CLK0 M2C, is running at 300MHz, allowing a maximum double datarate of 600Mbps.
The poor waveform shape of the ZDOK lines is due to external termination resistors being used. Fortunately,
these lines are only used for the FMC-to-ZDOK+ adaptor, and hence will seldom be used. However, all traces
simulated here do cross the receiver detection thresholds without oscillation, ensuring correct signal detection.
76
GMII Bus for 1Gbps Ethernet PHY
The traces for the GMII bus between the FPGA and 1Gbps Ethernet PHY were simulated. The results are
shown in Table 5.9. Similarly, the results of the crosstalk simulation are shown in Table 5.10
Table 5.9: Signal Integrity Simulation Results for the GMII Signals
Signal Group
Normal Voltage Range
0V – 2.5V
All GMII signals
Avg Simulated
Overshoot
150mV
Max Simulated
Overshoot
366mV
Max Acceptable Overshoot/Undershoot
500mV
Table 5.10: Crosstalk Simulation Results for the GMII Signals
Average Crosstalk
110mV
Maximum Crosstalk
157mV
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Signal Group
All GMII signals
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e
To
The overshoot on all the GMII buses was initially very high (over 500mV). This was improved by running
the simulations with a number of different source series termination resistors, to determine which resistor
values provided the best impedance matching. However, even after tweaking the termination resistor values,
the overshoot/undershoot is still higher than what one would expect. This is due to the very long traces
(approximately 200mm) between the FPGA and the Ethernet PHY, which results in strong coupling between
the parallel traces. Fortunately, the overshoot/undershoot and crosstalk is still within specification.
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An average case GMII signal is shown in Figure 5.22, while the signal with the largest overshoot is shown in
Figure 5.23. This worst-case signal (TXD2) is experiencing the “stair-step” effect that was described earlier
in this chapter, due to reflections on the line.
3600.0
ty
3100.0
2100.0
1600.0
ni
v
Voltage (mV)
er
si
2600.0
1100.0
U
600.0
100.0
-400.0
-900.0
0.00
2.000
4.000
6.000
8.000
10.000
12.000
14.000
16.000
18.000
Time (ns)
Figure 5.22: Signal integrity simulation for the GMII RX CLK trace. The clock is running at 125MHz, and
experiencing 82mV overshoot and 145mV undershoot (TYPICAL CASE).
5.5.3 Full 3D Model of the Rhino PCB
Once the board had been fully routed by SunCad Designs and the high speed traces had been simulated, a
complete 3D model of the board was built. This final verification step was completely automated by Altium
Designer. Since component 3D models of components had already been imported into every footprint file,
and all the component footprints had been placed on the PCB, Altium Designer had sufficient information to
build a complete 3D model of the populated PCB. This 3D model is shown in Figure 5.24. This provided a
simple mechanism to check for collisions between neighbouring components.
77
3100.0
2600.0
(
2100.0
1600.0
Voltage (mV)
1100.0
600.0
'-
~
100.0
-400.0
-900.0
0.00
5.000
10.000
15.000
20.000
25.000
30.000
35.000
40.000
45.000
Time (ns)
U
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ty
of
C
ap
e
To
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Figure 5.23: Signal integrity simulation for the TXD2 signal on the GMII bus. The signal is toggling at
125MHz, and experiencing 259mV overshoot and 366mV undershoot (WORST CASE).
Figure 5.24: 3D model of the complete Rhino PCB
This concludes the design of the hardware for Rhino. Over the past few chapters, the requirements have been
determined, the architecture defined, and the design fully specified at the schematic level. Furthermore, this
chapter has described the PCB-level design of Rhino, which has involved defining routing rules and PCB
stackup, placing the major components on the board, and verifying the final placement and routing using
signal integrity simulations. Rhino is therefore now at a point where it is ready for manufacture.
The next chapter describes the software that was written to test the hardware once it was built, and the following chapter gives the results of these tests.
78
CH A P T E R 6
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D EVELOPMENT OF TOOLS FOR
V ERIFICATION OF H ARDWARE D ESIGN
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To
As with any complex system, the functionality and performance of Rhino needs to be checked and verified
at all stages of the design process. Therefore, even though the schematic-level design of Rhino was reviewed
many times, and the PCB layout was simulated in HyperLynx, the complete system still needs to be functionally verified once it has been built. Both hardware and software tools were developed to aid this verification.
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The hardware tools took the form of a test rig. This rig contained the basic hardware infrastructure needed to
power up a Rhino board, peripherals that would typically be connected to Rhino in the field, and debugging
equipment. The software tools, on the other hand, included the bootloaders required to boot the processor
and correctly configure its peripherals, the application software that functionally tested the peripherals, and
the gateware that was loaded onto the FPGA to check its peripherals. These hardware and software tools are
described in this chapter.
6.1 T HE R HINO T EST R IG
U
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In order to power-up the first prototype Rhino boards, and fully test their hardware, a test rig was required.
This rig needed to provide the following infrastructure:
∙ 12V DC power for the board
∙ fans and temperature sensors
∙ power button, reset button and power LED
∙ JTAG programmer for configuring the FPGA before BORPH is up and running
∙ a debug board that allows the FPGA to communicate with a PC over RS-232
Such a rig was therefore designed in Pro Engineer and manufactured out of perspex. See Figure 6.1 for the Pro
Engineer 3D model of the rig. The test rig consists of a large base plate with standoffs for mounting the Rhino
PCB, a front panel on which the fans and power/reset buttons are mounted, and a back panel with cutouts for
the connectors. The top and sides are open to provide easy access to the board.
Figure 6.2 shows the test rig after it was built and all the fans, switches and debugging hardware had been
mounted. The Rhino PCB sits in the open space in the middle of the test rig, on the brass standoffs. The
79
To
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Figure 6.1: 3D model of the Rhino test rig
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e
red power button, black reset button and green power LED are mounted on the left of the front panel, while
the two 40mm fans are mounted on the right. The buttons and LED connect to the front panel header on the
Rhino board, and the fans obviously connect to the two fan connectors. Power is supplied to the rig by a
230VAC-to-12VDC “power brick”, which connects to a jack on the back panel.
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A RS-232 debug board is mounted on the left of the test-rig. This board connects to the FPGA GPIO header
via a ribbon cable. It contains toggle switches and an LED, connected to the GPIO lines, to aid debugging. It
also contains a RS-232 level converter, whose CMOS-level receive/transmit lines connect to the GPIO header
and whose RS-232-level lines are wired to a jack on the back panel. A serial cable connects this jack to a
serial port on a PC, allowing serial communication between the FPGA and the PC.
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Provision has also been made for a JTAG programmer to connect to the FPGA’s JTAG port (the JTAG cables
are shown in the top left corner of the photograph). This allows the FPGA to be programmed before BORPH
is up and running on the processor. Although not shown here, a Xilinx FMC debug card plugs onto the Rhino
PCB during testing, allowing the performance of the FMC interface to be verified.
U
6.2 P ROCESSOR B OOTLOADER S OFTWARE
Booting the AM3517 processor is a multi-stage process, as shown in Figure 6.3. The first stage is performed by
the ROM code on the processor itself, while the remaining three stages are carried out by the two bootloaders,
X-Loader and U-Boot, and the operating system. Note that the boot ROM is stored on the processor die itself
and cannot be changed, while the other three are stored on flash memory, an SD card or on the network.
The internal bootloader runs as soon as the processor is powered. It reads the boot-select switches to determine
the required boot source. If the Ethernet port has been selected, the processor broadcasts boot image requests
over the local network. If the SD card interface has been selected, the processor scans the first sector of the
FAT table for a file named “MLO”. Lastly, if the flash memory is the selected source, the processor scans
the first four NAND memory blocks for the start of a valid boot image. In all these cases, once the ROM
bootloader has found the boot image (i.e. the X-Loader file), it copies it into on-chip SRAM and executes it.
The main function of the X-Loader is to configure and initialise the DDR2 SDRAM. Once the DDR2 SDRAM
has been initialised, the X-Loader reads the boot-select switches again, and searches either the SD card or the
NAND flash for the U-Boot image. Once found, this file is copied into external DDR2 SDRAM and executed.
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To
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2
X-Loader
3
4
U-Boot
Linux
of
1
Internal Boot
ROM
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Figure 6.2: Photo of the completed Rhino test rig
ty
Figure 6.3: The AM3517 boot process
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U-Boot then configures the peripheral sub-systems on the processor, such as the SPI and I2 C ports, the GPIO
pins, and the video output interface. U-Boot uses environment variables to specify location of the operating
system (SD card, NAND flash memory, USB flash drive, or FTP server), the Rhino board’s network settings,
and any command line parameters that should be passed to the operating system. The operating system is
then copied into the SDRAM and executed. Although both Linux and Windows CE can run on the AM3517
processor, Rhino will always use Linux (BORPH).
The bootloaders are required as the internal boot ROM is unable to load the operating system directly. This
is because the operating system image is typically quite a few megabytes, too large to fit into the processor’s
64kB of on-chip SRAM. Since the boot ROM is fixed, it has no way of knowing the SDRAM settings for
the particular board and hence cannot initialise the DDR2 SDRAM. Therefore bootloaders must be used to
configure and initialise the SDRAM before the operating system is loaded. The reason that both X-Loader
and U-Boot are required is that U-Boot is also too big to fit into SRAM (it is approximately 200kB); hence
X-Loader must first run to initialise the DDR2 SDRAM, before calling U-Boot to initialise all the peripherals
and load the operating system.
6.2.1 X-Loader
The X-Loader is the second-stage bootloader, and performs the following operations:
1. Initialise all the on-chip clocks and PLLs (phase-locked loops) to the correct frequencies.
81
2. Each of the processor I/O pins can perform a number of different functions. Each pin has a primary
mode (such as a data line for the SDRAM), but can also have a number of secondary modes (such as a
GPIO). The X-Loader therefore sets the SDRAM, GPMC (which is used for the NAND flash memory)
and SD card pins to their correct primary mode.
3. Configure the SDRAM timing settings, and initialise the DDR2 SDRAM ICs.
4. Search the SD card or NAND flash memory for a file named “u-boot.bin”, copy it into SDRAM, and
execute it.
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The X-Loader port for Rhino was based on the port for the AM3517 development board. This meant that the
X-Loader did not need to be ported to a new processor, just to a new board. Therefore, in order to get this port
running on Rhino, only the changes listed below needed to be made. The full X-Loader source code, with
these changes, can be found on the attached CD. See Appendix D for details.
To
∙ Changed the terminal from UART3 to UART1.
∙ Added support for the second SD card interface (only MMC1 was supported, while Rhino uses MMC2).
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∙ Updated the DDR2 SDRAM timings for the Winbond chip used on Rhino.
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6.2.2 U-Boot
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U-Boot is the third stage bootloader. However, it is more than just a simple bootloader. It provides a simple,
terminal-like environment with a few basic commands for reading from and writing to NAND flash memory,
copying files across the network and for simple communications with off-chip peripherals. The main functions
carried out by U-Boot are:
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1. Set all the I/O pins to their correct mode (the X-Loader only configured the SDRAM, GPMC and SD
card pins).
2. Power-up all on-chip peripherals, and enable their clocks and interrupts.
U
3. Configure the GPMC correctly for interfacing to external memory devices.
4. Provide a command line environment for testing hardware peripherals and running standalone applications.
5. Provide drivers for peripherals (both on-chip and off), such as I2 C power management devices, network,
real-time clocks on the SPI bus, video output interface, USB, and NAND flash memory. These drivers
allow the peripherals to be accessed from both the U-Boot command line and standalone applications.
6. Provide a mechanism to easily copy standalone applications into RAM from a network server using
TFTP, and then execute these applications.
7. Store settings (such as IP address, boot server IP address and booting options) as environment variables
in NAND flash memory, so that they do not need to be re-entered each time the board is booted.
8. Load the operating system from either a network server, USB flash drive, SD card or NAND flash into
RAM, and start it. The operating system command line arguments, which are stored as environment
variables, are also passed to the operating system.
82
As with the X-Loader, the Rhino port of U-Boot was based on the port for the AM3517 development board.
The full source code can be found on the attached CD. The following changes were made to the AM3517
development board port of U-Boot before it could run on Rhino:
∙ Changed the mode settings for the rest of the I/O pins so that they would interface correctly with Rhino’s
off-chip peripherals.
∙ Configured the GPMC correctly for interfacing to both the NAND flash memory and the FPGA on
Rhino. This involved mapping regions of memory to the NAND flash and the FPGA, and configuring
the GPMC timings and protocols to interface to each device correctly.
∙ Changed the sizes of the DDR2 SDRAM and NAND flash devices to match the Rhino hardware.
∙ Changed terminal from UART3 to UART1.
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∙ Added hardware SPI support (U-Boot did not support SPI on the AM3517 processor).
To
∙ Extended the I2 C sub-system to include support for multiple I2 C busses and 16-bit data transfers.
e
∙ Exported the GPIO and I2 C functions so that they can be used in standalone applications.
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6.3 C ONFIGURING THE GPMC B US
C
ap
By porting both X-Loader and U-Boot, Rhino is able to boot off either an SD card or NAND flash memory
and then enter a terminal-like environment. This environment aids the hardware verification process, as it
allows hardware peripherals to be tested and standalone applications to be executed.
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As mentioned above, the GPMC bus was configured in U-Boot to interface correctly to the FPGA. This section
therefore discusses both the physical GPMC interface and how it was configured within U-Boot.
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The GPMC contains 16 external data lines and 10 external address lines. With 10 address lines, it can only
address 1024 locations, which is clearly insufficient if one wishes to access the FPGA DDR3 SDRAM from
the processor. To increase the addressable space, the 16 data lines can be used as additional address lines. In
this multiplexed mode, a total of 26 address lines are available, providing a total of 64 million addressable
locations. Since data bus is two bytes wide (16 bits), this provides a total addressable space of 128MB.
Furthermore, the GPMC bus has 8 chip select lines, allowing eight external memory devices, each 128MB, to
be addressed. This provides a total addressable space of 1GB. The address lines, data lines, chip select lines
and other control lines are all shown in Figure 6.4, which is taken from the Rhino schematics.
Looking at Figure 6.4, one can see that chip select (CS) 0 is wired to the NAND flash memory, while CS 1 to 7
are all connected to the FPGA. This means that 768MB of the processor’s GPMC address space is allocated to
the FPGA, and 128MB to the NAND flash memory. This may seem a bit strange, as the NAND flash memory
is 256MB in capacity. Furthermore, looking at the diagram taken from the schematics, one can see that no
address lines are connected to the NAND flash. This is because the NAND memory uses a unique addressing
protocol, that multiplexes commands, addresses and data onto the 16 data lines. Therefore, the NAND flash
memory is allocated only a single physical address, and software drivers are then used to correctly multiplex
the commands, addresses and data, and hence create a virtual address space of 256MB.
The 1GB of GPMC address space is memory mapped onto the processor’s address space, so that applications
can access external devices by simply reading from or writing to appropriate memory addresses. The processor
then handles the bus transactions in the background, completely invisibly to the user application. The memory
83
2
3
4
am3517_periph_a
DR2
C\A\S\
DQ0015
DQ0014
DQ0013
DQ0012
DQ0011
DQ0010
DQ1015
DQ1014
DQ1013
DQ1012
DQ1011
DQ1010
R\A\S\
0CK0P
0CK0N
0C\S\
0LDM1
0LDM0
0UDM1
0UDM0
0W\E\
20A9
20A8
20A7
20A6
20A5
20A4
20A3
20A2
20A1
20A0
00150000
DQS10P
DQS10N
DQS00P
DQS00N
DQ009
DQ008
DQ007
DQ006
DQ005
DQ004
DQ003
DQ002
DQ001
DQ000
DQ109
DQ108
DQ107
DQ106
DQ105
DQ104
DQ103
DQ102
DQ101
DQ100
130000
020000
0A13
0A12
0A11
0A10
0BA2
0BA1
0BA0
0CKE
0ODT
2EF00V9
SDRC
FPGA_PROC_BUS
A[10..1]
A[10..1]
DBG
D[15..0]
D[15..0]
RS23
CS0
CS1
CS2
CS3_DMAREQ0
CS4
CS5_DMAREQ2
CS6_DMAREQ3
CS7_IODIR
CS0
CS1
CS2_DMAREQ0
CS3
CS4_DMAREQ1
CS5_DMAREQ2
CS6_IODIR
ROC0BUS0W\P\
ROC0BUS0W\E\
ROC0BUS0O\E\
0PROC0BUS
OC0BUS0C\S\1\
OC0BUS0C\S\0\
OC0BUS0C\S\3\
C0BUS0A0100010
C0BUS0D0150000
ROC0BUS0A10
ROC0BUS0CLK
ROC0BUS0D15
ROC0BUS0D14
ROC0BUS0D13
ROC0BUS0D12
ROC0BUS0D11
ROC0BUS0D10
0BUS0A\D\V\0ALE
OC0BUS0BUSY1
OC0BUS0BUSY0
BUS0C\S\6\0IODIR
C\S\2\0D\M\A\R\E\Q\0\
C\S\5\0D\M\A\R\E\Q\2\
C\S\4\0D\M\A\R\E\Q\1\
ROC0BUS0A9
ROC0BUS0A8
ROC0BUS0A7
ROC0BUS0A6
ROC0BUS0A5
ROC0BUS0A4
ROC0BUS0A3
ROC0BUS0A2
ROC0BUS0A1
ROC0BUS0D9
ROC0BUS0D8
ROC0BUS0D7
ROC0BUS0D6
ROC0BUS0D5
ROC0BUS0D4
ROC0BUS0D3
ROC0BUS0D2
ROC0BUS0D1
ROC0BUS0D0
PROC_BUS
FPGA_
GPMC_BUS
CLK
WE
OE
ADV_ALE
CLK
WE
OE
ADV_ALE
CLE
WP
WP
INI
FPGA_
FPGA_S
GPMC_BUS
ETH
am3517_periph_b
USER
NAND_BUS
SUP
ap
CE
C
PRO
C
WE
RE
ALE
CLE
WP
of
ETH
ETH_P
ty
R/B
PW
e
IO[15..0]
AND
0C\E\
0IO15
0IO14
0IO13
0IO12
0IO11
0IO10
0W\P\
0W\E\
0R\E\
0R0B\
0150000
0ALE
0IO9
0IO8
0IO7
0IO6
0IO5
0IO4
0IO3
0IO2
0IO1
0IO0
0CLE
D
I2C_PW
To
BUSY0
BUSY1
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n
USER
WAIT0
WAIT1
WAIT2
SPI_3CH
er
si
Figure
SPI 6.4: The GPMC bus in the Rhino schematics
TC0SPI
0SPI0SCLK
0SPI0MOSI
0SPI0MISO
0SPI0C\S\
_SPI
MOSI
MISO
SCLK
CS
is fully
MOSI
MISO
SCLK
hasCS0
been
U
H
RTC_AUDIO_FP_SPI
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mapping of the GPMC address space
configurable, and
allocated as in Table 6.1. Note that
the GPMC may only use addresses
within
the
range
0x00000000
to
0x3FFFFFFF.
SPI
DIO0CTRL
O0CTRL0SCLK
O0CTRL0MOSI
O0CTRL0MISO
O0CTRL0C\S\
IO_CTRL
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Table 6.1:
MOSI
MISO
ChipSCLK
Select
CS
CS1
End address Region size
0x37FFFFFF 128MB
0x0FFFFFFF 128MB
CS2
0x17FFFFFF
128MB
0x1FFFFFFF 128MB
0x27FFFFFF 128MB
0x2FFFFFFF 128MB
0x3FFFFFFF 128MB
– SYS_BOOT[7..0]Unused
VCC
20
PIU502
_OC
\G\0\O\C\
1_OC
B\1\0\O\C\
B\2\0\O\C\
2_OC
FMC_
FMC_
D
AUDI
BOOT_BUF_EN
RS23
DBG
SYS_BOOT[7..0]
FAN_FAIL
VTTDDR3_PG
VCCMGT_PG
19
PIU5019
1Y4
2OE
11
PIU5011 2A1
13
PIU5013 2A2
15
PIU5015 2A3
17
PIU5017 2A4
84
GND
PWR_WARNS
USB
PWR_FAIL_INT
Looking at Figure 6.4, onePIU501
will1 notice
1OE that the GPMC contains a number of control lines. Understanding
PWR_OFF_INT
RESPWRON
these control lines is essential
to
understanding
the
bus
protocols
of
the
GPMC.
An
explanation
of
each
of the
2
18
SYS_BOOT0
PIU502 1A1
1Y1 PIU5018
4
16
SYS_BOOT1
control lines is therefore given
in Table
some of the CS lines can be used as DMA request lines
PIU504
1A2 6.2. Although
1Y2 PIU5016
6
14 SYS_BOOT2
PIU506 1A3
1Y3 PIU5014
(see Figure 6.4), all were used
purely
as chip selects
the testing simple.
8
12to keep
SYS_BOOT3
PIU508
PIU5012
1A4
US
US
Regions for the GPMC Bus on Rhino
CS number Connected to Start address
SPI
MOSI
CS0
NAND flash
0x30000000
MISO
CS1
FPGA SCLK
0x08000000
CS
CS2
FPGA
0x10000000
CS3
FPGA
0x18000000
CS4
FPGA
0x20000000
COC51
C51
VCC_3V3_PROC
CS5
FPGA
0x28000000
PIC5101 PIC5102
CS6
FPGA
0x38000000
COU5
100n
U5
CS7
–SN74LVC244ADB
GND FPGA
0SPI0PROC
PI0PROC0SCLK
PI0PROC0MOSI
PI0PROC0MISO
PI0PROC0C\S\
PI_PROC
H
9
SYS_BOOT6
2Y1 PIU509
7
SYS_BOOT7
PIU507
2Y2
5
SYS_BOOT4
2Y3 PIU505
3
SYS_BOOT5
2Y4 PIU503
am3517_power
1588_G
1
RTC_S
Table 6.2: GPMC Control Lines
GPMC Control Line
nCS0 to nCS7
CLK
nWE
nOE
nADV ALE
CLE
nWP
WAIT0 to WAIT2
Full name
Chip select 0 to 7
Clock
Write Enable
Output Enable
Address Valid
Control Latch Enable
Write Protect
Wait inputs
Direction
Output
Output
Output
Output
Output
Output
Output
Input
Description
Enables a specific external memory device.
Bus clock
Indicates valid data on bus during write
Indicates peripheral can write to data bus.
Indicates valid address present on bus.
Not used by FPGA.
Enables write protect on memory device.
Indicates that memory device still busy.
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The bus protocols and timings of the GPMC are fully configurable through processor registers. These settings,
as well as the CS memory mappings described earlier, are defined in the U-Boot Rhino board configuration
file. The actual bus settings themselves are not given here; rather, they are explained using timing diagrams.
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To
Figure 6.5 shows the bus cycles for a read operation, which takes 8 GPMC FCLK cycles, while Figure 6.6
shows the write operation, which takes 6 GPMC FCLK cycles. The GPMC FCLK is the internal function
clock for the GPMC bus, and runs at twice the rate of GPMC CLK. This allows events to take place on both
the rising and falling edge of the CLK. Note that these diagrams are specific to the timing and protocol settings
that have been chosen for Rhino. In both figures, pay careful attention to the bottom plot, which indicates the
actions performed by the FPGA and processor on each bus cycle. The “ZZZ”s in the read operation diagram
indicate that the data bus is undriven and thus in high-impedance state.
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The objective of the Rhino test software is to test the hardware as thoroughly as possible, by the simplest
means possible. Therefore, the FPGA-processor bus protocol was kept very simple so that the FPGA only
needs to perform actions on the rising edge of the GPMC CLK. This does mean that the protocol is not as
efficient as it could be; it is possible to achieve the same operations in fewer bus cycles, but with added
complexity. However, the bus does still run at the full 83MHz, thereby testing the traces at full speed.
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6.4 P ROCESSOR T EST S OFTWARE
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Standalone U-Boot applications were written to test Rhino’s power management sub-system, to test the FPGAprocessor bus and to test the real-time clock. The workings of these applications are discussed below.
6.4.1 Application: Rhino LEDs
Rhino’s equivalent of “Hello World”. The application switches the two processor user LEDs on or off, depending on the command line arguments.
6.4.2 Application: Rhino PSU Enable
This application switches the FPGA power supplies on and off. Since the FPGA power supplies are switched
off at power up, this program must be run before the FPGA or any of its peripherals can be tested.
The command line usage for this application is: go 0x80300000 <VCCINT> <VCCO AUX> <VCCMGT>
where 0x80300000 is the address in SDRAM where all standalone applications are stored, and the remaining three parameters indicate whether the relevant FPGA power supply must be switched on or off. The
program therefore merely reads the command line arguments and sets each of the three FPGA power supply
enable lines (connected to GPIO pins on the processor) either high or low.
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GPMC Read Operation
GPMC_FCLK
Cycles
0
CLK
1
2
3
4
5
6
7
0
,,
~~----;------'---i-----i-----i!
,,
,,
VI'-----Ci-------C!------~------~------'
+-______-{,j
I
L -____
~
ADDR[10:1]
,,!
:v<~+-----------------j~
i
VALID ADDR [26:17]
J<
i
DON’T CARE
"
"
~,
VALID ADDR [16:1]
ZZZZZ
VALID DATA [15:0]
~
,
L -__4 -____- ',
,
ZZZZZZZZZZZ
L -__~-----<
,,
,,
,,
,,
e
DATA[15:0]
,
!V
I
!, \
,
,,
,
,
--r-------r-------r------~'
nOE
:
,
w
n
I
nADV
To
nCS
,,
,,
C
CLK
ap
Processor (ARM) and FPGA actions on each clock cycle
of
t
ARM writes
address
ARM releases
address bus
FPGA writes
data
FPGA
releases
data bus
er
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ty
FPGA reads
address
t
ARM reads data
Figure 6.5: The GPMC read operation, as configured for Rhino
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6.4.3 Application: Rhino FMC Control
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The FMC interface is tested using a FPGA gateware design and a Xilinx XM105 FMC debug card. The
XM105 card (shown in Figure 6.7) brings the data lines out onto headers, allowing the signals from one half
of the bus to be looped back to the other half of the bus. The debug card also contains a Silicon Labs clock
(Si570), whose frequency can be programmed over the FMC I2 C bus. However, before the FPGA can test the
FMC interface, the FMC card must be powered up and the clock programmed to run at the correct frequency.
The Rhino FMC Control processor application therefore performs the following operations, in the given order.
Other than the I2 C operations, which are carried out using the U-Boot I2 C drivers, the steps are performed by
simply setting or reading GPIO pins.
1. Switches on all the FMC load switches, supplying 2.5V, 3.3V and 12V to both FMC cards.
2. Sets the PGOOD (power good) and GA (geographic address, which sets the EEPROM address on the
I2 C bus) signals going to the FMC cards.
3. Indicates whether the debug card has been plugged into FMC 0 or FMC 1 connector, by reading the
nFMC PRSNT signals.
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GPMC Write Operation
GPMC_FCLK
Cycles
0
1
2
3
4
5
0
CLK
nCS
nADV
DATA[15:0]
VALID ADDR [16:1]
DON’T CARE
To
VALID ADDR [26:17]
VALID DATA [15:0]
ap
e
ADDR[10:1]
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nWE
of
C
Processor (ARM) and FPGA actions on each clock cycle
ty
CLK
er
si
ARM writes
address
ARM writes data
FPGA reads
address
FPGA reads
data
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Figure 6.6: The GPMC write operation, as configured for Rhino
4. Reprograms the Silicon Labs clock on the FMC debug card, changing the frequency from 156.25MHz
to 312.5MHz, by sending commands over the FMC I2 C bus.
6.4.4 Application: Rhino GPMC Test
This standalone application is used in conjunction with a gateware design on the FPGA to test the FPGAprocessor bus. For this test, the FPGA is programmed to emulate a read-only memory. Rather than actually
storing 768MB of data, the FPGA instead always returns (address[15:0] + 1) when read by the processor.
Simply returning the address as the data value (rather than the address + 1) would not have fully tested the
FPGA-processor bus. Since the lower 16-bits of the address are multiplexed onto the data bus during the read
operation, if the processor did not clear the data bus after writing the address, and the FPGA did not drive
the bus at all, the lower 16-bits of the address would remain on the data bus. The processor would therefore
incorrectly think that the FPGA returned the correct value. Hence, the FPGA returns (address[15:0] + 1). The
full details of the FPGA gateware design are explained later in this chapter.
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Figure 6.7: Xilinx XM105 FMC debug card
(Image taken from Xilinx website: http://www.xilinx.com)
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In order to test the write operation, the FPGA is programmed to display the bottom four bits of the data word
on four of the FPGA’s LEDs, for any write request. This obviously does not test all the data and address lines,
but that is not necessary; the write operation merely needs to test the write control lines.
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The Rhino GPMC Test U-Boot application therefore reads a number of different address locations from the
FPGA, and checks in each case that the returned values equals (address[15:0] + 1). The application also
writes four values in sequence to an arbitrary address, and the user is required to check that the correct pattern
appears on the LEDs. Note that in order to read or write to the FPGA, the application merely needs to read or
write to an address that lies within one of the FPGA’s six chip select regions. The processor handles the bus
transactions in the background, completely invisible to the user application.
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The application actually runs three separate tests, as described below:
Test 1: The processor sequentially reads all 768MB of the address space allocated to the FPGA, checking at
each address that the returned value equals (address[15:0] + 1).
Test 2: The problem with test 1 is that most of the address lines change very slowly (especially those near the
MSB). Therefore, to test all the address lines at high speed, Test 2 reads just two separate addresses that have
inverse bit values. By alternately reading these two addresses 64 million times each, all the address lines are
flipped on every read cycle, verifying their performance at high speed.
Test 3: To test the write operation, the processor writes the following four binary values in sequence: b0001,
b0010, b0100, b1000. Since these writes occur 500ms apart, a “walking” effect is created on the FPGA LEDs.
For Test 1 and 2, any incorrect read responses are recorded and the total number of errors are displayed at the
end of the test. For Test 3, the user must manually check that the correct pattern appears on the FPGA LEDs.
6.4.5 Application: Rhino RTC Test
This application tests the real-time clock that is connected to the processor via SPI. The application first sets
the value of the seconds register to 1, by writing to the real-time clock via the SPI interface. The application
then waits 4 seconds, using a delay loop, and then reads the new seconds value from the real-time clock, and
prints it out to the terminal. If the real-time clock is working correctly, the new seconds value that is printed
out to the terminal should be 5.
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6.4.6 Application: Rhino System Monitor
The system monitor application reads the status of all the power, temperature and fan monitors on Rhino and
prints the relevant voltages, currents, temperatures and fan speeds to the terminal. The application runs for
a total of 6 minutes, taking readings every 2 seconds. The readings are printed to the terminal as commaseparated values (CSV), so that they can easily be saved as a CSV file and opened in a spreadsheet program.
The software consists of an initialisation stage and a 6 minute loop stage, described below. A number of
events, such as powering up the FPGA or turning the fans on, also occur at pre-determined times (i.e. after a
fixed number of loop iterations). All I2 C operations use the native U-Boot I2 C driver for the AM3517.
To
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Initialisation:
Switch off fans
Calibrate current sensors (based on the value of the current sensing resistor)
Both of these operations are achieved by sending commands over the I2 C power management bus.
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Loop (iterates every 2 seconds):
Print out all voltages, currents, temperatures and fan speeds to the terminal.
This is performed by reading all the monitors connected to the I2 C power management bus.
Events:
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After 30 seconds: switch on the FPGA, by driving the FPGA power supply enable lines high.
After 1 minute: prompt user to program the FPGA using a JTAG programmer.
After 2.5 minutes: FPGA programming should now be complete.
After 3 minutes: the FMC load switches are enabled, switching the FMC cards on.
After 4 minutes: the fans are switched on at 90% speed.
After 6 minutes: test complete.
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By switching on each component separately, the effect of that particular component on the board’s power
consumption and temperature can be easily determined.
6.5 FPGA T EST G ATEWARE
The previous section described the standalone U-Boot applications that were written to test the processor and
its peripherals. Similar test applications were written for the FPGA to verify the operation and performance
of its peripherals. These gateware designs were written in VHDL and compiled into a FPGA configuration
file using Xilinx ISE.
6.5.1 Rhino Blinky
Rhino Blinky is the most basic test application for the FPGA. The logic circuit is clocked by the 100MHz
system clock, which is reduced in frequency using a PLL and an overflow counter within the FPGA. The
circuit bit-shifts a 8-bit number every 100ms, which is displayed on the LEDs, creating a “walking” pattern.
The purpose of this design is to verify that the FPGA itself is operating correctly, that the 100MHz system
clock is working, and that the LEDs have been correctly wired to the FPGA.
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6.5.2 Rhino DDR3 Memory Test
The purpose of this gateware design is to test the DDR3 SDRAM ICs and their traces at high speed. In order
to simplify the gateware required to interface to the DDR3 SDRAM ICs, Xilinx DDR3 SDRAM IP cores are
used to perform the low-level interfacing operations. Each core interfaces to a single DDR3 SDRAM IC using
the memory controller blocks on the Spartan-6. The cores are clocked by the 100MHz system clock, which
is multiplied up by a PLL to generate the 333MHz clock for the address lines and the 667MHz clock for the
data lines. The SDRAM devices are not run at the full 800MHz speed, as the current silicon version of the
Spartan-6 contains a flaw that does not allow speeds higher than 667MHz, unless the core voltage is increased.
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Two separate VHDL “processes” were written to test each of the two SDRAM ICs. Since these two processes
work in exactly the same way, only the state chart for DDR3 0 has been shown in Figure 6.8. Each process is
clocked by the output clock of the relevant memory core (called clk out in the state chart). This output clock
runs at 1/16th of the 667MHz data clock, as the datapath on the fabric side of the core allows 16 bytes (128
bits) to be written every clock cycle.
e
To
Note that in the state chart, the boxes indicate states, with the name of the state shown in the top half, and the
actions performed in that state in the bottom half. The arrows indicate transitions, with the text indicating the
events that trigger that transition, and the text in square brackets explaining the guard condition that must be
satisfied before the transition can occur.
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To briefly explain the test gateware: incrementing values (1, 2, 3...) are written to the SDRAM. In order to
accelerate the write operation, the FIFO queue in the memory core is used to queue 64 write values before the
write operation is actually executed. This is repeated until the entire 256MB of SDRAM has been written.
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6.5.3 Rhino 1GBE Test
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The design then reads back the entire memory IC, requesting 64 addresses at a time (burst mode). The
gateware reads each value in the read queue, checking that it matches the value that was originally written to
SDRAM. This continues until the entire SDRAM has been read. At the end of the test, the LEDs are switched
on to indicate that the test is complete, and whether any errors were detected.
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The purpose of the Rhino 1GBE Test is to check the 1Gbps Ethernet PHY circuitry, as well as the traces
between the FPGA and the PHY. The gateware design checks the management data interface, the GMII bus
and the RJ45 analogue interface by enabling various loopback modes.
For the sake of clarity, the discussion of the 1Gbps Ethernet PHY circuitry that was given earlier in the
schematics chapter is briefly recapped. Two separate interfaces connect the PHY and the FPGA. The GMII
bus is an 8-bit transmit, 8-bit receive full-duplex parallel interface that is used for transferring data packets
between the FPGA and the PHY. A separate, slower, serial interface, called the management data interface, is
used for configuring the PHY. The FPGA uses this interface to modify registers on the PHY.
Using the management data interface, the FPGA can enable both GMII loopback and line loopback modes. In
GMII loopback mode, the PHY simply connects the GMII receive lines to the GMII transmit lines, within the
PHY. This allows the FPGA to verify the integrity of the GMII bus at high speed, without having to implement
any network protocol. In line loopback mode, the PHY simply echoes any Ethernet packets that it receives
on the Ethernet cable, back to device at the other end of the cable. This mode allows the analogue half of the
PHY circuitry to be tested by using a PC to send Ethernet packets to Rhino, and then using a packet sniffing
application to ensure that all the packets are correctly echoed back.
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The gateware design uses a state machine with a large number of states. Since there is an almost completely
linear progression from one state to the next, the states have been represented in tabular format in Table 6.3.
Most of the states simply read or modify the registers on the PHY using the management data interface. With
the exception of STATE 11, every state progresses to the following state once the read or write request has
completed.
Table 6.3: Main State Machine for Rhino 1GBE Test
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Actions within State
Wait 5 seconds for PHY to come out of reset.
Request PHY ID via MDIO.
Check that PHY ID = 0x0141. Request Status register.
Display link and auto-negotiation status. Write new PHY LED settings.
Request Control register via MDIO.
Modify Control register to enable GMII loopback, and write it back.
Wait for completion of Control register write. Then signal start of GMII loopback test.
Wait for GMII loopback test to finish. Request Control register via MDIO.
Modify Control register to disable GMII loopback, and write it back.
Wait for completion of Control register write. Request PHY-specific Control register.
Modify PHY-specific Control register to toggle line loopback, and write it back.
Wait 10 seconds and then go to STATE 9.
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State
STATE 0
STATE 1
STATE 2
STATE 3
STATE 4
STATE 5
STATE 6
STATE 7
STATE 8
STATE 9
STATE 10
STATE 11
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Of interest are states 9, 10 and 11. These states read and modify the PHY-specific control register every 10
seconds, and in doing so, enable and disable the line loopback mode every 10 seconds. This aids testing of the
cable side of the PHY, as the operation can be verified when line loopback mode is both enabled and disabled.
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Another two, much simpler, state machines were written that control the actual sending and receiving of
data along the GMII bus. These two state machines are activated when the GMII loopback mode is enabled.
The transmit state machine is clocked by the GTX CLK. It first writes incrementing values from 0 to 255 to
the GMII transmit bus. However, with this test, the most significant bits change slowly. The state machine
therefore also writes just two values, with inverse bit values, 256 times. This causes the data traces to invert
on every bus clock cycle.
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The receive state is clocked by the RX CLK, which is generated by the PHY. On the rising RX CLK edge,
the state machine checks the RX DV signal from the PHY, to determine if valid data is present. If so, it reads
the data bus and compares it to what was just transmitted. If it does not match, the error is recorded.
At the end of the test, the FPGA LEDs are switched on/off to indicate that the test has completed and whether
it passed or not. Although not described here, an additional management data interface VHDL module was
written to control the sending and receiving of 16-bit register values along the serial MDC and MDIO lines.
6.5.4 Rhino 10GBE Test
The Rhino 10GBE Test verifies the performance and functionality of the CX4 10Gbps Ethernet ports. It does
this by sending 10 million 64-bit words out one CX4 port, through an external loopback cable to the second
CX4 port, and back to the FPGA. The FPGA then inspects the received data to ensure that it matches the
transmitted data.
All data is transmitted using the XAUI link-layer protocol; no attempt has been made to implement the Ethernet protocol, which is built on top of the XAUI protocol. The XAUI protocol uses four XAUI lanes, each
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running at 3.125Gbps, connected in parallel to a single CX4 connector. These four lanes must be bonded on
the FPGA, which means that their transmit clocks are synchronised. Furthermore, the XAUI lanes implement
8b/10b error correction. This means that each 8-bit data byte is encoded as a 10-bit symbol, allowing error
correction to take place. As a result, the total throughput per CX4 connector is 10Gbps, and not 12.5Gbps.
The Rhino 10GBE Test logic design is implemented using two independent datapath processes, one per CX4
connector. The operation of each of these VHDL processes can be described as follows:
∙ Stage 1: wait for all the PLLs to achieve lock, and for the transmit clocks for the four XAUI lanes to
become synchronised.
∙ Stage 2a: continuously send IDLE characters so that the receiver at the other end of the cable can detect
these IDLE characters, lock onto the carrier clock signal, and align its own receive clocks.
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∙ Stage 2b: At the same time as Stage 2a, wait until own receivers are aligned and synchronised. Once
this occurs, clear any local receiver faults and proceed to Stage 3.
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∙ Stage 3: repeat 1 million times:
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– Transmit a fixed 64-bit test sequence. The low-level transceiver logic, implemented in IP cores
and transceiver hardware, converts the 64-bit word into four 16-bit words, and transmits each one
serially down a XAUI lane.
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– Check that each received 64-bit word matches the test sequence that was transmitted by the
transceivers at the other end of the CX4 cable. If not, record the error.
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If any errors were detected after the 10 million transfers, the fault is indicated on FPGA LEDs. Note that since
the 64-bit test sequence is transmitted serially, the test word doesn’t need to be changed for each transfer. A
single, fixed value will still cause a number of high-speed transitions on the data line.
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Again, Xilinx IP cores were used to control the GTP transceivers and to implement the XAUI protocol. The
transceiver IP cores contained a large number of user-defined settings, but most were left at their default
value. One setting that is of particular interest is the pre-emphasis setting, which allows the high frequency
components of the signal to be emphasised (by a gain ranging from 0dB to 7.6dB) before being transmitted
[45], helping to maintain signal integrity. In order to determine the optimum pre-emphasis setting, a simple
FPGA logic circuit was designed that cycled through 8 predefined pre-emphasis values every 30 seconds,
allowing the signal waveform to be viewed on a high-speed digital oscilloscope at each setting.
6.5.5 Rhino FMC Test
The Rhino FMC Test verifies the integrity of FMC connector traces at high speed. This is achieved using the
Xilinx XM105 FMC debug card that was described in Section 6.4.3. By placing jumpers on the headers on
the FMC debug card, the one half of the FMC LA[33:0] data bus can be looped back to the other half. This
allows the FPGA to write data to one half of the data bus, and then read that same data back on the other half.
If, however, the data read back does not match what was written, then a hardware fault exists.
This gateware design is used in conjunction with the U-Boot Rhino FMC Control standalone application.
The U-Boot application is run before the FPGA is programmed. It powers up the FMC card and programs
the Silicon Labs clock to run at 312.5MHz. Two-pin jumpers are then placed on the LA[33:0] headers on
the FMC card, creating loopback connections as shown in Figure 6.9. Data is written to the FMC data lines
labelled “Outputs” and read back on the lines labelled “Inputs”.
92
The Silicon Labs clock on the FMC card is connected to the FMCx CLK0 M2C line. A PLL within the FPGA
divides the clock frequency by four to obtain 75MHz, which in turn clocks the logic for the test. The design
performs two types of tests: a counting test and an alternating bits test. The counting test writes incrementing
values from 0 to 65 535 to the FMC output lines, testing for shorts and breaks in the data traces. An alternating
bit test is also done which writes just two data values, with inverse bit values, on alternate clock cycles, testing
the traces at high-speed. Both tests run for 65 536 clock cycles. The flow of logic on the FPGA for the FMC
test can be described as follows:
Initialisation:
cycle counter = 0
test type = COUNTING
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On falling clock edge:
Write data to output FMC pins
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To
On rising clock edge:
Read FMC input pins. If this does not match most recently written data, record the error.
If test type = COUNTING, increment write value.
Else test type = ALTERNATING, and invert bits of write value.
Increment cycle counter
If cycle counter = 64k, set test type = ALTERNATING
If cycle counter = 128k, stop test
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The FPGA LEDs are used to indicate whether the test has finished, and whether there were any errors. The
status of the nPRSNT, GA0 and GA1 FMC control signals are also displayed on the LEDs. To aid debugging,
a UART controller from OpenCores has been included in this design. The transmit and receive lines of the
UART are wired to the GPIO pins that connect to the RS-232 debug board on the test rig. If an error is
detected, both the transmitted data and the received data are sent to a PC via this UART for further analysis.
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Another version of the test was written that runs at 150MHz, but as will be explained in the next chapter, this
gave unsatisfactory results.
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6.5.6 Rhino Processor Interface Test
This gateware design is used in conjunction with the U-Boot standalone application described earlier (Rhino
GPMC Test) to test the FPGA-processor interface. It makes the FPGA appear as a read-only memory, that
returns (address[15:0] + 1) whenever it is read. It also has a simple write function, that displays the bottom
four bits of the data bus on the LEDs whenever a read occurs to any address.
The logic circuit is described by the flowchart in Figure 6.10. Note that this is a flowchart, and not a state
diagram, and describes the main VHDL process. This process is executed on every rising edge of the GPMC
CLK. If any of the FPGA CS lines are low, the logic design then samples the nADV, nOE and nWE lines. If
nADV is low, then the processor has just written the address to the bus and the FPGA stores this address. If
nOE is low, it is the second cycle of a read transaction, and the FPGA writes (address[15:0] + 1) to the data
bus. If nWE is low, it is the second cycle of a write transaction, and the FPGA displays D[3:0] on the LEDs.
This concludes the discussion of the test hardware and software that was developed for Rhino. The design of
construction of the test rig was described in the first half of the chapter, while the processor test software and
FPGA test gateware was discussed in the second half. The next chapter gives the results of these tests.
93
•t
rising edge of clk_out [calib_done='1']
State: DDR3_INIT
entry/Clear read, write, control pipelines
I
rising edge of clk_out
1
rising edge of clk_out
[less than 64 values added to
"write" queue]
State: DDR3_WRITE_LOAD
entry/Write next data value to "write" queue
I
rising edge of clk_out [64 values written to "write" queue]
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1
rising edge of clk_out
[less than 256MB
written to SDRAM]
To
State: DDR3_WRITE_EXEC
entry/signal core to write entire queue to SDRAM
I
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rising edge of clk_out
State: DDR3_WRITE_WAIT
C
exit/reset "write" queue; increment write address by 64*16 bytes
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rising edge of clk_out [all 256MB written to SDRAM]
[still more addresses to read]
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State: DDR3_READ_REQ
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entry/Request 64 128-bit words from SDRAM
I
rising edge of clk_out
(
t
State: DDR3_READ_WAIT
L--
)
I
rising edge of clk_out [data available from SDRAM]
[read data <> written data] /
record error
[read data = written data]
[read all 64 words]
~
[more words in queue to check]
[entire SDRAM memory checked]
State: DDR3_IDLE
entry/Set finished LED and result LED
Figure 6.8: State chart for the DDR3 0 memory test
94
Inputs
LA00
LA01
LA02
LA03
LA04
LA05
LA06
LA07
LA08
LA09
LA10
LA11
LA12
LA13
LA14
LA15
LA16
LA17
LA18
LA19
LA20
LA21
LA22
LA23
LA24
LA25
LA26
LA27
LA28
LA29
LA30
LA31
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Outputs
To
Loopback
Jumpers
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Figure 6.9: Loopback connections using jumpers on the FMC debug card
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nADV low indicates first
cycle of bus transaction
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On every rising
edge of GPMC CLK
Yes
Is nADV low?
No
Are any FPGA
nCS lines low?
No
Set D[15:0] to
high-impedance
U
Record address
Yes
nOE low indicates second
cycle of read transaction
Write
(addr[15:0] + 1)
to data bus
Yes
Is nOE low?
No
nWE low indicates second
cycle of write transaction
Display D[3:0]
on LEDs
Yes
Is nWE low?
No
Set D[15:0] to
high-impedance
Figure 6.10: Flowchart describing the flow of logic in the Rhino Processor Interface Test gateware
95
CH A P T E R 7
R ESULTS OF H ARDWARE V ERIFICATION
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7.1 T HE C OMPLETED R HINO PCB S
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While the test software was being developed, the first prototype Rhino PCBs were being manufactured. This
chapter describes the tests that were carried out during manufacture to ensure that the boards were built
according to specification, and the results of these tests. Photographs of the completed PCBs are also given.
This is followed by a brief discussion of the hardware bugs that were picked up during the process of powering
up the boards and running the bootloaders. Finally, the results of the software tests, which were described in
the previous chapter, are given.
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The PCBs were manufactured in two stages. Firstly, the bare-board PCBs were manufactured by Vector
Fabrication in Milpitas, California, USA. They were then shipped to South Africa where they were populated
by Tellumat in Cape Town. Four boards were manufactured for the prototype run. Figure 7.1 shows the
completed Rhino board, while Figure 7.2 shows the completed board from a different angle, with annotations.
Figure 7.1: The completed Rhino PCB
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Figure 7.2: Another view of the completed Rhino PCB, with annotations
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7.2 PCB M ANUFACTURING T EST R ESULTS
Two automated test processes were carried out during PCB manufacturing: impedance testing and X-raying.
Impedance testing takes place during the manufacturing of the bare PCB and verifies that the impedancecontrolled traces do in fact exhibit the correct AC impedance. X-raying, on the other hand, takes place after
the board has been fully populated, and is used to check that the BGA packages have been correctly soldered.
Vector Fabrication used a digital sampling oscilloscope to measure the AC impedance of the impedancecontrolled traces. The results of these measurements are given in Table 7.1. All measured impedances are
within 6% of the target impedance, which is well within the 10% manufacturing tolerance specification.
All the PCBs were X-rayed after they had been assembled by Tellumat. The aim of this was to check for shorts
and dry solder joints under the BGA packages, as these packages cannot be visually inspected. An X-ray of
one of the DDR3 SDRAM ICs (U72) is given in Figure 7.3. The dark grey circles are the BGA balls, which
are arranged in six columns on the SDRAM IC. The open circles between the balls are the vias. From this
X-ray, one can see that all the balls are solid circles, indicating that there are no dry solder joints. One or two
of the balls do have slightly lighter patches, called voids, but these are all within limits (as will be explained
later). Furthermore, there are clearly no shorts between balls or vias.
97
Table 7.1: Impedance Measurement Results for the Rhino PCB
1
Single-ended Impedance
Target Actual Error
50
52.77
+5.54%
3
5
12
14
16
50
50
50
50
50
52.04
51.93
51.11
51.21
51.21
+4.08%
+3.86%
+2.22%
+2.42%
+2.42%
Differential Impedance
Target Actual Error
100
101.5
+1.5%
90
91.23
+1.37%
100
105.3
+5.3%
100
101.5
+1.5%
100
103.4
+3.4%
100
105.3
+5.3%
100
103.4
+3.4%
90
89.66
-0.38%
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Figure 7.3: X-ray of one of the DDR3 SDRAM ICs on Rhino after production
A void analysis of the bottom-right six balls is given in Figure 7.4. The lighter grey areas on the circles (which
have been highlighted with green in this image) indicate voids. A void is simply a cavity within the solder
ball, caused by a trapped air bubble or vapourised flux [56]. The void percentage, which is the percentage of
the cross-sectional area of the ball that is occupied by the void, is given next to each void. For these six balls,
the void percentage varies from 0.6% to 4.8%. Since the IPC-7095 Class 2 specification for BGA void size is
12% of the ball area [57], all voids are within the recommended limit.
All the BGA packages on the Rhino boards were X-rayed and were checked with automated image recognition
software. This software checks for shorts, dry joints and voids under the BGA packages. All the Rhino
prototype PCBs passed these automated tests.
7.3 H ARDWARE B UGS AND M ODIFICATIONS
All four prototype Rhino PCBs were powered up and tested using the test rig described in the previous chapter.
This test rig, with one of the Rhino boards, can be seen in Figure 7.5. Two FMC cards have been plugged
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Figure 7.4: Void analysis of six of the balls on the DDR3 SDRAM IC
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into this board: the red FMC card on the left is a quad-channel ADC card, while the board on the right is the
Xilinx FMC debug card.
Figure 7.5: The Rhino test rig being used to power up a board
During the process of powering up the first prototype board and attempting to get X-Loader and U-Boot
running, a number of hardware errors were picked up. All of these faults were design errors, and not manufacturing problems. Fortunately, most were relatively easy to solve with simple manual modifications. The
details of these design errors, and the fixes, are detailed in Table 7.2. In the majority of these cases, the error
was simply an omitted pull-up or pull-down resistor, which was easily corrected by hand-soldering a resistor
between the appropriate vias or IC pins. Luckily, the four faults that could not be corrected with simple mod99
ifications (indicated by an asterisk next to the fault number) did not impede the operation of the board in any
way. Note that the full schematics in Appendix B already include all these fixes.
Table 7.2: Rhino Hardware Design Errors
7
8*
9*
10*
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Fix
10K pull-down resistor (R468) has been added to
keep power supply enable line low at startup.
2k2 pull-down resistors (R466 and R467) added
to keep supply EN pins low at startup.
Added two 47k pull-up resistors (R463 and
R464) to open-collector outputs, so that they can
pull the enable pins high.
BOOT BUF EN net is now driven by GPIO11,
and not GPIO115. Hence, the boot buffer is now
disabled at startup, allowing correct detection of
boot switches.
Loopback
connection
added
between
MMC2 CLK and MMC2 CLKIN on processor.
22 ohm series resistors (R38, R83, R85, R331,
R338 and R462) have been added to all SD card
traces.
10k pull-up resistor (R465) was added to keep
PWR KILL net high during the reset.
A RC delay circuit (R469, C562) is added that
only enables the CX4 optical power if the output
of the detection circuit is high for at least 100ms.
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6*
AM3517 boot ROM cannot boot from SD card,
as SD clock (which is generated by processor) is not fed back to clock feedback input
(MMC2 CLKIN).
Possible overshoot on SD card traces. However,
processor still able to read and write card without
errors.
Pressing the reset button powers down the processor, instead of resetting it.
The FPGA 3.3V power supply trips-out if a CX4
cable is plugged in before the FPGA is powered
up. This is caused by a 2ms glitch in the optical
cable detection circuitry at power-up.
The traffic LED on the 1Gbps Ethernet RJ45 jack
never turns on.
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2
Fault
Processor power supply switches on as soon as
DC power is connected.
FPGA power supplies switch on as soon as DC
power is connected
Processor supply rails VCC 3V3 PROC and
VCC LDOs do not ever turn on, as the enable
inputs are driven by open-collector outputs.
Boot buffer IC (U5) is incorrectly enabled at
power up, causing incorrect detection of boot
switches.
The two USB UART serial ports have RX and
TX traffic LEDs. The silkscreen label DBGx RX
was placed next to the TX LED, and vice versa.
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#
1
Previously, two parallel resistors were used as an
OR-gate for switching the LED on. Instead, two
parallel diodes (D47 and D48) are now used.
The silkscreen labels were swapped around on
the PCB design file.
After these modifications were made to the original design, the first prototype board was able to power up and
run both X-Loader and U-Boot. A USB cable was used to connect the UART USB port to a PC, and the boot
messages were monitored using a serial terminal program. The U-Boot command prompt was then used to
run some rudimentary tests to verify that the processor, the power supplies and USB-to-UART converter were
working correctly. The rest of the board was tested in more detail later, as is described in the next section.
Once the first board was powered up and running, the remaining three prototype boards were checked. Two
of the three boards loaded U-Boot correctly, but one did not. After further investigation, it was discovered
that the DDR2 SDRAM on this board was faulty, as the X-Loader would hang when trying to copy U-Boot
into SDRAM. No shorts or large voids were present on the X-ray for that board. One must therefore conclude
that either one of the DDR2 SDRAM ICs are faulty, or else there is a problem with a PCB trace. Since no
flying-probe or bed-of-nails testing was performed on the bare boards, the second cause is more likely.
100
7.4 R ESULTS OF THE S OFTWARE - BASED T ESTS
Once the boards were powered up and running U-Boot, more detailed hardware tests were carried out. This
involved using either the native U-Boot diagnostic tools, the standalone test applications described in the
previous chapter, or the FPGA test gateware that was developed. The results of these tests are described here.
Oscilloscope plots have been given for a number of tests, which were obtained by probing a via on the relevant
bus during the test. Since the via was typically in the middle of the trace, and the oscilloscope probes were
unterminated, a number of the plots exhibit waveforms with poor signal integrity. Furthermore, 50 ohm probes
could not be used, as the end of the trace was already terminated and, in most cases, the source was not able to
drive two 50 ohm loads. Therefore, the oscilloscope plots shown here are not in anyway demonstrative of the
integrity of the actual waveforms at the receiver. A Tektronix TDS5052B oscilloscope was used for all tests.
7.4.1 The Processor and its Peripherals
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Since most of the tests for the processor and its peripherals were fairly trivial, they will all be discussed
together in this section.
AM3517 ARM Processor
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To verify that the processor itself was working correctly, X-Loader and U-Boot were run from an SD card,
and the terminal output was monitored using a serial terminal application on a PC. The terminal output during
a successful boot is given below:
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Texas Instruments X-Loader 1.46 (Dec 23 2010 - 19:50:17)
Starting X-loader on MMC
Reading boot sector
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220504 Bytes Read from MMC
Starting OS Bootloader from MMC...
Starting OS Bootloader...
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U-Boot 2009.11-svn436 (Feb 08 2011 - 01:40:39)
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OMAP34xx/35xx-GP ES1.0, CPU-OPP2 L3-165MHz
AM3517RHINO Board + LPDDR/NAND
I2C:
ready
DRAM: 256 MB
NAND: 256 MiB
In:
serial
Out:
serial
Err:
serial
Die ID #5202000100000000015da39601021017
Net:
davinci_emac_initialize
Ethernet PHY: GENERIC @ 0x01
DaVinci EMAC
Hit any key to stop autoboot: 10 9 8 7 6
No MMC card found
Booting from nand ...
5
4
NAND read: device 0 offset 0x280000, size 0x400000
4194304 bytes read: OK
Wrong Image Format for bootm command
ERROR: can’t get kernel image!
AM3517_RHINO #
101
3
2
1
0
Processor DDR2 SDRAM
U-Boot contains an integrated memory test application. This application checks both the integrity of the
memory, as well as the integrity of the signal traces. It checks for stuck-high, stuck-low and shorted pins. The
test was run five times, over a period of a few hours, and no errors were detected.
(a) Clock CK N and CK P
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Figure 7.6a shows the oscilloscope traces for the two halves of the differential clock, while Figure 7.6b shows
the trace for address line A1. While the address line is as clean as one would wish, the clock line does not
exhibit fast rise and fall edges. This may be due to slow rise times at the output, or due to reflections caused
by an incorrectly terminated oscilloscope probe. Nevertheless, the DDR2 still passes the memory tests.
(b) Address A1
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Figure 7.6: DDR2 SDRAM oscilloscope traces
SD Card Connector
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Since both the X-Loader and U-Boot were correctly read from the SD card and executed, one can only conclude that the SD card connector works correctly.
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100Mbps Ethernet PHY
To test the Ethernet PHY circuitry, an Ethernet cable was used to connect the processor’s Ethernet jack to
a PC. The TFTP (trivial file transfer protocol) tool built into U-Boot was then used to copy a file from the
PC to the board. The terminal output from this transfer is shown below. As can be seen, the entire file
(rhino psu enable.bin) was successfully transferred.
AM3517_RHINO # tftp 0x80300000 rhino_psu_enable.bin
Using DaVinci EMAC device
TFTP from server 192.168.0.100; our IP address is 192.168.0.1
Filename ’rhino_psu_enable.bin’.
Load address: 0x80300000
Loading: **#
done
Bytes transferred = 642 (282 hex)
AM3517_RHINO #
102
NAND Flash
To test the NAND flash memory, the X-Loader and U-Boot images were copied from a PC, across the network,
into the processor’s SDRAM. These bootloader images were then written to the NAND flash using U-Boot’s
NAND drivers. The SD card was removed and the board power cycled. The board booted correctly into
U-Boot, using the images stored on the NAND flash, proving that the flash memory works correctly.
Real-time Clock
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The real-time clock was tested using the standalone application that was described in the previous chapter
(Rhino RTC Test). This application set the seconds register of the real-time clock to 1, waited four seconds
in a delay loop, and then read the seconds register back. The terminal output from this application is shown
below. The program outputs the value 5, proving that the real-time clock did in fact increment its seconds
register by 4 during the delay.
AM3517_RHINO # go 0x80300000
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## Starting application at 0x80300000 ...
Rhino Real-time Clock Test Program
Seconds: 5.
## Application terminated, rc = 0x0
AM3517_RHINO #
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USB Host Ports, Audio Codec, and Video Transmitter
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None of these peripherals were tested, as no U-Boot drivers were available for any of them. While new drivers
could have been written, this would have been both time consuming, as these are all complex peripherals,
and an inefficient use of time, as working Linux drivers already exist for these peripherals. Since these are
non-critical peripherals, they will only be tested once the Linux port is complete.
7.4.2 Spartan-6 FPGA and its User LEDs
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The FPGA and its peripherals were tested by programming the FPGA with the gateware designs that were
described in the previous chapter. The configuration files (bit files) for these designs were programmed onto
the FPGA using a JTAG programmer that was connected to the FPGA’s dedicated JTAG port. Neither the
processor nor the USB-to-JTAG/I2 C/RS-232 converter could be used to program the FPGA, as the support
software had not yet been developed for these interfaces.
To test the Spartan-6 FPGA itself, the JTAG programmer was connected and the JTAG chain was scanned
using a PC. The Spartan-6 was correctly detected, proving that the FPGA core works correctly. A basic
configuration file, Rhino Blinky, was then downloaded onto the FPGA, which flashed the LEDs correctly.
7.4.3 DDR3 SDRAM
The operation of the DDR3 SDRAM was verified using the DDR3 SDRAM gateware. As has been described,
this test wrote to both SDRAM ICs, and then read the data back. The entire test took 3 seconds to run, and the
results are shown in Table 7.3, with no errors being detected. The signals on two of the traces were captured
by an oscilloscope. Figure 7.7a shows address bits 0 and 1 for the DDR3 0 IC, while Figure 7.7b shows the
LDQS differential data strobe. While the LDQS signal transitions cleanly without overshoot or ringing, the
address signals are not ideal. The overshoot and undershoot, resulting from reflections, is clearly evident.
However, this is most likely due to an unterminated oscilloscope, and not real signal integrity problems.
103
Table 7.3: Status of the FPGA LEDs during the DDR3 SDRAM Test
Meaning
DDR3 0 calibration complete
DDR3 0 test complete
DDR3 0 test passed (no errors)
DDR3 1 calibration complete
DDR3 1 test complete
DDR3 1 test passed (no errors)
Heartbeat
State
On
On (after 3 seconds)
On (after 3 seconds)
On
On (after 3 seconds)
On (after 3 seconds)
Flashing
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LED
0
1
2
3
4
5
6
(b) Data strobe lines LDQS P and LDQS N
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(a) Address lines A0 (top) and A1 (bottom)
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Figure 7.7: DDR3 0 SDRAM oscilloscope traces
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7.4.4 Processor-FPGA Interface
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Both processor software and FPGA gateware was required to test the FPGA-processor interface. The Rhino
GPMC Test application on the processor reads the entire address space, each time ensuring that the FPGA
returns the correct value. The terminal output below shows the six FPGA chip-select regions being read,
followed by an alternating address test (Test 2). No errors were detected. The entire test took 116 seconds,
which gives a net read throughput of 7.7MB/s. The actual throughput in the final Rhino system should be
much higher, as burst mode, more efficient bus transfers and DMA will be used.
AM3517_RHINO # go 0x80300000
## Starting application at 0x80300000 ...
== Rhino GPMC Test ==
Reading data
Read test 1:
Read test 1:
Read test 1:
Read test 1:
Read test 1:
Read test 1:
from FPGA...
testing next
testing next
testing next
testing next
testing next
testing next
CS
CS
CS
CS
CS
CS
region....
region....
region....
region....
region....
region....
104
Read test 2: starting...
Finished reading from FPGA. Number of errors: 0
Writing data to FPGA to flash LEDs
GPMC test finished.
## Application terminated, rc = 0x0
AM3517_RHINO #
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During the write test, the FPGA LEDs were observed. They turned on in the correct order, proving that
the write operation works correctly. Oscilloscope traces were recorded for two of the signals during the
read test: address valid signal nADV and data bit D0. The plot shows four “spikes” in the nADV signal,
representing four bus transfers. In each “spike”, the nADV signal goes low briefly near the beginning of the
transaction, indicating that the address is valid. The signal stays high for the rest of the transfer while data
is present on the bus. Since these plots were recorded during the read test, the data bit D0 is alternately high
and low, representing incrementing data values. These plots show a fair amount of ringing, again due to the
unterminated probe being connected to the middle of the trace.
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Figure 7.8: Oscilloscope traces for the processor-FPGA bus, showing signals nADV (top) and D0 (bottom)
7.4.5 CX4 10Gbps Ethernet Ports
The CX4 ports were tested by connecting a 0.5m CX4 cable from the one port to the other. 10 million packets
were transmitted from each port, while the other port received and checked each packet. The table of status
LEDs below show that no errors were detected on either port after receiving the 10 million packets.
One of the CX4 ports was then connected then connected to a 10Gbps Ethernet PCI-Express card on a PC, to
check that the transceivers would align and synchronise with a different link partner. Figure 7.9 shows that
Windows XP detects the link as being operational. Note that, due to a well-known bug in Windows XP, it
cannot show link speeds higher than 1.4Gbps in the network status dialogue box [58].
Lastly, different length CX4 cables were used to connect one of the CX4 ports on Rhino to a Tektronix
DPO72004 high-speed digital oscilloscope. This oscilloscope was used to produce eye-diagrams for each of
the different cable lengths, with different pre-emphasis settings. Figure 7.10 shows eye diagrams for a 0.5m
cable and a 2m cable, with a pre-emphasis setting of 3.5dB. In both plots, the eye is clearly open and only
minor overshoot is present.
105
Table 7.4: Status of the FPGA LEDs during the CX4 Test
Meaning
CX4 0: link is up and all receivers aligned
CX4 0: test complete
CX4 0: errors were detected
CX4 0: TX or RX local fault
CX4 1: link is up and all receivers aligned
CX4 1: test complete
CX4 1: errors were detected
CX4 1: TX or RX local fault
State after Loopback Test
On
On
Off
Off
On
On
Off
Off
of
C
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e
To
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LED
0
1
2
3
4
5
6
7
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Figure 7.9: Windows XP network status when connected to Rhino via CX4 cable
(a) 0.5m cable
(b) 2m cable
Figure 7.10: Eye diagrams for the XAUI signals on different length CX4 cables
7.4.6 1Gbps Ethernet
The 1Gbps Ethernet gateware carried out three separate tests. The first test verified that the management data
interface worked correctly by reading the Ethernet PHY ID. Table 7.5, which shows the status LEDs for the
106
test, shows that LED 3 was on, indicating that this test passed. The gateware then checked the GMII interface,
by writing to it in loopback mode, and checking the data that was received back. LED 6 and LED 7 show that
this test passed too.
Table 7.5: Status of the FPGA LEDs during the 1Gbps Ethernet Test
Meaning
Register reads (via MDIO) complete
GMII loopback test complete (all packets sent)
GMII loopback test complete (all packets received)
PHY ID correct
Ethernet link up
Link auto-negotiation complete
GMII loopback test passed (data bits)
GMII loopback test passed (control bits)
Line loopback enabled
State after Test
On
On
On
On
On
On
On
On
Flashing at 0.1Hz
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n
LED
0
1
2
3
4
5
6
7
GPIO LED
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To
Lastly, the Ethernet port was connected to a PC equipped with a Gigabit Ethernet card. The line loopback
mode was then switched on and off every 10 seconds, as was indicated by an LED connected to one of the
GPIO lines. A simple C application was written for the PC, which sent a UDP packet to the board once a
second, via the Ethernet link. The traffic on the PC’s Ethernet port was monitored using WireShark, a packet
sniffing tool. When the line loopback was enabled on the Rhino board, Wireshark detected each packet being
correctly echoed back to the PC. When line loopback mode was disabled, no packets were echoed.
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Figure 7.11 gives a Windows XP network connection dialogue box, showing that the PC recognised the Rhino
board as a valid Ethernet device, and correctly auto-negotiated the speed to 1Gbps.
Figure 7.11: Windows XP network status when connected to Rhino via 1Gbps Ethernet cable
7.4.7 FMC Connectors
As was described in the previous chapter, the FMC connectors were tested using the Xilinx FMC debug card,
with jumpers to loopback the data bus. However, before the FPGA gateware could run, the card needed to
be powered up and the clock frequency reprogrammed. The output of the standalone U-Boot application that
performed these operations is shown below. Note that the FMC0 nPRST M2C is detected as being low, which
means that an FMC card has been plugged into FMC connector 0.
107
AM3517_RHINO # go 0x80300000
## Starting application at 0x80300000 ...
== Rhino FMC Control Program ==
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Switching on FMC supplies.
Setting FMC_PG_C2M = 1, FMC0_GA[1:0] = 00, FMC1_GA[1:0] = 01.
Done setting signals.
FMC0_nPRST_M2C> 0
FMC1_nPRST_M2C> 1
Register 7 of SiLab chip was 0. Setting to 0x00
Finished.
## Application terminated, rc = 0x0
AM3517_RHINO #
To
Once the card was powered up, the FPGA was programmed with the FMC test gateware. This gateware
performed both a counting test (write incrementing values to the FMC) and an alternating test (write two data
words with inverse bit values). Table 7.6 shows that both tests passed, for both FMC 0 and FMC 1.
C
State for FMC 0 Test
On
Off
Off
–
On
On
On
Flashing
er
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ty
of
Meaning
FMCx PRSNT
FMCx GA0
FMCx GA1
Unused
All tests finished
Counting test passed
Alternating test passed
Heartbeat
State for FMC 1 Test
On
On
Off
–
On
On
On
Flashing
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LED
0
1
2
3
4
5
6
7
ap
e
Table 7.6: Status of the FPGA LEDs after the FMC Tests
U
Oscilloscope plots were captured for the two of the signals. Figure 7.12a shows the clock signal after it has
been converted from LVDS to single-ended. This signal does not reach either the ground or supply rails, as
the slew rate is too slow. This is because the clock signal is running at 312.5MHz, but the LVDS converter is
only rated for signals up to 250MHz. Although the FPGA does register the clock signals correctly, running
the clock above 250MHz is not advisable for sensitive applications. Figure 7.12 shows the LA00 LVDS
differential data signals for FMC connector 0. This signal, which has a data rate of 75Mbps, is fairly noisy
and has ringing. This is because the Xilinx FMC debug card is unfortunately not designed for high speed: it
has limited impedance control, the differential signals are not always routed together, and the jumpers are not
designed for high-speed signals. Therefore, this particular test failed when the data was clocked at 150Mbps.
However, if a proper high-speed FMC card is used, much better performance can be expected.
7.4.8 GPIO Connector
The GPIO connector was indirectly tested in two previous tests. The 1Gbps Ethernet test used an LED,
connected to one of the GPIO lines, to indicate whether line loopback was enabled. The FMC test used the
RS-232 debug board, which was connected to the GPIO connector, to send debug information to the PC over
a serial cable. Since both of these tests worked correctly, one can assume that the GPIO connector performs
as expected.
108
(b) Differential data pair FMC0 LA00 N and FMC0 LA00 P
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(a) FMC1 CLK0 M2C (single-ended), running at 312.5MHz
To
Figure 7.12: Oscilloscope plots of the FMC signals during testing
e
7.4.9 Power Supply and Management Sub-System
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ap
The Rhino System Monitor U-Boot application was developed to test the power supply and management subsystem. This application took readings from all the sensors every two seconds, and saved the results to a CSV
file. The results of this file are plotted in Figures 7.13, 7.14 and 7.15. In each plot, the power-on and power-off
events are marked with vertical dotted lines.
ty
of
In Figure 7.13, the four FPGA power rails turn on correctly when the FPGA power supplies are switched on.
The vertical axis of each plot is in mV, while the horizontal axis is in seconds.
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In Figure 7.14, the current on the four FPGA rails ramps up when the FPGA is switched on. Once the
FPGA programming has been completed, a significant increase of current is noticed on both the 1.2V FPGA
core supply and the 1.5V FPGA DDR3 supply. This is because the FPGA was programmed with the DDR3
SDRAM memory test. When the FMC cards are eventually switched on, the current on the 3.3V and 12V
FMC rails climbs, while the 2.5V FMC rail remains at zero current (it is not used on the FMC debug card).
Just like the voltage plots, the vertical axis of these plots is in mA.
Lastly, Figure 7.15 shows the FPGA temperature rising once programming begins, and then rising at a faster
rate once the DDR3 SDRAM test is running. However, once the fans are switched on, all three temperatures
start dropping. The vertical axes of the temperature plots are in ∘ C. The fan speeds rise correctly to 90% of
their maximum speed when they are switched on, verifying that the fan speed controller works correctly.
Table 7.7: Comparison of Automated Measurements and Manual Measurements
Reading
12V In
5V Processor
1.2V FPGA
1.5V FGPA
2.5V FPGA
3.3V FPGA
Ambient Temperature
Automated Measurement
12.16V
5.02V
1.22V
1.52V
2.51V
3.31V
30∘ C
109
Manual Measurement
12.16V
5.01V
1.21V
1.51V
2.50V
3.29V
28.2∘ C
12240
12220
12200
12180
12160
12140
12V VOLT
0
50
100
150
200
250
300
0
50
100
150
200
250
300
-500 0
50
100
150
200
250
300
200
350
400
1500
1000
500
1V2 FPGA VOLT
0
350
400
2000
1500
1000
500
1V5 FPGA VOLT
0
350
400
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n
3000
2000
1000
0
50
100
150
-1000 0
50
100
150
50
100
To
0
250
-1000
4000
2V5 FPGA VOLT
350
400
1000
0
5040
200
C
2000
ap
e
3000
300
3V3 FPGA VOLT
250
300
250
300
350
400
5020
5010
0
FPGA
switched on
150
er
si
5000
ty
of
5030
FPGA program
begin
FPGA
program end
5V PROC VOLT
200
FMC cards
switched on
350
400
Fans
switched on
U
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Figure 7.13: Plot of the voltage readings taken by the Rhino System Monitor
The validity of the voltage and temperature readings was checked by taking manual readings with a calibrated
voltmeter and thermometer after the test. These readings were compared to the final system monitor readings
and the results are shown in Table 7.7. All automated voltage measurements are sufficiently close to both the
desired voltage and the manual measurement. The 1.8∘ C difference between the automated and manual temperature readings is due to the slow response time of the mercury thermometer used. Although the accuracy
of the current measurements has not been determined at this stage, they are in line with predicted values.
7.4.10 Summary of Test Results
Since all the software-based tests passed for the processor, FPGA and monitoring sub-systems, one can conclude that Rhino was designed and built correctly. The one test, that although passed, did not perform quite
as well as expected, was the FMC connector test. The fact that the test passed at 75MHz, and not 150MHz,
is most probably due to the design of the Xilinx FMC debug card, and not Rhino itself. This will however
require further testing with high-performance FMC ADC cards before Rhino enters production.
On the software front, other members of the UCT Software-Defined Radio Research Group have recently
110
i
1500
1000
500
0
I
0
f
i
50
12V CURR
!
100
150
200
250
300
100
150
200
250
300
100
150
200
250
300
200
i:
350
400
400
200
1V2 FPGA CURR
0
0
50
I
-200
1000
500
-500
!
i
50
150
50
0
I
-50 0
1V5 FPGA CURR
i
t
i
50
I
I
:
100
I
I
·f
I -
150
I
I
250
I
I
I
I
600
400
I
r
i
50
100
i'
,!
150
0
i'
50
,
100
150
50
0
-50 0
200
300
350
250
.
350
'"
150
200
350
250
300
50
100
400
400
400
3V3 FMC CURR
350
t. ·I· · I·'M . -+r Y 'vW~ v:
0
-20
100
2V5 FPGA CURR
2V5 FMC CURR
ni
v
0
50
U
20
150
er
si
100
40
250
ty
-50
400
3V3 FPGA CURR
300
of
0
200
C
50
i
e
0
-200 0
300
ap
200
350
,,
,,
100
r
w
n
I
0
400
To
0
350
400
12V FMC CURR
150
200
250
300
350
400
450
5V PROC CURR
400
350
0
I
I
50
,--------'-,
"
~I
FPGA
switched on
1
I
I
FPGA program
begin
100
150II
'
I
I
,-'---------,
'
1 1,--------------1 1
FPGA
program end
I
I
200
FMC cards
switched on
1
250
300
350
400
,------'------Fans
1 switched on 1
Figure 7.14: Plot of the current readings taken by the Rhino System Monitor
managed to get Linux running on the processor. A U-Boot application has also been developed that allows the
processor to program the FPGA via the Serial Configuration Interface. These developments prove that Rhino
meets the requirements of running Linux on the processor and having the processor configure the FPGA.
111
34
FPGA TEMP
32
30
28
0
50
100
150
200
250
300
350
400
36
PROC TEMP
34
32
30
0
50
100
150
200
250
300
350
400
34
AMBIENT TEMP
32
30
28
0
50
100
150
200
250
300
350
400
8000
FAN1 RPM
4000
2000
0
50
100
150
200
250
300
To
0
w
n
6000
8000
6000
350
400
FAN2 RPM
e
4000
0
100
150
FPGA
program end
FPGA program
begin
200
FMC cards
switched on
250
300
350
400
Fans
switched on
of
FPGA
switched on
50
C
0
ap
2000
er
si
7.5 E STIMATED B OARD C OST
ty
Figure 7.15: Plot of the temperature and fan speed readings taken by the Rhino System Monitor
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Once the initial prototypes were working, quotes were obtained from manufacturers for producing larger
volumes of the Rhino board. Below is the cost per board, if manufactured in quantities of 100. The cost of
the enclosure (which has had some preliminary design and costing done), power supply and cabling has also
been included. Therefore, the total below represents the total estimated cost price for producing a complete
Rhino system. FMC mezzanine cards obviously need to be purchased separately at an additional cost.
Table 7.8: Estimated System Cost for Rhino
Components from Digi-Key
PCB manufacturing by Vector Fabrication
Assembly by Tellumat
Power supply, cabling, etc
Enclosure (estimate)
Total
$905
$300
$280
$70
$80
$1635
Since the intention of producing Rhino is not to make a profit, but rather to aid research and training, one
should be able to sell a complete Rhino system for $1700. This takes into account price fluctuations and
administrative costs. Interestingly enough, this is the same price as the USRP N200 series, but Rhino offers
far higher performance. Since the requirements that were identified in Chapter 1 stated that the board should
cost less the $1800, the cost shown above meets the requirements.
112
CH A P T E R 8
C ONCLUSIONS AND F UTURE W ORK
ap
8.1 S UMMARY OF THE R HINO D ESIGN P ROCESS
e
To
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With Rhino fully designed, the board manufactured and the system tested, conclusions can now be drawn
regarding the success of this project. This chapter therefore begins with a brief summary of the design process
that took Rhino from concept to working system. The system architecture, test results and estimated costs are
then analysed to determine whether the final Rhino design meets the specification given in Chapter 3. Finally,
the work still remaining for Rhino is discussed.
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The design process began by determining the basic requirements for a low-cost FPGA board for training and
research, by obtaining input from specialists in the relevant target application fields. Existing FPGA boards
were then reviewed to (a) determine if any of these boards met the requirements for the proposed low-cost
FPGA board, and (b) identify the main pros and cons of each board. Although none of these boards met all
the necessary requirements, the analysis of the relative strengths and weaknesses allowed guidelines to be
developed for Rhino which built on the existing good ideas, and avoided the common pitfalls.
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In Chapter 3, these guidelines were combined with the original customer specification and the requirements
analysis to formulate a detailed specification for Rhino. This detailed specification guided all subsequent
design decisions. The main electrical components were then selected to meet this specification.
U
With the detailed specification defined and the main components selected, the actual design could begin.
This was started by expanding the high-level block diagram to obtain a sub-system diagram. This was then
transferred to schematics, where each sub-system block became a schematic sheet. Once the schematics
were complete, the PCB design began. The theory behind the routing of high-speed digital signals was first
reviewed. This then lead to the development of the routing rules and PCB stackup that were used to avoid
signal integrity problems. Although the actual routing itself was outsourced to SunCad Designs, all the highspeed traces were checked for signal integrity problems via simulation.
Both hardware and software tools were developed to verify that Rhino was designed and manufactured correctly. A test rig was built to provide the necessary support infrastructure (power, fans, etc.) and debugging
hardware. Software was developed for the processor and gateware for the FPGA to test all the on-board
components. Finally, these tests were run on a manufactured Rhino board, with the board passing all tests.
113
8.2 C ONCLUSIONS
Chapter 7 showed that Rhino was successfully manufactured and passed all the software tests, proving that
all the sub-systems operated correctly at full performance. However, one still needs to determine whether
the completed Rhino system meets all the requirements that were identified in Chapter 1 and the detailed
specification that was developed in Chapter 3. Table 8.1 is given below to help determine this. It gives each
of the points in the detailed specification from Section 3.1 and indicates whether or not they were met.
Table 8.1: Comparison of the Detailed Rhino Specification and the Manufactured Board
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Met
Met
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Processor
Networking
I/O Interface
of
FPGA Networking
Processor has flash memory
for storing operating system.
A high-speed 20Gbps connection and a slower 1Gbps
Ethernet connection
Ethernet connection for control
Two 32-bit LVDS interfaces
with industry-standard connector.
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Flash memory
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Memory
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Processor
To
Spartan-6 FPGA with sufficient logic resources and 64
LVDS pairs for FMC cards.
Any TI ARM processor that
is supported by Linux.
1GB of SDRAM for FPGA,
with throughput of 20Gbps.
Sufficient SDRAM for processor to run Linux.
Comments
Processor-FPGA interface passed all tests. UBoot standalone application able to program
FPGA.
Met
Largest Spartan-6 FPGA used, with sufficient
logic resources. The two FMC connectors together provide 68 LVDS data pairs.
Met
The AM3517 is used on Rhino, with Linux
successfully running on it.
Partially FPGA has 512MB of DDR3 SDRAM, with
met
25.6Gbps throughput. Can be upgraded to
1GB once bigger ICs available. The processor
has 256MB SDRAM, enough to run Linux.
All memory ICs were successfully tested.
Met
Processor is supplied with 256MB NAND
flash, which passed all U-Boot tests.
Met
Both the CX4 and the 1Gbps Ethernet connections passed the software tests.
e
FPGA
Met?
Met
ap
Specification
Processor used to control and
program FPGA.
C
Category
Architecture
Clock Synchronisation
System Monitoring
Cost
Mechanism to synchronise
clocks on different boards to
within 10ns.
All voltages, currents, temperatures and fan speeds
must be monitored.
Rhino must cost less than
$1800 to manufacture
Met
Met
Met
Processor has 100Mbps Ethernet link, which
has successfully been used for TFTP.
Two industry-standard FMC connectors are
used, which provide 34 LVDS data pairs per
connector. The FMC connectors passed testing at 75MHz.
The 100Mbps Ethernet PHY implements the
Precision Time Protocol, allowing clock synchronisation to within 10ns.
The Rhino System Monitor application provided all the required readings, with acceptable accuracy.
The estimated cost price for a complete Rhino
system is $1635.
The only aspect where there is partial compliance is the FPGA SDRAM, which can be met as soon as larger
RAM ICs are available. It is assumed that the FMC interface meets the performance requirement of 400Mbps
per line, but this can only be tested once a high-speed FMC card is available. Therefore, one can conclude
from the table above that Rhino does in fact comply with the detailed specification that was drawn up at
the beginning of the project. This means that Rhino also meets the customer specification, the performance
114
requirements, and the guidelines based on the review of existing boards.
8.3 F UTURE W ORK FOR R HINO
Much work still remains for Rhino, with the obvious tasks being the development of processor firmware,
drivers, gateware libraries for the FPGA and a development toolchain. However, since this thesis focuses on
the hardware of Rhino, only the remaining hardware items will be discussed here.
8.3.1 Manufacture Next Revision of Rhino with the Necessary Modifications
The first task is to spin a new version of the PCB that fixes the hardware bugs in the current revision. These
bugs were identified in Table 7.2, as well as their fixes. These changes have already been made on the
schematics; they still however need to be transferred to the PCB design file, and then manufactured.
To
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Besides these bugs, there are also a few non-critical changes that would further enhance the Rhino board.
These changes have not yet been implemented, but it is strongly recommended that they are included in the
next revision of the board:
ap
e
∙ Currently, the virtual serial port used for the processor terminal closes whenever the board is turned off,
as the FTDI USB-to-JTAG/I2 C/RS-232 chip is powered off the processor power supply. This causes the
serial terminal application on the PC to crash. Powering this IC off the USB port instead would allow
the serial port to remain open while the board power is cycled.
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∙ The current for all the power, status and GPIO LEDs should be reduced. At present, the current through
each LED s 10mA, consuming a total of 0.9W if all LEDs are switched on. If the LED current is halved,
0.45W will be saved, and the LEDs will still be clearly visible.
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∙ The boot switch table on the silkscreen on the PCB should be rotated by 180∘ , so that it has the same
orientation as the boot switches.
The last change to the board is to replace the FPGA DDR3 SDRAM ICs with 4Gb devices, if they are available.
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8.3.2 Further Reduce Board Cost
U
Although the Rhino board meets cost requirements, the cost could be further reduced if the PCB was reduced
from 16 layers to 14 layers. The details of how this can be achieved were described in Section 5.3.
8.3.3 Upgrade to SFP+ Network Connectors
The Rhino design team only became aware of the low availability of new CX4 network switches at a late
stage in the design process. As a result, Rhino was manufactured with CX4 network connectors. It may
be advantageous to consider changing to SFP+ network connectors in future revisions. However, before this
decision can be made, it will be necessary to take a survey of typical Rhino users to determine what percentage
uses CX4 switches and what percentage uses SFP+ switches. If the majority of users only have CX4 hardware,
then the CX4 connectors will probably remain, as purchasing new network switches is an expensive exercise.
8.3.4 Build the Rhino Hide
The last remaining hardware task is to build a rack-mount enclosure for Rhino. The specification for this
enclosure, named the Rhino Hide, was developed as part of this thesis. The proposed layout for the Rhino
Hide is given in Appendix C, while the full specification is given on the attached CD.
115
AP P E N D I X A
I/O I NTERFACE R EQUIREMENTS
To
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The input-output requirements for each target application for Rhino (namely radar, radio astronomy and bioinformatics) were given in Table 1.1 in Chapter 1. However, in order to determine the exact number of I/O lines
necessary to interface the ADCs and DACs with the FPGA, as well as the required data rate of each line, some
calculations are required. These calculations are outlined in this appendix.
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C
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e
There are two concepts that must be understood before the calculations can make sense. These are complex
(I/Q) sampling and differential signalling. In complex sampling, both the original signal (in-phase, I) and a
90∘ phase-shifted version of the signal (quadrature, Q) are sampled. This allows a bandwidth equal to the
sampling rate to be sampled (i.e. a 500MHz bandwidth can be sampled at 500MS/s). The disadvantage is that
the number of bits required to represent each sample is doubled, as both the I and Q signals must be sampled.
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ty
Digital differential signalling uses two separate signals to convey a single bit. The value of the bit is determined by the voltage difference between the two signals. Although this requires twice the number of signals
as single-ended signalling, it does improve signal integrity and noise immunity, as we look only at the difference between two signals, and not the absolute value of each one. Because of this, low-voltage differential
signalling (LVDS), one of the more popular differential signalling standards, is used for the interface between
the ADCs/DACs and the FPGA.
U
A.1 I/O R EQUIREMENTS FOR R ADAR A PPLICATIONS
For the radar I/O calculations, we assume that:
∙ There is one ADC and one DAC connected to the Rhino board.
∙ Both the ADC and DAC have 12-bit resolution, and support a 400MHz bandwidth (as per the requirements in Table 1.1).
∙ I/Q sampling is used.
∙ The ADCs and DACs use LVDS for the digital data lines.
Therefore:
∙ The sampling rate is 400MS/s.
116
∙ Each ADC/DAC has 24 LVDS pairs (12 bits for I and 12 bits for Q), each pair with a data rate of
400Mbps.
∙ Since the board needs to support both an ADC and a DAC, two separate 24-bit buses are required.
A.2 I/O R EQUIREMENTS FOR R ADIO A STRONOMY A PPLICATIONS
For the radio astronomy I/O calculations, we assume that:
∙ There are two ADCs connected to the Rhino board.
∙ The ADCs have 8-bit resolution, and support a 500MHz bandwidth (as per the requirements in Table
1.1).
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n
∙ I/Q sampling is used.
To
∙ A demux factor of two is used in the ADC. This means that the ADC demultiplexes the digital output
signals by a factor of two, resulting in twice as many digital outputs from the ADC, but each running at
half the original data rate.
ap
e
∙ The ADCs use LVDS for the digital data lines.
∙ The sampling rate is 500MS/s.
ty
∙ Number of LVDS pairs is given by:
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Therefore:
= (8 bits) * 2 * 2
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(sampling resolution) * (demux factor) * 2 (for I and Q)
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= 32 LVDS pairs per ADC
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∙ Since a demux factor of two is used, the data rate is half the sampling rate. Therefore, each LVDS pair
runs at 250Mbps.
∙ Since the board needs to support two ADCs, two separate 32-bit LVDS buses are required.
117
AP P E N D I X B
F ULL R HINO S CHEMATICS
To
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The complete Rhino schematics can be found on the following pages. The contents page at the beginning of
the schematics should be helpful when trying to navigate to a particular schematic.
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It is strongly suggested that these schematics be read in conjunction with Chapter 4: Schematic-level Hardware Design of Rhino.
118
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Published: 11/02/2011
Revision: 1.1
Schematics
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RHINO
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FPGA
Processor
FPGA-Processor Bus
ty
2x 256MB DDR3 SDRAM
of
256MB DDR2 SDRAM
ARM Core
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Texas
Instruments
AM3517
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Xilinx Spartan-6
XC6SLX150T
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256MB NAND Flash
2x FMC Connectors
D
D
D
D
2x 1OGbps CX4 Connectors
rhino_contents
D
rhino_power_distrib
rhino_top_level
(C) 2011 Alan Langman and Simon Scott
1
2
3
4
D
C
B
A
120
Page
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
1
1
2
ty
of
To
w
n
3
3
Schematic
AM3517 Peripherals (Part A)
AM3517 Peripherals (Part B)
AM3517 Power
AM3517 Supply Decoupling Caps
AM3517 DDR2 RAM (top level)
DDR2 RAM 0
DDR2 RAM 1
NAND Flash
100Mbps Ethernet PHY
RS-232 Header for Peripherals
AM3517 Clocks
USB On-the-Go
USB Host Transceivers
SD Card and Real-time Clock
HDMI Video Transmitter
Audio
USB to JTAG/I2C/RS-232
JTAG Chain
Configuration Interface Level Translator
Power Supply Management
Spartan-6 Power Supplies
Spartan-6 LDO Power Supplies
FMC Power Supply Switches
Si6463BDQ FET Load Switch 0
Si6463BDQ FET Load Switch 1
Si6463BDQ FET Load Switch 2
Si6463BDQ FET Load Switch 3
AM3517 Power Supply
Power Monitor
Temperature Monitor and Fan Controller
Power LEDs
Mounting Holes and Fiducials
e
ap
C
Page
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
Table of Contents
er
si
ni
v
U
Schematic
Table of Contents
Rhino Power Distribution and Monitoring
Rhino Overview
Spartan-6 (top level)
Spartan-6 Bank 0
Spartan-6 Bank 1
Dual LVDS Receiver 0
Spartan-6 Bank 2
Spartan-6 Bank 3
Dual LVDS Receiver 1
Spartan-6 Bank 4
Spartan-6 Bank 5
Spartan-6 Multi-Gigabit Transceivers
Spartan-6 Configuration
Spartan-6 Power
Spartan-6 Supply Decoupling Caps
DDR3 RAM 0
DDR3 RAM 1
FMC 0 HPC Connector (top-level)
FMC 1 HPC Connector (top-level)
FMC 0 HPC Connector (Rows A, B, C, D)
FMC 1 HPC Connector (Rows A, B, C, D)
FMC 0 HPC Connector (Rows E, F, G, H)
FMC 1 HPC Connector (Rows E, F, G, H)
FMC 0 HPC Connector (Rows J, K and Ground)
FMC 1 HPC Connector (Rows J, K and Ground)
CX4 10Gbps Ethernet Connector 0
CX4 10Gbps Ethernet Connector 1
1 Gbps Ethernet PHY
Spartan-6 GPIO Header and LEDs
Spartan-6 Clocks
AM3517 (top-level)
2
4
4
D
C
B
A
1
2
3
4
Rhino Power Distribution and Monitoring
Front Panel 10
A
PowerSW
J
[ Status LEDs
SPI I/O
Expander
I
A
SPI
J
r----~
, ~
2
1 C Power
~M:a:=.m:1 ~s )
Button Press
~ 12V in
Yin
AC/DC
I
Push-button
Controller
~
Killin
I
Enable Out
GPIO Oul
n
l
External supply or
power brick
FPGA and FMC Power Generation
12V
1£ g
1VS
Supply
6A
'--~
~
En
3V3
Supply
10A
~t;J
-=n=
~
~
~
1
1
~
~
~
C
( 1NA219s '"'I
I used for
I
I power
l monitorin I I
-'
D
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FPGA Supplies
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FPGA and its Peripherals
FMC
Supplies
Incoming & Proc
Supply
~l ~I
i
PROC 3V3
12C
5M Bu5
I
~
FPGA
Heatsink
ARM
Heatsink
Sensor
Sensor
~
PROC 3V3
Processor Power Generation
Ambient
Temperature
Sensor
2
C
~ AC97 Codee (analogue)
FM C LPC Connector (x2)
Case Fan
Case Fan
Connector a
Connector 1
1
USB Hosl Port (x2)
J
1t t 1
12V
1
1
Monitor/Management
Subsystem
Fan controller: 2 channels
12C
5MBu5
Vee
12C
5MBus
D
T
PROC 3V3
--
r-
12C
1
f
~
T
1
Multi-channel Supply
(TPS6S023)
1V2: 1.7A
1V8: 1A
3V3: 1A
12C
Vin
Interface
SV Supply
6A
'--~
Temperature Monitor: 3 channels
Vee
i:;
En
9
I I
~ ~
Voltage/CurrenUPower Monitor: 10 channels
Vee
Vln
FET
Switch
1V2 - MGT
lOO 1.SA
~
,..- L..- <-..,
~
FET
Switch
~
B
Switch
'-- r---" ' - - r---"
OV7S - VTT
lOO 3A
~
Yin
rs
i
121
'-----
En
2VS
Supply
10A
C
ap
Yin
En
1V2
Supply
6A
12V
~
of
Vin
GPIO Oul
e
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B
AM3517 ARM
Processor and
Peripherals
Interr~ ln
Inlerrupl
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To
w
240V
J
--
12 C Power
I
~M:a~m~t ~s J
3
4
I
1
FMC_1
() ()UUU
D
FMC_1
!l
o
122
"
MGT_CLKS
3
(C) 2011 Alan Langman and Simon Scott
Ii
2
nn
FPGA_SYS_CLK
mounting_holes_fids
Date:
File:
A4
Size
Title
AUDIO_CTRL
29/03/2011
C:\Users\..\rhino_top_level.SchDoc
RHINO
Number
Project
FP_SPI_PROC
SUPPLY_EN
WARN_OUT
PWR_KILL
usb_host
OTG_OC
USB_OTG
usb_otg
4
Sheet 4 of
Drawn By:
1.0
65
Simon Scott
Revision
AUDIO_DATA
AUDIO_CTRL
audio
DDC_I2C
DVI
video
SD_BUS
RTC_SQW/INT
RTC_SPI
sd_card_and_rtc
HS_USB2
USB2_OC
USB2_RST
HS_USB1
USB1_OC
USB1_RST
FP_I2C_FPGA
pwr_supply_management
OVER_TEMP
FP_I2C_FPGA
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
AUDIO_DATA
Rhino Overview
CLKS_IN
J J
oJ
MGT_CLKS_IN
SYS_CLK
spartan6_clocks
PROC_CLKS
am3517_clocks
RS232_DATA
RS232_CTRL
J J
FMC_BUS
fmc_1
RS232_DATA
RS232_CTRL
DDC_I2C
DVI
FTDI_SUPPLY_EN
I2C_PWR_MAN
o0
CX4_BUS
w
n
NAND
0
cx4_1
periph_rs232
NAND_BUS
I' ,-
CX4_BUS
UO
CX4_1
CX4_0
)
FMC_0
I'
no )
FMC_BUS
To
I
FMC_0
"
nand_flash
on 0 oO(ln
FPGA_PROC_BUS
RTC_SQW/INT
FMC_0_CTRL
RTC_SPI
FMC_1_CTRL
FPGA_AWAKE
SD_BUS
FPGA_SUSPEND
"
I
FPGA_CONFIG
INIT_B_DIR
~
e
ap
FPGA_CONFIG_3V3
OUO OUU
cx4_0
C
CONFIG_3V3
INIT_B_DIR
HS_USB2
USB2_OC
USB2_RST
HS_USB1
USB1_OC
USB1_RST
,J
FMC_0_CTRL
FMC_1_CTRL
FPGA_AWAKE
SUSPEND
CONFIG_2V5
~
FMC_0_CTRL
FMC_1_CTRL
FPGA_CONFIG_2V5
config_lvl_xlator
of
DDR2
II II
FPGA_PROC_BUS
FPGA_CONFIG
ty
DDR2
4
OOD
fmc_0
DDR3_1
GPIO[15..0]
ou
PROC_DDR2_BUS
I ~:I
GPIO[15..0]
USER_LED[7..0]
0 U
II II
C
DDR3_1
on
am3517_ram
~I~~
;I ~_ _ _ _-+
IJ ~__~~.~~
,J ~~~I'~_ _~~_ _-*~
OVR_T
ii
,-
oon
DDR3_BUS
[C
USER_LED[7..0]
o
ram_ddr3_1
() 0
er
si
o0
spartan6_gpio
(
OTG_OC
USB_OTG
V
1588_GPIO[3..0]
onn 00
1588_CLK
1588_GPIO[3..0]
ETH_RMII
ETH_RESET
ETH_PWRDWN
PROC_JTAG
l JUU
1588_CLK2
1588_CLK1
1588_GPIO[3..0]
RMII
RESET
PWRDWN/INT
JTAG
II
I
0 0
B
ni
v
( (
1588_CLK
o
JTAG
"
OUU
DDR3_0
000
CTRL
II II
GIGE_CTRL
01)00
GMII
IJ
DDR3_0
U
I
II
DDR3_BUS
ram_ddr3_0
GIGE_GMII
U
100mbps_ethernet
DBG_UART0 I2C_PWR_MAN
DBG_UART1
FP_SPI_PROC
SUPPLY_EN
USB_I2C_EN
PWR_WARNS
PWR_KILL
am3517
n
1gbps_ethernet
I2C_EN
'v
usb_to_jtag_rs232
JTAG
UART0
UART1
FPGA_SUPPLY_EN
I2C
~o
jtag_chain
FMC_0_CTRL
FMC_1_CTRL
FPGA_JTAG
FMC_0_JTAG
FMC_1_JTAG
JTAG_MASTER
PROC_JTAG
100M_JTAG
1G_JTAG
,',J
FPGA_RESET
FP_I2C_FPGA
FPGA_JTAG
FMC_0_JTAG
FMC_1_JTAG
FMC_0_CTRL
FMC_1_CTRL
3
"':nn 0
OVR_T
FP_I2C_FPGA
spartan6
2
" ~~~
m
A
Reconfigurable Hardware Interface
for computatioN and radiO
RHINO
1
o
C
B
A
D
I
f-I--
I---
-
"
I---
0
A
I
1
DONE
PROGRAM_B
INIT_B
CCLK
DIN
FPGA_CONFIG_BUS
CONF_INIT_B
CONF_CCLK
CONF_DIN
2
e
0
I
3
MGT_CLKS_IN
spartan6_decoupling
10GBE_1
w
n
()
10GBE_0
spartan6_mgt
To
MCB5_DDR3
spartan6_bank5
ap
()
spartan6_power
SUSPEND
RESET
CONF_DONE
CONF_PROGRAM_B
FPGA_JTAG
spartan6_config
J "0
()
~
POF\P\G\A\0\R\E\S\E\T\
FPGA_RESET
TIn
CONET0TIE8
CONF_INIT_B
CONF_CCLK
CONF_DIN
FMC_0_ZDOK_P[3..2]
FMC_0_ZDOK_N[3..2]
FMC0_LA_P[33..0]
FMC0_LA_N[33..0]
spartan6_bank2
C
-
29/03/2011
C:\Users\..\spartan6.SchDoc
RHINO
Number
Project
4
Sheet 5 of
Drawn By:
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
1.0
65
Simon Scott
Revision
MGT_CLKS_IN
POMGT0CLKS0IN0MGT0CLK10P
POMGT0CLKS0IN0MGT0CLK10N
POMGT0CLKS0IN0MGT0CLK00P
POMGT0CLKS0IN0MGT0CLK00N
POMGT0CLKS0IN
POCX4010TX30P
POCX4010TX30N
POCX4010TX20P
POCX4010TX20N
POCX4010TX10P
POCX4010TX10N
POCX4010TX00P
POCX4010TX00N
POCX4010RX30P
POCX4010RX30N
POCX4010RX20P
POCX4010RX20N
POCX4010RX10P
POCX4010RX10N
POCX4010RX00P
POCX4010RX00N
POCX401
CX4_1
CX4_0
POCX4000TX30P
POCX4000TX30N
POCX4000TX20P
POCX4000TX20N
POCX4000TX10P
POCX4000TX10N
POCX4000TX00P
POCX4000TX00N
POCX4000RX30P
POCX4000RX30N
POCX4000RX20P
POCX4000RX20N
POCX4000RX10P
POCX4000RX10N
POCX4000RX00P
POCX4000RX00N
POCX400
PODDR3010W\E\
PODDR3010UDQS0P
PODDR3010UDQS0N
PODDR3010UDM
PODDR3010R\E\S\E\T\
PODDR3010R\A\S\
PODDR3010ODT
PODDR3010LDQS0P
PODDR3010LDQS0N
PODDR3010LDM
PODDR3010DQ0150000
PODDR3010DQ15
PODDR3010DQ14
PODDR3010DQ13
PODDR3010DQ12
PODDR3010DQ11
PODDR3010DQ10
PODDR3010DQ9
PODDR3010DQ8
PODDR3010DQ7
PODDR3010DQ6
PODDR3010DQ5
PODDR3010DQ4
PODDR3010DQ3
PODDR3010DQ2
PODDR3010DQ1
PODDR3010DQ0
PODDR3010CKE
PODDR3010CK0P
PODDR3010CK0N
PODDR3010C\A\S\
PODDR3010BA020000
PODDR3010BA2
PODDR3010BA1
PODDR3010BA0
PODDR3010A0130000
PODDR3010A13
PODDR3010A12
PODDR3010A11
PODDR3010A10
PODDR3010A9
PODDR3010A8
PODDR3010A7
PODDR3010A6
PODDR3010A5
PODDR3010A4
PODDR3010A3
PODDR3010A2
PODDR3010A1
PODDR3010A0
PODDR301
DDR3_1
FMC_0_JTAG
FMC_1_JTAG
POFMC010CTRL0PG0C2M
POFMC010CTRL0P\R\S\N\T\0\M\2\C\
POFMC010CTRL0I2C0SDA
POFMC010CTRL0I2C0SCL
POFMC010CTRL0GA1
POFMC010CTRL0GA0
POFMC010CTRL
FMC_1_CTRL
POFMC000CTRL0PG0C2M
POFMC000CTRL0P\R\S\N\T\0\M\2\C\
POFMC000CTRL0I2C0SDA
POFMC000CTRL0I2C0SCL
POFMC000CTRL0GA1
POFMC000CTRL0GA0
POFMC000CTRL
FMC_0_CTRL
POFP0I2C0FPGA0SDA
POFP0I2C0FPGA0SCL
POFP0I2C0FPGA
FP_I2C_FPGA
POFPGA0AWAKE
FPGA_AWAKE
POSYS0CLK0SYS0CLK0P
POSYS0CLK0SYS0CLK0N
POSYS0CLK
SYS_CLK
PODDR3000W\E\
PODDR3000UDQS0P
PODDR3000UDQS0N
PODDR3000UDM
PODDR3000R\E\S\E\T\
PODDR3000R\A\S\
PODDR3000ODT
PODDR3000LDQS0P
PODDR3000LDQS0N
PODDR3000LDM
PODDR3000DQ0150000
PODDR3000DQ15
PODDR3000DQ14
PODDR3000DQ13
PODDR3000DQ12
PODDR3000DQ11
PODDR3000DQ10
PODDR3000DQ9
PODDR3000DQ8
PODDR3000DQ7
PODDR3000DQ6
PODDR3000DQ5
PODDR3000DQ4
PODDR3000DQ3
PODDR3000DQ2
PODDR3000DQ1
PODDR3000DQ0
PODDR3000CKE
PODDR3000CK0P
PODDR3000CK0N
PODDR3000C\A\S\
PODDR3000BA020000
PODDR3000BA2
PODDR3000BA1
PODDR3000BA0
PODDR3000A0130000
PODDR3000A13
PODDR3000A12
PODDR3000A11
PODDR3000A10
PODDR3000A9
PODDR3000A8
PODDR3000A7
PODDR3000A6
PODDR3000A5
PODDR3000A4
PODDR3000A3
PODDR3000A2
PODDR3000A1
PODDR3000A0
PODDR300
DDR3_0
POGPIO0150000
POGPIO15
POGPIO14
POGPIO13
POGPIO12
POGPIO11
POGPIO10
POGPIO9
POGPIO8
POGPIO7
POGPIO6
POGPIO5
POGPIO4
POGPIO3
POGPIO2
POGPIO1
POGPIO0
GPIO[15..0]
POUSER0LED070000
POUSER0LED7
POUSER0LED6
POUSER0LED5
POUSER0LED4
POUSER0LED3
POUSER0LED2
POUSER0LED1
POUSER0LED0
USER_LED[7..0]
POGIGE0CTRL0R\E\S\E\T\
POGIGE0CTRL0MDIO
POGIGE0CTRL0MDC
POGIGE0CTRL0I\N\T\
POGIGE0CTRL0COMA
POGIGE0CTRL
GIGE_CTRL
POGIGE0GMII0TXD7
POGIGE0GMII0TXD6
POGIGE0GMII0TXD5
POGIGE0GMII0TXD4
POGIGE0GMII0TXD3
POGIGE0GMII0TXD2
POGIGE0GMII0TXD1
POGIGE0GMII0TXD0
POGIGE0GMII0TX0ER
POGIGE0GMII0TX0EN
POGIGE0GMII0TX0CLK
POGIGE0GMII0RXD7
POGIGE0GMII0RXD6
POGIGE0GMII0RXD5
POGIGE0GMII0RXD4
POGIGE0GMII0RXD3
POGIGE0GMII0RXD2
POGIGE0GMII0RXD1
POGIGE0GMII0RXD0
POGIGE0GMII0RX0ER
POGIGE0GMII0RX0DV
POGIGE0GMII0RX0CLK
POGIGE0GMII0GTX0CLK
POGIGE0GMII0CRS
POGIGE0GMII0COL
POGIGE0GMII
GIGE_GMII
4
-
Date:
File:
A4
Size
FMC_0_JTAG
FMC_1_JTAG
FMC_1_CTRL
FMC_0_CTRL
FP_I2C_FPGA
FPGA_AWAKE
SYS_CLK
Spartan-6 (top-level)
FMC1_CLK0_M2C_P
FMC1_CLK0_M2C_N
FMC1_CLK1_M2C_P
FMC1_CLK1_M2C_N
FMC_0_ZDOK_P[1..0]
FMC_0_ZDOK_N[1..0]
Title
,,,
SUSPEND
POSUSPEND
x
VADJ PINET0TIE501PINET0TIE502 VCC_2V5_FMC0
PINET0TIE601
PINET0TIE602
3P3VAUXCONET0TIE5
VCC_AUX_FMC0
PINET0TIE701
PINET0TIE702
3P3VCONET0TIE6
VCC_3V3_FMC0
PINET0TIE801
PINET0TIE802 VCC_12V_FMC0
12P0VCONET0TIE7
CONF_INIT_B
CONF_CCLK
CONF_DIN
FMC_0_ZDOK_P[3..2]
FMC_0_ZDOK_N[3..2]
of
FMC0_CLK0_M2C_P
FMC0_CLK0_M2C_N
FMC0_CLK1_M2C_P
FMC0_CLK1_M2C_N
,
FPGA_CONFIG
POFPGA0CONFIG0PROGRAM0B
POFPGA0CONFIG0INIT0B
POFPGA0CONFIG0DONE
POFPGA0CONFIG0DIN
POFPGA0CONFIG0CCLK
POFPGA0CONFIG
FMC_0_ZDOK_P[3..0]
FMC_0_ZDOK_N[3..0]
FMC0_CLK0_M2C_P
FMC0_CLK0_M2C_N
FMC0_CLK1_M2C_P
FMC0_CLK1_M2C_N
ty
()
D
123
ZDOK_P[3..0]
ZDOK_N[3..0]
VREF_A_M2C
FMC0_CLK0_M2C_P
FMC0_CLK0_M2C_N
FMC0_CLK1_M2C_P
FMC0_CLK1_M2C_N
PRSNT_M2C
PG_C2M
('"
FPGA_JTAG
POFPGA0JTAG0TMS
POFPGA0JTAG0TDO
POFPGA0JTAG0TDI
POFPGA0JTAG0TCK
POFPGA0JTAG0T\R\S\T\
POFPGA0JTAG
\.
FMC_0_CTRL
FPGA_AWAKE
MCB4_DDR3
spartan6_bank4
FMC1_LA_P18_CC
FMC1_LA_N18_CC
FMC1_CLK0_M2C_P
FMC1_CLK0_M2C_N
FMC1_CLK1_M2C_P
FMC1_CLK1_M2C_N
FMC_0_ZDOK_P[1..0]
FMC_0_ZDOK_N[1..0]
USER_LED[7..0]
GPIO[15..0]
GIGE_GMII
GIGE_CTRL
spartan6_bank3
3
()
C
x
FMC_0_CTRL
FPGA_AWAKE
(
CLK0_M2C_P
CLK0_M2C_N
CLK1_M2C_P
CLK1_M2C_N
LA_P[33..0]
LA_N[33..0]
FMC_0_JTAG
I2C
GA0
GA1
1588_CLK
1588_GPIO[3..0]
",
I2C
GA0
GA1
JTAG
PRSNT_M2C_L
PG_C2M
FPGA_PROC_BUS
FP_I2C_FPGA
FMC_1_CTRL
er
si
ni
v
FP_I2C_FPGA
FMC_1_CTRL
()()
FMC_0
POFMC000ZDOK0P030000
POFMC000ZDOK0P3
POFMC000ZDOK0P2
POFMC000ZDOK0P1
POFMC000ZDOK0P0
POFMC000ZDOK0N030000
POFMC000ZDOK0N3
POFMC000ZDOK0N2
POFMC000ZDOK0N1
POFMC000ZDOK0N0
POFMC000VREF0A0M2C
POFMC000VADJ
POFMC000PRSNT0M2C0L
POFMC000PG0C2M
POFMC000LA0P0330000
POFMC000LA0P33
POFMC000LA0P32
POFMC000LA0P31
POFMC000LA0P30
POFMC000LA0P29
POFMC000LA0P28
POFMC000LA0P27
POFMC000LA0P26
POFMC000LA0P25
POFMC000LA0P24
POFMC000LA0P23
POFMC000LA0P22
POFMC000LA0P21
POFMC000LA0P20
POFMC000LA0P19
POFMC000LA0P18
POFMC000LA0P17
POFMC000LA0P16
POFMC000LA0P15
POFMC000LA0P14
POFMC000LA0P13
POFMC000LA0P12
POFMC000LA0P11
POFMC000LA0P10
POFMC000LA0P9
POFMC000LA0P8
POFMC000LA0P7
POFMC000LA0P6
POFMC000LA0P5
POFMC000LA0P4
POFMC000LA0P3
POFMC000LA0P2
POFMC000LA0P1
POFMC000LA0P0
POFMC000LA0N0330000
POFMC000LA0N33
POFMC000LA0N32
POFMC000LA0N31
POFMC000LA0N30
POFMC000LA0N29
POFMC000LA0N28
POFMC000LA0N27
POFMC000LA0N26
POFMC000LA0N25
POFMC000LA0N24
POFMC000LA0N23
POFMC000LA0N22
POFMC000LA0N21
POFMC000LA0N20
POFMC000LA0N19
POFMC000LA0N18
POFMC000LA0N17
POFMC000LA0N16
POFMC000LA0N15
POFMC000LA0N14
POFMC000LA0N13
POFMC000LA0N12
POFMC000LA0N11
POFMC000LA0N10
POFMC000LA0N9
POFMC000LA0N8
POFMC000LA0N7
POFMC000LA0N6
POFMC000LA0N5
POFMC000LA0N4
POFMC000LA0N3
POFMC000LA0N2
POFMC000LA0N1
POFMC000LA0N0
POFMC000JTAG0TMS
POFMC000JTAG0TDO
POFMC000JTAG0TDI
POFMC000JTAG0TCK
POFMC000JTAG0T\R\S\T\
POFMC000JTAG
POFMC000I2C0SDA
POFMC000I2C0SCL
POFMC000I2C
POFMC000GA1
POFMC000GA0
POFMC000CLK10M2C0P
POFMC000CLK10M2C0N
POFMC000CLK00M2C0P
POFMC000CLK00M2C0N
POFMC00012P0V
POFMC0003P3VAUX
POFMC0003P3V
POFMC00
FMC_BUS
(
PRSNT_M2C
PG_C2M
U
spartan6_bank1
( ( (
PO15880CLK
1588_CLK
PO15880GPIO030000
PO15880GPIO3
PO15880GPIO2
PO15880GPIO1
PO15880GPIO0
1588_GPIO[3..0]
FMC_1_JTAG
I2C
GA0
GA1
FMC1_LA_P18_CC
FMC1_LA_N18_CC
SYS_CLK
FMC1_LA_P[33..0]
FMC1_LA_N[33..0]
FMC1_ZDOK_P[3..0]
FMC1_ZDOK_N[3..0]
spartan6_bank0
I,J
00
B
\.
I2C
GA0
GA1
JTAG
PRSNT_M2C_L
PG_C2M
VREF_A_M2C
SYS_CLK
2
(
POFPGA0PROC0BUS0W\P\
POFPGA0PROC0BUS0W\E\
POFPGA0PROC0BUS0O\E\
POFPGA0PROC0BUS0D0150000
POFPGA0PROC0BUS0D15
POFPGA0PROC0BUS0D14
POFPGA0PROC0BUS0D13
POFPGA0PROC0BUS0D12
POFPGA0PROC0BUS0D11
POFPGA0PROC0BUS0D10
POFPGA0PROC0BUS0D9
POFPGA0PROC0BUS0D8
POFPGA0PROC0BUS0D7
POFPGA0PROC0BUS0D6
POFPGA0PROC0BUS0D5
POFPGA0PROC0BUS0D4
POFPGA0PROC0BUS0D3
POFPGA0PROC0BUS0D2
POFPGA0PROC0BUS0D1
POFPGA0PROC0BUS0D0
POFPGA0PROC0BUS0CLK
POFPGA0PROC0BUS0C\S\6\0IODIR
POFPGA0PROC0BUS0C\S\5\0D\M\A\R\E\Q\2\
POFPGA0PROC0BUS0C\S\4\0D\M\A\R\E\Q\1\
POFPGA0PROC0BUS0C\S\3\
POFPGA0PROC0BUS0C\S\2\0D\M\A\R\E\Q\0\
POFPGA0PROC0BUS0C\S\1\
POFPGA0PROC0BUS0C\S\0\
POFPGA0PROC0BUS0BUSY1
POFPGA0PROC0BUS0BUSY0
POFPGA0PROC0BUS0A\D\V\0ALE
POFPGA0PROC0BUS0A0100010
POFPGA0PROC0BUS0A10
POFPGA0PROC0BUS0A9
POFPGA0PROC0BUS0A8
POFPGA0PROC0BUS0A7
POFPGA0PROC0BUS0A6
POFPGA0PROC0BUS0A5
POFPGA0PROC0BUS0A4
POFPGA0PROC0BUS0A3
POFPGA0PROC0BUS0A2
POFPGA0PROC0BUS0A1
POFPGA0PROC0BUS
FPGA_PROC_BUS
POFMC010ZDOK0P030000
POFMC010ZDOK0P3
POFMC010ZDOK0P2
POFMC010ZDOK0P1
POFMC010ZDOK0P0
POFMC010ZDOK0N030000
POFMC010ZDOK0N3
POFMC010ZDOK0N2
POFMC010ZDOK0N1
POFMC010ZDOK0N0
POFMC010VREF0A0M2C
POFMC010VADJ
POFMC010PRSNT0M2C0L
POFMC010PG0C2M
POFMC010LA0P0330000
POFMC010LA0P33
POFMC010LA0P32
POFMC010LA0P31
POFMC010LA0P30
POFMC010LA0P29
POFMC010LA0P28
POFMC010LA0P27
POFMC010LA0P26
POFMC010LA0P25
POFMC010LA0P24
POFMC010LA0P23
POFMC010LA0P22
POFMC010LA0P21
POFMC010LA0P20
POFMC010LA0P19
POFMC010LA0P18
POFMC010LA0P17
POFMC010LA0P16
POFMC010LA0P15
POFMC010LA0P14
POFMC010LA0P13
POFMC010LA0P12
POFMC010LA0P11
POFMC010LA0P10
POFMC010LA0P9
POFMC010LA0P8
POFMC010LA0P7
POFMC010LA0P6
POFMC010LA0P5
POFMC010LA0P4
POFMC010LA0P3
POFMC010LA0P2
POFMC010LA0P1
POFMC010LA0P0
POFMC010LA0N0330000
POFMC010LA0N33
POFMC010LA0N32
POFMC010LA0N31
POFMC010LA0N30
POFMC010LA0N29
POFMC010LA0N28
POFMC010LA0N27
POFMC010LA0N26
POFMC010LA0N25
POFMC010LA0N24
POFMC010LA0N23
POFMC010LA0N22
POFMC010LA0N21
POFMC010LA0N20
POFMC010LA0N19
POFMC010LA0N18
POFMC010LA0N17
POFMC010LA0N16
POFMC010LA0N15
POFMC010LA0N14
POFMC010LA0N13
POFMC010LA0N12
POFMC010LA0N11
POFMC010LA0N10
POFMC010LA0N9
POFMC010LA0N8
POFMC010LA0N7
POFMC010LA0N6
POFMC010LA0N5
POFMC010LA0N4
POFMC010LA0N3
POFMC010LA0N2
POFMC010LA0N1
POFMC010LA0N0
POFMC010JTAG0TMS
POFMC010JTAG0TDO
POFMC010JTAG0TDI
POFMC010JTAG0TCK
POFMC010JTAG0T\R\S\T\
POFMC010JTAG
POFMC010I2C0SDA
POFMC010I2C0SCL
POFMC010I2C
POFMC010GA1
POFMC010GA0
POFMC010CLK10M2C0P
POFMC010CLK10M2C0N
POFMC010CLK00M2C0P
POFMC010CLK00M2C0N
POFMC01012P0V
POFMC0103P3VAUX
POFMC0103P3V
POFMC01
FMC_1
TIn
VADJ PINET0TIE101PINET0TIE102 VCC_2V5_FMC1
PINET0TIE201
PINET0TIE202 VCC_AUX_FMC1
3P3VAUXCONET0TIE1
PINET0TIE301
PINET0TIE302
3P3VCONET0TIE2
VCC_3V3_FMC1
PINET0TIE401
PINET0TIE402
12P0VCONET0TIE3
VCC_12V_FMC1
CONET0TIE4
LA_P[33..0]
LA_N[33..0]
ZDOK_P[3..0]
ZDOK_N[3..0]
FMC1_CLK0_M2C_P
CLK0_M2C_P
FMC1_CLK0_M2C_N
CLK0_M2C_N
FMC1_CLK1_M2C_P
CLK1_M2C_P
FMC1_CLK1_M2C_N
CLK1_M2C_N
FMC_BUS
1
IW
A
D
C
B
I
r-
-
-
-
f-
-
f-
B
C
FMC1_LA_P[33..0]
FMC1_LA_N[33..0]
R189
84R5
PIR18 01
PIR18901
GND
PIR190 1
R190
84R5
ty
er
si
ni
v
U
SYS_CLK_P
SYS_CLK_N
PIR18902COR189 PIR190 2COR190
PIR18701
R188
127R
C
FMC1_LA_N18
FMC1_LA_P18
POFMC10LA0N180CC
FMC1_LA_N18_CC
POFMC10LA0P180CC
FMC1_LA_P18_CC
4
I
BANK 0
124
3
Date:
File:
A4
Size
Title
4
Sheet 6 of
Drawn By:
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
29/03/2011
C:\Users\..\spartan6_bank0.SchDoc
RHINO
Number
Project
Spartan-6 Bank 0
-
2
Note:
1.) FMC1_LA_0, FMC1_LA_1 and FMC1_LA_17 can all be used as mezzanine-to-carrier clocks
2.) Place the 127R and 84R5 termination resistors, on the SYS_CLK lines, as close to the Spartan-6 clock input pins as possible
3.) The SYS_CLK pins must be configured as LVPECL_33 inputs
XC6SLX150T-4FGG676C
U35A
COU35A
-
1
of
3
a
PIU350H7 PIU350G7 PIU350H8 PIU350G8 PIU350F7 PIU350F6 PIU350C PIU350B PIU350G6 PIU350F PIU350E6 PIU350E PIU350H9 PIU350G9 PIU350A3 PIU350A2 PIU350F9 PIU350E8 PIU350D PIU350C PIU350H1 PIU350G1 PIU350B4 PIU350A4 PIU350F1 PIU350E1 PIU350B PIU350A PIU350G12 PIU350F1 PIU350F12 PIU350E12 PIU350J1 PIU350G1 PIU350H12 PIU350G1 PIU350E1 PIU350D13 PIU350C13 PIU3p
50A1 PIU350B12 PIU3e
50A12 PIU350B14 PIU350A14 PIU350K12 PIU350J12 PIU350J1 PIU350H13 PIU350F14 PIU350E14 PIU350K14 PIU350H14 PIU350J1 PIU350H1 PIU350J16 PIU350J17 PIU350F16 PIU350E16 PIU350G1 PIU350F1 PIU350F18 PIU350E18 PIU350G16 PIU350F17 PIU350F2 PIU350E2 PIU350H17 PIU350G17 PIU350C21 PIU350B21 PIU350H18 PIU350H19 PIU350B2 PIU350A2 PIU350G19 PIU350F19 PIU350B2 PIU350A2 PIU350D21 PIU350D2
To
w
n
SYS_CLK_P
SYS_CLK_N
FPGA_SYS_CLK
R187
127R
PIR18702COR187 PIR18 02COR188
VCC_3V3_FPGA
2
65
Simon Scott
Revision
1.0
POFMC10ZDKN32 POFMC10ZDK32
A
B
C
D
I
D
POFMC10LA0P18
POFMC10LA0P17
POFMC10LA0P16
POFMC10LA0P15
POFMC10LA0P14
POFMC10LA0P13
POFMC10LA0P12
POFMC10LA0P11
POFMC10LA0P10
POFMC10LA0P9
POFMC10LA0P8
POFMC10LA0P7
POFMC10LA0P6
POFMC10LA0P5
POFMC10LA0P4
POFMC10LA0P3
POFMC10LA0P2
POFMC10LA0P1
POFMC10LA0P0
POFMC10LA0P0330000
POFMC10LA0P33
POFMC10LA0P32
POFMC10LA0P31
POFMC10LA0P30
POFMC10LA0P29
POFMC10LA0P28
POFMC10LA0P27
POFMC10LA0P26
POFMC10LA0P25
POFMC10LA0P24
POFMC10LA0P23
POFMC10LA0P22
POFMC10LA0P21
POFMC10LA0P20
POFMC10LA0P19
FMC1_LA_P[33..0]
POFMC10LA0N18
POFMC10LA0N17
POFMC10LA0N16
POFMC10LA0N15
POFMC10LA0N14
POFMC10LA0N13
POFMC10LA0N12
POFMC10LA0N11
POFMC10LA0N10
POFMC10LA0N9
POFMC10LA0N8
POFMC10LA0N7
POFMC10LA0N6
POFMC10LA0N5
POFMC10LA0N4
POFMC10LA0N3
POFMC10LA0N2
POFMC10LA0N1
POFMC10LA0N0
POFMC10LA0N0330000
POFMC10LA0N33
POFMC10LA0N32
POFMC10LA0N31
POFMC10LA0N30
POFMC10LA0N29
POFMC10LA0N28
POFMC10LA0N27
POFMC10LA0N26
POFMC10LA0N25
POFMC10LA0N24
POFMC10LA0N23
POFMC10LA0N22
POFMC10LA0N21
POFMC10LA0N20
POFMC10LA0N19
FMC1_LA_N[33..0]
POSYS0CLK0SYS0CLK0P
POSYS0CLK0SYS0CLK0N
POSYS0CLK
SYS_CLK
1
FMC1_ZDOK_N[3..0]
FMC1_ZDOK_N[3..0]
A
I
ct::
H7
G7
H8
G8
F7
F6
C3
B3
G6
F5
E6
E5
H9
G9
A3
A2
F9
E8
D5
C5
H10
G10
B4
A4
F10
E10
B5
A5
G12
F11
F12
E12
J11
G11
H12
G13
E13
D13
C13
A13
B12
A12
B14
A14
K12
J12
J13
H13
F14
E14
K14
H14
J15
H15
J16
J17
F16
E16
G15
F15
F18
E18
G16
F17
F20
E20
H17
G17
C21
B21
H18
H19
B22
A22
G19
F19
B23
A23
D21
D22
I
FMC1_LA_P2
FMC1_LA_N2
FMC1_LA_P3
FMC1_LA_N3
FMC1_LA_P4
FMC1_LA_N4
FMC1_LA_P5
FMC1_LA_N5
FMC1_LA_P6
FMC1_LA_N6
FMC1_LA_P7
FMC1_LA_N7
FMC1_LA_P8
FMC1_LA_N8
FMC1_LA_P9
FMC1_LA_N9
FMC1_LA_P10
FMC1_LA_N10
FMC1_LA_P11
FMC1_LA_N11
FMC1_LA_P12
FMC1_LA_N12
FMC1_LA_P13
FMC1_LA_N13
FMC1_LA_P14
FMC1_LA_N14
FMC1_LA_P15
FMC1_LA_N15
FMC1_LA_P16
FMC1_LA_N16
FMC1_LA_P18
FMC1_LA_N18
FMC1_LA_P19
FMC1_LA_N19
FMC1_LA_P0
FMC1_LA_N0
FMC1_LA_P1
FMC1_LA_N1
FMC1_LA_P17
FMC1_LA_N17
SYS_CLK_P
SYS_CLK_N
FMC1_LA_P20
FMC1_LA_N20
FMC1_LA_P21
FMC1_LA_N21
FMC1_LA_P22
FMC1_LA_N22
FMC1_LA_P23
FMC1_LA_N23
FMC1_LA_P24
FMC1_LA_N24
FMC1_LA_P25
FMC1_LA_N25
FMC1_LA_P26
FMC1_LA_N26
FMC1_LA_P27
FMC1_LA_N27
FMC1_LA_P28
FMC1_LA_N28
FMC1_LA_P29
FMC1_LA_N29
FMC1_LA_P30
FMC1_LA_N30
FMC1_LA_P31
FMC1_LA_N31
FMC1_LA_P32
FMC1_LA_N32
FMC1_LA_P33
FMC1_LA_N33
FMC1_ZDOK_P0
FMC1_ZDOK_N0
FMC1_ZDOK_P1
FMC1_ZDOK_N1
FMC1_ZDOK_P2
FMC1_ZDOK_N2
FMC1_ZDOK_P3
FMC1_ZDOK_N3
..... ,.--J
HI"
I
IO_L1P_HSWAPEN_0
IO_L1N_VREF_0
IO_L2P_0
IO_L2N_0
IO_L3P_0
IO_L3N_0
IO_L4P_0
IO_L4N_0
IO_L5P_0
IO_L5N_0
IO_L8P_0
IO_L8N_VREF_0
IO_L13P_0
IO_L13N_0
IO_L14P_0
IO_L14N_0
IO_L15P_0
IO_L15N_0
IO_L16P_0
IO_L16N_0
IO_L21P_0
IO_L21N_0
IO_L22P_0
IO_L22N_0
IO_L23P_0
IO_L23N_0
IO_L24P_0
IO_L24N_0
IO_L30P_0
IO_L30N_0
IO_L31P_0
IO_L31N_0
IO_L32P_0
IO_L32N_0
IO_L33P_0
IO_L33N_0
IO_L34P_GCLK19_0
IO_L34N_GCLK18_0
IO_L35P_GCLK17_0
IO_L35N_GCLK16_0
IO_L36P_GCLK15_0
IO_L36N_GCLK14_0
IO_L37P_GCLK13_0
IO_L37N_GCLK12_0
IO_L38P_0
IO_L38N_VREF_0
IO_L39P_0
IO_L39N_0
IO_L40P_0
IO_L40N_0
IO_L41P_0
IO_L41N_0
IO_L43P_0
IO_L43N_0
IO_L48P_0
IO_L48N_0
IO_L49P_0
IO_L49N_0
IO_L50P_0
IO_L50N_0
IO_L51P_0
IO_L51N_0
IO_L56P_0
IO_L56N_0
IO_L57P_0
IO_L57N_0
IO_L58P_0
IO_L58N_0
IO_L59P_0
IO_L59N_0
IO_L62P_0
IO_L62N_VREF_0
IO_L63P_SCP7_0
IO_L63N_SCP6_0
IO_L64P_SCP5_0
IO_L64N_SCP4_0
IO_L65P_SCP3_0
IO_L65N_SCP2_0
IO_L66P_SCP1_0
IO_L66N_SCP0_0
FMC1_ZDOK_P[3..0]
FMC1_ZDOK_P[3..0]
f-
I
r-
f-
f-
1
FMC0_CLK1_M2C
FMC0_CLK0_M2C
PIR19701 PIR19801
R197
4k7
PO15880GPIO030000
PO15880GPIO3
PO15880GPIO2
PO15880GPIO1
PO15880GPIO0
1588_GPIO[3..0]
FMC_0_PRSNT
FMC_1_PRSNT
R198
4k7
PIR19702 COR197 PIR19802COR198
VCC_3V3_FPGA
1588_GPIO[3..0]
e
ap
C
CS2_DMAREQ0
CS3
CS4_DMAREQ1
CS5_DMAREQ2
CS6_IODIR
WE
OE
ADV_ALE
WP
BUSY0
BUSY1
CS1
CLK
CS0
of
To
1n
125
2
3
w
n
Date:
File:
A4
Size
Title
1588_CLK
SDA
SCL
SDA
SCL
4
Sheet 7 of
Drawn By:
1.0
65
Simon Scott
Revision
POFPGA0AWAKE
FPGA_AWAKE
1588_CLK
PO15880CLK
FMC_0_CTRL
POFMC000CTRL0PG0C2M
POFMC000CTRL0P\R\S\N\T\0\M\2\C\
POFMC000CTRL0I2C0SDA
POFMC000CTRL0I2C0SCL
POFMC000CTRL0I2C
POFMC000CTRL0GA1
POFMC000CTRL0GA0
POFMC000CTRL
POFMC010CTRL0PG0C2M
POFMC010CTRL0P\R\S\N\T\0\M\2\C\
POFMC010CTRL0I2C0SDA
POFMC010CTRL0I2C0SCL
POFMC010CTRL0I2C
POFMC010CTRL0GA1
POFMC010CTRL0GA0
POFMC010CTRL
FMC_1_CTRL
POFP0I2C0FPGA0SDA
POFP0I2C0FPGA0SCL
POFP0I2C0FPGA
FP_I2C_FPGA
POFPGA0PROC0BUS0W\P\
POFPGA0PROC0BUS0W\E\
POFPGA0PROC0BUS0O\E\
POFPGA0PROC0BUS0D0150000
POFPGA0PROC0BUS0D15
POFPGA0PROC0BUS0D14
POFPGA0PROC0BUS0D13
POFPGA0PROC0BUS0D12
POFPGA0PROC0BUS0D11
POFPGA0PROC0BUS0D10
POFPGA0PROC0BUS0D9
POFPGA0PROC0BUS0D8
POFPGA0PROC0BUS0D7
POFPGA0PROC0BUS0D6
POFPGA0PROC0BUS0D5
POFPGA0PROC0BUS0D4
POFPGA0PROC0BUS0D3
POFPGA0PROC0BUS0D2
POFPGA0PROC0BUS0D1
POFPGA0PROC0BUS0D0
POFPGA0PROC0BUS0CLK
POFPGA0PROC0BUS0C\S\6\0IODIR
POFPGA0PROC0BUS0C\S\5\0D\M\A\R\E\Q\2\
POFPGA0PROC0BUS0C\S\4\0D\M\A\R\E\Q\1\
POFPGA0PROC0BUS0C\S\3\
POFPGA0PROC0BUS0C\S\2\0D\M\A\R\E\Q\0\
POFPGA0PROC0BUS0C\S\1\
POFPGA0PROC0BUS0C\S\0\
POFPGA0PROC0BUS0BUSY1
POFPGA0PROC0BUS0BUSY0
POFPGA0PROC0BUS0A\D\V\0ALE
POFPGA0PROC0BUS0A0100010
POFPGA0PROC0BUS0A10
POFPGA0PROC0BUS0A9
POFPGA0PROC0BUS0A8
POFPGA0PROC0BUS0A7
POFPGA0PROC0BUS0A6
POFPGA0PROC0BUS0A5
POFPGA0PROC0BUS0A4
POFPGA0PROC0BUS0A3
POFPGA0PROC0BUS0A2
POFPGA0PROC0BUS0A1
POFPGA0PROC0BUS
FPGA_PROC_BUS
POFMC00CLK10M2C0P
FMC0_CLK1_M2C_P
POFMC00CLK10M2C0N
FMC0_CLK1_M2C_N
POFMC00CLK00M2C0P
FMC0_CLK0_M2C_P
POFMC00CLK00M2C0N
FMC0_CLK0_M2C_N
4
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
GA0
GA1
PRSNT_M2C
PG_C2M
I2C
FMC_CTRL
GA0
GA1
PRSNT_M2C
PG_C2M
I2C
29/03/2011
C:\Users\..\spartan6_bank1.SchDoc
RHINO
Number
Project
SDA
SCL
FMC_CTRL
Spartan-6 Bank 1
FMC_0_GA0
FMC_0_GA1
FMC_0_PRSNT
FMC_I2C_SDA
FMC_I2C_SCL
FMC_1_GA0
FMC_1_GA1
FMC_1_PRSNT
FMC_I2C_SDA
FMC_I2C_SCL
R196
2k2
PIR19501 PIR19601
R195
2k2
PIR19502 COR195 PIR19602COR196
I2C
B_IN+
B_IN-
A_IN+
A_IN-
VCC_3V3_FPGA
B_OUT
A_OUT
dual_lvds_receiver0
FP_I2C_SDA
FP_I2C_SCL
FMC0_CLK1_M2C
FMC0_CLK0_M2C
-
Layout Notes:
1.) Place the MAX9111 LVDS receiver IC as close to the Spartan-6 as possible,
to minimise noise on the clock lines
1588_GPIO0
1588_GPIO1
1588_GPIO2
1588_GPIO3
FMC_I2C_SDA
FMC_I2C_SCL
FMC_0_GA0
FMC_0_GA1
FMC_1_GA0
FMC_1_GA1
FP_I2C_SDA
FP_I2C_SCL
ty
D[15..0]
A[10..1]
I I IIIIII I II
PIU350AC24
D[15..0]
er
si
ni
v
U
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
1588_CLK
D15
r__------------------~A~----------------------___\
x
XC6SLX150T-4FGG676C
N17
N18
PIU350N18
L23
PIU350L23
L24
PIU350L24
N19
PIU350N19
N20
PIU350N20
N21
PIU350N21
N22
PIU350N22
P17
PIU350P17
P19
PIU350P19
N23
PIU350N23
N24
PIU350N24
R18
PIU350R18
R19
PIU350R19
P21
PIU350P21
P22
PIU350P22
R20
PIU350R20
R21
PIU350R21
P24
PIU350P24
P26
PIU350P26
R23
PIU350R23
R24
PIU350R24
T22
PIU350T22
T23
PIU350T23
U23
PIU350U23
U24
PIU350U24
R25
PIU350R25
R26
PIU350R26
V23
PIU350V23
W24
PIU350W24
U25
PIU350U25
U26
PIU350U26
T24
PIU350T24
T26
PIU350T26
V24
PIU350V24
V26
PIU350V26
W25
PIU350W25
W26
PIU350W26
AA25
PIU350AA25
AA26
PIU350AA26
AD24
PIU350AD24
AD26
PIU350AD26
AB24
PIU350AB24
AB26
PIU350AB26
AC25
PIU350AC25
AC26
PIU350AC26
Y24
PIU350Y24
Y26
PIU350Y26
AE25
PIU350AE25
AE26
PIU350AE26
U21
PIU350U21
U22
PIU350U22
T19
PIU350T19
T20
PIU350T20
AA23
PIU350AA23
AA24
PIU350AA24
U19
PIU350U19
U20
PIU350U20
V20
PIU350V20
V21
PIU350V21
AC23
PIU350AC23
AC24
PIU350N17
FPGA_PROC_BUS
0
x
D
IO_L28P_1
IO_L28N_VREF_1
IO_L29P_A23_M1A13_1
IO_L29N_A22_M1A14_1
IO_L30P_A21_M1RESET_1
IO_L30N_A20_M1A11_1
IO_L31P_A19_M1CKE_1
IO_L31N_A18_M1A12_1
IO_L32P_A17_M1A8_1
IO_L32N_A16_M1A9_1
IO_L33P_A15_M1A10_1
IO_L33N_A14_M1A4_1
IO_L34P_A13_M1WE_1
IO_L34N_A12_M1BA2_1
IO_L35P_A11_M1A7_1
IO_L35N_A10_M1A2_1
IO_L36P_A9_M1BA0_1
IO_L36N_A8_M1BA1_1
IO_L37P_A7_M1A0_1
IO_L37N_A6_M1A1_1
IO_L38P_A5_M1CLK_1
IO_L38N_A4_M1CLKN_1
IO_L39P_M1A3_1
IO_L39N_M1ODT_1
IO_L40P_GCLK11_M1A5_1
IO_L40N_GCLK10_M1A6_1
IO_L41P_GCLK9_IRDY1_M1RASN_1
IO_L41N_GCLK8_M1CASN_1
IO_L42P_GCLK7_M1UDM_1
IO_L42N_GCLK6_TRDY1_M1LDM_1
IO_L43P_GCLK5_M1DQ4_1
IO_L43N_GCLK4_M1DQ5_1
IO_L44P_A3_M1DQ6_1
IO_L44N_A2_M1DQ7_1
IO_L45P_A1_M1LDQS_1
IO_L45N_A0_M1LDQSN_1
IO_L46P_FCS_B_M1DQ2_1
IO_L46N_FOE_B_M1DQ3_1
IO_L47P_FWE_B_M1DQ0_1
IO_L47N_LDC_M1DQ1_1
IO_L48P_HDC_M1DQ8_1
IO_L48N_M1DQ9_1
IO_L49P_M1DQ10_1
IO_L49N_M1DQ11_1
IO_L50P_M1UDQS_1
IO_L50N_M1UDQSN_1
IO_L51P_M1DQ12_1
IO_L51N_M1DQ13_1
IO_L52P_M1DQ14_1
IO_L52N_M1DQ15_1
IO_L53P_1
IO_L53N_VREF_1
IO_L66P_1
IO_L66N_1
IO_L67P_1
IO_L67N_1
IO_L68P_1
IO_L68N_1
IO_L69P_1
IO_L69N_VREF_1
IO_L74P_AWAKE_1
IO_L74N_DOUT_BUSY_1
A[10..1]
3
·UU UU
C
BANK 1
COU35B
U35B
2
o
B
A
1
-,--,----
-f-
-
...-.
-
-
D
C
B
A
B
I
2
ap
C
GND
3
1
PIU7403
NC
1
PIU7401 IN2
PIU7402 IN+
1n
PIC54402 PIC54401
PIU7408
PIU7405
----11
1'
I
GND
GND
e
4
6
PIU7406
OUT
NC
NC
PIU7404
7
PIU7407
3
w
n
22R
PIR45001
PIR45002
R450
COR4
To
COU2
U74
MAX9111ESA
100n
PIC54502 PIC54501
22R
PIR44802
COR2
R448
PIR44801
126
4
Sheet 8 of
Drawn By:
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
29/03/2011
C:\Users\..\dual_lvds_receiver.SchDoc
RHINO
Number
Project
Dual LVDS Receiver
-
Date:
File:
A4
Size
Title
POB0OUT0dual0lvds0receiver0
B_OUT
POA0OUT0dual0lvds0receiver0
A_OUT
4
-
1
Layout Notes:
1.) Place the 100R and 22R termination resistors as close to the pins of the
MAX9111ESA IC as possible
2.) Place the 100nF and 1nF decoupling caps as close to the IC as possible
PIU7305
7
PIU7307
4
NC PIU7304
6
NC PIU7306
OUT
GND
COU1
U73
MAX9111ESA
VCC_3V3_FPGA
COC3
COC4
C544
C545
ty
PIU7308
PIC54301
100n
PIC54302
3
1.0
65
Simon Scott
Revision
B
A
C
D
I
D
100R
GND
-
PIR44902
COR3
R449
3
~II'
-
PIR44901
NC
PIU7303
PIU7302
of
ININ+
1
2
PIU7301
er
si
PIR44702
==
B_IN-
POB0IN00dual0lvds0receiver0
B_IN+
ni
v
100R
PIR44701
GND
,
C
A_IN-
U
POA0IN00dual0lvds0receiver0
A_IN+
~
8
COR1
R447
PIC54201
1n
PIC54202
8
VCC_3V3_FPGA
COC1
COC2
C542
C543
1
1'
==
VCC
r-
----11
til'
GND
2
~II'
VCC
==
ff
5
A
1
.,
GND
==
5
til'
I
r-
ff
c-
c-
A
I
B
I
POFMC00LA0P0330000
POFMC00LA0P33
POFMC00LA0P32
POFMC00LA0P31
POFMC00LA0P30
POFMC00LA0P29
POFMC00LA0P28
POFMC00LA0P27
POFMC00LA0P26
POFMC00LA0P25
POFMC00LA0P24
POFMC00LA0P23
POFMC00LA0P22
POFMC00LA0P21
POFMC00LA0P20
POFMC00LA0P19
POFMC00LA0P18
POFMC00LA0P17
POFMC00LA0P16
POFMC00LA0P15
POFMC00LA0P14
POFMC00LA0P13
POFMC00LA0P12
POFMC00LA0P11
POFMC00LA0P10
POFMC00LA0P9
POFMC00LA0P8
POFMC00LA0P7
POFMC00LA0P6
POFMC00LA0P5
POFMC00LA0P4
POFMC00LA0P3
POFMC00LA0P2
POFMC00LA0P1
POFMC00LA0P0
FMC0_LA_P[33..0]
POFMC00LA0N0330000
POFMC00LA0N33
POFMC00LA0N32
POFMC00LA0N31
POFMC00LA0N30
POFMC00LA0N29
POFMC00LA0N28
POFMC00LA0N27
POFMC00LA0N26
POFMC00LA0N25
POFMC00LA0N24
POFMC00LA0N23
POFMC00LA0N22
POFMC00LA0N21
POFMC00LA0N20
POFMC00LA0N19
POFMC00LA0N18
POFMC00LA0N17
POFMC00LA0N16
POFMC00LA0N15
POFMC00LA0N14
POFMC00LA0N13
POFMC00LA0N12
POFMC00LA0N11
POFMC00LA0N10
POFMC00LA0N9
POFMC00LA0N8
POFMC00LA0N7
POFMC00LA0N6
POFMC00LA0N5
POFMC00LA0N4
POFMC00LA0N3
POFMC00LA0N2
POFMC00LA0N1
POFMC00LA0N0
FMC0_LA_N[33..0]
GND
50_OHM i
I
CONF_CCLK
ty
er
si
ni
v
U
of
C
e
To
BANK 2
XC6SLX150T-4FGG676C
3
Date:
File:
A4
Size
Title
Sheet 9 of
Drawn By:
4
CONF_INIT_B
1.0
65
Simon Scott
Revision
PIR203 2 POCONF0INIT0B
R203
2k2
PIR203 1COR203
VCC_2V5_FPGA
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
29/03/2011
C:\Users\..\spartan6_bank2.SchDoc
RHINO
Number
Project
Spartan-6 Bank 2
-
2
General Note:
1.) FMC0_LA_0, 1, 17 and 18 can all be used as mezzanine-to-carrier clocks
w
n
POFMC0ZDK32 POFMC0ZDKN32
-
1
PIR201
R201
2k2
PIR2012 COR201
4
PIU350AE24 PIU350AF24 PIU350Y21 PIU350A2 PIU350AD2 PIU350AF23 PIU350W2 PIU350Y2 PIU350AB2 PIU350AC2 PIU350V18 PIU350W19 PIU350AD2 PIU350AF2 PIU350W17 PIU350W18 PIU350A21 PIU350AB21 PIU350Y17 PIU350A17 PIU3501 PIU350V16 PIU350A19 PIU350AB19 PIU350W16 PIU350Y16 PIU350A18 PIU350AB17 PIU350Y1 PIU350A16 PIU350V14 PIU350V1 PIU3501 PIU350V13 PIU350A1 PIU350AB1 PIU350AE1 PIU350AF1 PIU350a
AB14 PIU350AC14 PIU3p
50AE1 PIU350AF1 PIU350AD14 PIU350AF14 PIU350Y12 PIU350A12 PIU350W14 PIU350Y1 PIU350V12 PIU350W12 PIU350AB1 PIU350A1 PIU350Y1 PIU350A1 PIU350V1 PIU350V1 PIU350A9 PIU350AB9 PIU350A1 PIU350AB1 PIU350AD6 PIU350AF6 PIU350W1 PIU350W9 PIU350AE PIU350AF PIU350Y9 PIU350A8 PIU350AB7 PIU350AC6 PIU350AC PIU350AD PIU350W8 PIU350W7 PIU350AD4 PIU350AF4 PIU350A7 PIU350A6 PIU350AE PIU350AF
Layout Note:
1.) Route the CONF_CCLK line as a 50 Ohm controlled impedance
transmission line
2.) Place the two 100 ohm resistors on the CONF_CCLK line as close to the
FPGA pin as possible
127
U35C
COU35C
FMC0_LA_P[33..0]
FMC0_LA_N[33..0]
~
A
B
C
D
I
D
PIR20 1
CONF_DIN
POCNF0LK POCNF0DI
PIR20 1
R200
2k2
PIR20 2COR200
3
I
C
R202
100R
PIR20 2COR202
PIR19 01
R199
100R
PIR19 02COR199
FMC0_LA_P3
FMC0_LA_N3
FMC0_LA_P4
FMC0_LA_N4
FMC0_LA_P5
FMC0_LA_N5
VCC_2V5_FPGA
2
FMC_0_ZDOK_P[3..2]
FMC_0_ZDOK_P[3..2]
1
FMC0_LA_P2
FMC0_LA_N2
FMC_0_ZDOK_N[3..2]
FMC_0_ZDOK_N[3..2]
VCC_2V5_FPGA
I'
~
AE24
AF24
Y21
AA22
AD23
AF23
W20
Y20
AB22
AC22
V18
W19
AD22
AF22
W17
W18
AA21
AB21
Y17
AA17
U15
V16
AA19
AB19
W16
Y16
AA18
AB17
Y15
AA16
V14
V15
U13
V13
AA15
AB15
AE15
AF15
AB14
AC14
AE13
AF13
AD14
AF14
Y12
AA12
W14
Y13
V12
W12
AB13
AA13
Y11
AA11
V11
V10
AA9
AB9
AA10
AB11
AD6
AF6
W10
W9
AE5
AF5
Y9
AA8
AB7
AC6
AC5
AD5
W8
W7
AD4
AF4
AA7
AA6
AE3
AF3
III'
FMC0_LA_P6
FMC0_LA_N6
FMC0_LA_P7
FMC0_LA_N7
FMC0_LA_P8
FMC0_LA_N8
FMC0_LA_P9
FMC0_LA_N9
FMC0_LA_P10
FMC0_LA_N10
FMC0_LA_P11
FMC0_LA_N11
FMC0_LA_P12
FMC0_LA_N12
FMC0_LA_P13
FMC0_LA_N13
FMC0_LA_P14
FMC0_LA_N14
FMC0_LA_P15
FMC0_LA_N15
FMC0_LA_P16
FMC0_LA_N16
FMC0_LA_P0
FMC0_LA_N0
FMC0_LA_P1
FMC0_LA_N1
FMC0_LA_P17
FMC0_LA_N17
FMC0_LA_P18
FMC0_LA_N18
FMC0_LA_P19
FMC0_LA_N19
FMC0_LA_P20
FMC0_LA_N20
FMC0_LA_P21
FMC0_LA_N21
FMC0_LA_P22
FMC0_LA_N22
FMC0_LA_P23
FMC0_LA_N23
FMC0_LA_P24
FMC0_LA_N24
FMC0_LA_P25
FMC0_LA_N25
FMC0_LA_P26
FMC0_LA_N26
FMC0_LA_P27
FMC0_LA_N27
FMC0_LA_P28
FMC0_LA_N28
FMC0_LA_P29
FMC0_LA_N29
FMC0_LA_P30
FMC0_LA_N30
FMC0_LA_P31
FMC0_LA_N31
FMC0_LA_P32
FMC0_LA_N32
FMC0_LA_P33
FMC0_LA_N33
FMC_0_ZDOK_P3
FMC_0_ZDOK_N3
FMC_0_ZDOK_P2
FMC_0_ZDOK_N2
6
~
IO_L1P_CCLK_2
IO_L1N_M0_CMPMISO_2
IO_L2P_CMPCLK_2
IO_L2N_CMPMOSI_2
IO_L3P_D0_DIN_MISO_MISO1_2
IO_L3N_MOSI_CSI_B_MISO0_2
IO_L4P_2
IO_L4N_VREF_2
IO_L5P_2
IO_L5N_2
IO_L12P_D1_MISO2_2
IO_L12N_D2_MISO3_2
IO_L13P_M1_2
IO_L13N_D10_2
IO_L14P_D11_2
IO_L14N_D12_2
IO_L15P_2
IO_L15N_2
IO_L16P_2
IO_L16N_VREF_2
IO_L17P_2
IO_L17N_2
IO_L18P_2
IO_L18N_2
IO_L19P_2
IO_L19N_2
IO_L20P_2
IO_L20N_2
IO_L24P_2
IO_L24N_VREF_2
IO_L26P_2
IO_L26N_2
IO_L27P_2
IO_L27N_2
IO_L28P_2
IO_L28N_2
IO_L29P_GCLK3_2
IO_L29N_GCLK2_2
IO_L30P_GCLK1_D13_2
IO_L30N_GCLK0_USERCCLK_2
IO_L31P_GCLK31_D14_2
IO_L31N_GCLK30_D15_2
IO_L32P_GCLK29_2
IO_L32N_GCLK28_2
IO_L33P_2
IO_L33N_2
IO_L34P_2
IO_L34N_2
IO_L35P_2
IO_L35N_2
IO_L36P_2
IO_L36N_2
IO_L41P_2
IO_L41N_VREF_2
IO_L46P_2
IO_L46N_2
IO_L47P_2
IO_L47N_2
IO_L48P_D7_2
IO_L48N_RDWR_B_VREF_2
IO_L49P_D3_2
IO_L49N_D4_2
IO_L50P_2
IO_L50N_2
IO_L51P_2
IO_L51N_2
IO_L52P_2
IO_L52N_2
IO_L53P_2
IO_L53N_2
IO_L61P_2
IO_L61N_VREF_2
IO_L62P_D5_2
IO_L62N_D6_2
IO_L63P_2
IO_L63N_2
IO_L64P_D8_2
IO_L64N_D9_2
IO_L65P_INIT_B_2
IO_L65N_CSO_B_2
I
r-
f-
f-
1
PIU350M9
rrrr
128
XC6SLX150T-4FGG676C
PIU350AA3
AA3
Y6
PIU350Y6
Y5
PIU350Y5
AB4
PIU350AB4
AC3
PIU350AC3
V7
PIU350V7
V6
PIU350V6
U4
PIU350U4
U3
PIU350U3
V5
PIU350V5
W5
PIU350W5
U9
PIU350U9
U8
PIU350U8
U7
PIU350U7
T6
PIU350T6
AB3
PIU350AB3
AB1
PIU350AB1
AD3
PIU350AD3
AD1
PIU350AD1
AC2
PIU350AC2
AC1
PIU350AC1
AE2
PIU350AE2
AE1
PIU350AE1
AA2
PIU350AA2
AA1
PIU350AA1
Y3
PIU350Y3
Y1
PIU350Y1
W2
PIU350W2
W1
PIU350W1
V3
PIU350V3
V1
PIU350V1
U2
PIU350U2
U1
PIU350U1
T3
PIU350T3
T1
PIU350T1
V4
PIU350V4
W3
PIU350W3
R7
PIU350R7
R6
PIU350R6
R2
PIU350R2
R1
PIU350R1
R8
PIU350R8
T8
PIU350T8
U5
PIU350U5
T4
PIU350T4
R10
PIU350R10
T9
PIU350T9
P3
PIU350P3
P1
PIU350P1
N6
PIU350N6
P6
PIU350P6
P5
PIU350P5
R5
PIU350R5
N8
PIU350N8
N7
PIU350N7
R4
PIU350R4
R3
PIU350R3
R9
PIU350R9
P8
PIU350P8
N5
PIU350N5
N4
PIU350N4
P10
PIU350P10
N9
PIU350N9
M10
PIU350M10
M9
AA4
PIU350AA4
AC4
PIU350AC4
AB5
PIU350AB5
33R
PIR20402
R215
COR215
PIR21501
2
100R
PIR21502
FMC1_CLK1_M2C
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
FMC1_CLK0_M2C
GMII_RX_CLK
R216
COR216
PIR21601
ty
GMII_TX_CLK
GMII_RX_CLK
PIR20702
33R
33R
PIR20802
33R
PIR20902
33R
PIR21002
33R
PIR21102
33R
PIR21202
33R
PIR21302
33R
PIR21402
33R
PIR20602
33R
PIR20502
er
si
GMII_TX_CLK
MDC
MDIO
INT
RESET
COMA
USER_LED0
USER_LED1
USER_LED2
USER_LED3
USER_LED4
USER_LED5
USER_LED6
USER_LED7
ni
v
U
COR204
R204
PIR20401
COR205
R205
PIR20501
COR206
R206
PIR20601
COR207
R207
PIR20701
COR208
R208
PIR20801
COR209
R209
PIR20901
COR210
R210
PIR21001
COR211
R211
PIR21101
COR212
R212
PIR21201
COR213
R213
PIR21301
COR214
R214
PIR21401
»»»»>~
D
IO_L1P_3
IO_L1N_VREF_3
IO_L2P_3
IO_L2N_3
IO_L7P_3
IO_L7N_3
IO_L8P_3
IO_L8N_3
IO_L9P_3
IO_L9N_3
IO_L10P_3
IO_L10N_3
IO_L17P_3
IO_L17N_VREF_3
IO_L18P_3
IO_L18N_3
IO_L31P_3
IO_L31N_VREF_3
IO_L32P_M3DQ14_3
IO_L32N_M3DQ15_3
IO_L33P_M3DQ12_3
IO_L33N_M3DQ13_3
IO_L34P_M3UDQS_3
IO_L34N_M3UDQSN_3
IO_L35P_M3DQ10_3
IO_L35N_M3DQ11_3
IO_L36P_M3DQ8_3
IO_L36N_M3DQ9_3
IO_L37P_M3DQ0_3
IO_L37N_M3DQ1_3
IO_L38P_M3DQ2_3
IO_L38N_M3DQ3_3
IO_L39P_M3LDQS_3
IO_L39N_M3LDQSN_3
IO_L40P_M3DQ6_3
IO_L40N_M3DQ7_3
IO_L41P_GCLK27_M3DQ4_3
IO_L41N_GCLK26_M3DQ5_3
IO_L42P_GCLK25_TRDY2_M3UDM_3
IO_L42N_GCLK24_M3LDM_3
IO_L43P_GCLK23_M3RASN_3
IO_L43N_GCLK22_IRDY2_M3CASN_3
IO_L44P_GCLK21_M3A5_3
IO_L44N_GCLK20_M3A6_3
IO_L45P_M3A3_3
IO_L45N_M3ODT_3
IO_L46P_M3CLK_3
IO_L46N_M3CLKN_3
IO_L47P_M3A0_3
IO_L47N_M3A1_3
IO_L48P_M3BA0_3
IO_L48N_M3BA1_3
IO_L49P_M3A7_3
IO_L49N_M3A2_3
IO_L50P_M3WE_3
IO_L50N_M3BA2_3
IO_L51P_M3A10_3
IO_L51N_M3A4_3
IO_L52P_M3A8_3
IO_L52N_M3A9_3
IO_L53P_M3CKE_3
IO_L53N_M3A12_3
IO_L54P_M3RESET_3
IO_L54N_M3A11_3
IO_L55P_M3A13_3
IO_L55N_M3A14_3
IO_L57P_3
IO_L57N_VREF_3
2
~
100R
PIR21602
of
MDC
MDIO
INT
RESET
COMA
To
B_OUT
3
Date:
File:
A4
Size
Title
PIR19301
29/03/2011
C:\Users\..\spartan6_bank3.SchDoc
RHINO
4
Sheet 10 of
Drawn By:
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
FMC_0_ZDOK_N[1..0]
POFMC000ZDOK0N010000
POFMC000ZDOK0N1
POFMC000ZDOK0N0
Number
Project
0R
PIR19102 POFMC10CLK10M2C0P
FMC1_CLK1_M2C_P
0R
PIR19202 POFMC10CLK10M2C0N
FMC1_CLK1_M2C_N
POFMC10CLK00M2C0N
FMC1_CLK0_M2C_N
POFMC10CLK00M2C0P
FMC1_CLK0_M2C_P
1.0
65
Simon Scott
Revision
COR193NOPOP PIR19302
R193
0R
FMC1_LA_P18_CC
POFMC10LA0P180CC
COR194
R194
0R
PIR19401
PIR19402 POFMC10LA0N180CC
FMC1_LA_N18_CC
NOPOP
COR191
R191
PIR19101
COR192
R192
PIR19201
FMC_0_ZDOK_P[1..0]
POFMC000ZDOK0P010000
POFMC000ZDOK0P1
POFMC000ZDOK0P0
B_IN+
B_IN-
A_IN+
A_IN-
POGIGE0CTRL0R\E\S\E\T\
POGIGE0CTRL0MDIO
POGIGE0CTRL0MDC
POGIGE0CTRL0I\N\T\
POGIGE0CTRL0COMA
POGIGE0CTRL
GIGE_CTRL
Spartan-6 Bank 3
FMC_0_ZDOK_N[1..0]
FMC_0_ZDOK_P[1..0]
w
n
GPIO[15..0] POGPIO9
POGPIO15
POGPIO8
POGPIO7
POGPIO14
POGPIO6
POGPIO5
POGPIO13
POGPIO4
POGPIO3
POGPIO12
POGPIO2
POGPIO1
POGPIO11
POGPIO0
POGPIO10
POGPIO0150000
GPIO[15..0]
A_OUT
dual_lvds_receiver1
POUSER0LED070000
POUSER0LED7
POUSER0LED6
POUSER0LED5
POUSER0LED4
POUSER0LED3
POUSER0LED2
POUSER0LED1
POUSER0LED0
USER_LED[7..0]
MDC
MDIO
INT
RESET
COMA
GIGE_CTRL
POGIGE0GMII0TXD7
POGIGE0GMII0TXD6
POGIGE0GMII0TXD5
POGIGE0GMII0TXD4
POGIGE0GMII0TXD3
POGIGE0GMII0TXD2
POGIGE0GMII0TXD1
POGIGE0GMII0TXD0
POGIGE0GMII0TX0ER
POGIGE0GMII0TX0EN
POGIGE0GMII0TX0CLK
POGIGE0GMII0RXD7
POGIGE0GMII0RXD6
POGIGE0GMII0RXD5
POGIGE0GMII0RXD4
POGIGE0GMII0RXD3
POGIGE0GMII0RXD2
POGIGE0GMII0RXD1
POGIGE0GMII0RXD0
POGIGE0GMII0RX0ER
POGIGE0GMII0RX0DV
POGIGE0GMII0RX0CLK
POGIGE0GMII0GTX0CLK
POGIGE0GMII0CRS
POGIGE0GMII0COL
POGIGE0GMII
GIGE_GMII
1.) Place the 100 ohm termination resistors as close to the FPGA pins as possible
2.) Place the 22 ohm termination resistors as close to the FPGA pins as possible
3.) Place the MAX9111 LVDS receiver IC as close to the Spartan-6 as possible, to minimise noise
Layout Notes:
FMC1_CLK1_M2C
FMC_0_ZDOK_P0
FMC_0_ZDOK_N0
FMC_0_ZDOK_P1
FMC_0_ZDOK_N1
e
4
1.) FMC_0_ZDOK lines connect to FPGA pins that are configured as BLVDS I/Os, rather than
LVDS I/Os. Therefore, external termination resistors are required.
General Notes:
3
FMC1_CLK0_M2C
USER_LED[7..0]
ap
C
GTX_CLK
TX_EN
TX_ER
TXD0
TXD1
TXD2
TXD3
TXD4
TXD5
TXD6
TXD7
RX_DV
RX_ER
RXD0
RXD1
RXD2
RXD3
RXD4
RXD5
RXD6
RXD7
CRS
COL
TX_CLK
RX_CLK
GMII
[l
C
BANK 3
COU35D
U35D
«««««
B
A
1
r__----------A-----------_,
[l
nn
D
C
B
A
B
I
2
ap
C
GND
3
1
PIU7603
NC
1
PIU7601 IN2
PIU7602 IN+
1n
PIC54802 PIC54801
PIU7608
PIU7605
----11
1'
I
GND
GND
e
4
6
PIU7606
OUT
NC
NC
PIU7604
7
PIU7607
3
w
n
22R
PIR45401
PIR45402
R454
COR4
To
COU2
U76
MAX9111ESA
100n
PIC54902 PIC54901
22R
PIR45202
COR2
R452
PIR45201
129
4
Sheet 11 of
Drawn By:
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
29/03/2011
C:\Users\..\dual_lvds_receiver.SchDoc
RHINO
Number
Project
Dual LVDS Receiver
-
Date:
File:
A4
Size
Title
POB0OUT0dual0lvds0receiver1
B_OUT
POA0OUT0dual0lvds0receiver1
A_OUT
4
-
1
Layout Notes:
1.) Place the 100R and 22R termination resistors as close to the pins of the
MAX9111ESA IC as possible
2.) Place the 100nF and 1nF decoupling caps as close to the IC as possible
PIU750
7
PIU7507
4
NC PIU7504
6
NC PIU7506
OUT
GND
COU1
U75
MAX9111ESA
VCC_3V3_FPGA
COC3
COC4
C548
C549
ty
PIU7508
PIC54701
100n
PIC54702
3
1.0
65
Simon Scott
Revision
B
A
C
D
I
D
100R
GND
-
PIR45302
COR3
R453
3
~II'
-
PIR45301
NC
PIU7503
PIU7502
of
ININ+
1
2
PIU7501
er
si
PIR45102
==
B_IN-
POB0IN00dual0lvds0receiver1
B_IN+
ni
v
100R
PIR45101
GND
,
C
A_IN-
U
POA0IN00dual0lvds0receiver1
A_IN+
~
8
COR1
R451
PIC54601
1n
PIC54602
8
VCC_3V3_FPGA
COC1
COC2
C546
C547
1
1'
==
VCC
r-
----11
til'
GND
2
~II'
VCC
==
ff
5
A
1
.,
GND
==
5
til'
I
r-
ff
c-
c-
A
I
I
I
2
~
130
A[13..0]
RESET
CKE
A[13..0]
RESET
CKE
BA[2..0]
WE
To
ODT
CK_P
CK_N
3
w
n
Date:
File:
A4
Size
Title
4
Sheet 12 of
Drawn By:
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
29/03/2011
C:\Users\..\spartan6_bank4.SchDoc
RHINO
Number
Project
Spartan-6 Bank 4
POMCB40DDR30W\E\
POMCB40DDR30UDQS0P
POMCB40DDR30UDQS0N
POMCB40DDR30UDM
POMCB40DDR30R\E\S\E\T\
POMCB40DDR30R\A\S\
POMCB40DDR30ODT
POMCB40DDR30LDQS0P
POMCB40DDR30LDQS0N
POMCB40DDR30LDM
POMCB40DDR30DQ0150000
POMCB40DDR30DQ15
POMCB40DDR30DQ14
POMCB40DDR30DQ13
POMCB40DDR30DQ12
POMCB40DDR30DQ11
POMCB40DDR30DQ10
POMCB40DDR30DQ9
POMCB40DDR30DQ8
POMCB40DDR30DQ7
POMCB40DDR30DQ6
POMCB40DDR30DQ5
POMCB40DDR30DQ4
POMCB40DDR30DQ3
POMCB40DDR30DQ2
POMCB40DDR30DQ1
POMCB40DDR30DQ0
POMCB40DDR30CKE
POMCB40DDR30CK0P
POMCB40DDR30CK0N
POMCB40DDR30C\A\S\
POMCB40DDR30BA020000
POMCB40DDR30BA2
POMCB40DDR30BA1
POMCB40DDR30BA0
POMCB40DDR30A0130000
POMCB40DDR30A13
POMCB40DDR30A12
POMCB40DDR30A11
POMCB40DDR30A10
POMCB40DDR30A9
POMCB40DDR30A8
POMCB40DDR30A7
POMCB40DDR30A6
POMCB40DDR30A5
POMCB40DDR30A4
POMCB40DDR30A3
POMCB40DDR30A2
POMCB40DDR30A1
POMCB40DDR30A0
POMCB40DDR3
MCB4_DDR3
-
GND
C195
COC195
100n
I- ~ HII'
PIC19502
PIC19501
e
BA[2..0]
WE
ODT
CLK
CLK
ap
C
UDM
LDM
RAS
CAS
LDQS_P
LDQS_N
UDQS_P
UDQS_N
4
-
1
of
LDQS
LDQS
UDQS
UDQS
DQ[15..0]
DDR3_BUS
I
VREF_0V75_DDR3
A5
A6
A3
ODT
CLK
CLK
A0
A1
BA0
BA1
A7
A2
WE
BA2
A10
A4
A8
A9
CKE
A12
RESET
A11
A13
DQ[15..0]
I
Layout Notes:
1.) Ensure that ball H6 (a NO CONNECT pin) is not connected to any trace or plane
ty
DQ14
DQ15
DQ12
DQ13
UDQS
UDQS
DQ10
DQ11
DQ8
DQ9
DQ0
DQ1
DQ2
DQ3
LDQS
LDQS
DQ6
DQ7
DQ4
DQ5
GND
II
1.0
65
Simon Scott
Revision
A
B
C
D
I
D
PIU350H5
PIC19401
100n
PIC19402
3
r
XC6SLX150T-4FGG676C
M4
N3
PIU350N3
N2
PIU350N2
N1
PIU350N1
M3
PIU350M3
M1
PIU350M1
L2
PIU350L2
L1
PIU350L1
K3
PIU350K3
K1
PIU350K1
J2
PIU350J2
J1
PIU350J1
H3
PIU350H3
H1
PIU350H1
G2
PIU350G2
G1
PIU350G1
F3
PIU350F3
F1
PIU350F1
E2
PIU350E2
E1
PIU350E1
D3
PIU350D3
D1
PIU350D1
J4
PIU350J4
J3
PIU350J3
L9
PIU350L9
L8
PIU350L8
L4
PIU350L4
L3
PIU350L3
M8
PIU350M8
M6
PIU350M6
K5
PIU350K5
J5
PIU350J5
L7
PIU350L7
L6
PIU350L6
B2
PIU350B2
B1
PIU350B1
L10
PIU350L10
K10
PIU350K10
G4
PIU350G4
G3
PIU350G3
J9
PIU350J9
J7
PIU350J7
C2
PIU350C2
C1
PIU350C1
K9
PIU350K9
K8
PIU350K8
E4
PIU350E4
E3
PIU350E3
K7
PIU350K7
K6
PIU350K6
H6
PIU350H6
H5
PIU350M4
er
si
ni
v
U
IO_L58P_4
IO_L58N_VREF_4
IO_L59P_M4DQ14_4
IO_L59N_M4DQ15_4
IO_L60P_M4DQ12_4
IO_L60N_M4DQ13_4
IO_L61P_M4UDQS_4
IO_L61N_M4UDQSN_4
IO_L62P_M4DQ10_4
IO_L62N_M4DQ11_4
IO_L63P_M4DQ8_4
IO_L63N_M4DQ9_4
IO_L64P_M4DQ0_4
IO_L64N_M4DQ1_4
IO_L65P_M4DQ2_4
IO_L65N_M4DQ3_4
IO_L66P_M4LDQS_4
IO_L66N_M4LDQSN_4
IO_L67P_M4DQ6_4
IO_L67N_M4DQ7_4
IO_L68P_M4DQ4_4
IO_L68N_M4DQ5_4
IO_L69P_M4UDM_4
IO_L69N_M4LDM_4
IO_L70P_M4RASN_4
IO_L70N_M4CASN_4
IO_L71P_M4A5_4
IO_L71N_M4A6_4
IO_L72P_M4A3_4
IO_L72N_M4ODT_4
IO_L73P_M4CLK_4
IO_L73N_M4CLKN_4
IO_L74P_M4A0_4
IO_L74N_M4A1_4
IO_L75P_M4BA0_4
IO_L75N_M4BA1_4
IO_L76P_M4A7_4
IO_L76N_M4A2_4
IO_L77P_M4WE_4
IO_L77N_M4BA2_4
IO_L78P_M4A10_4
IO_L78N_M4A4_4
IO_L79P_M4A8_4
IO_L79N_M4A9_4
IO_L80P_M4CKE_4
IO_L80N_M4A12_4
IO_L81P_M4RESET_4
IO_L81N_M4A11_4
IO_L82P_M4A13_4
IO_L82N_M4A14_4
IO_L83P_4
IO_L83N_VREF_4
GND
PIR21702
VREF_0V75_DDR3
COC194
C194
!
I
C
COU35E
U35E
100R
PIR21701
COR217
R217
2
,
B
1
YII'
BANK 4
rT
l"
I
r-
f-
In
f-
131
I
I
2
C197
COC197
100n
PIR21801
R218
100R
JII'
I'
GND
DQ[15..0]
UDQS
UDQS
w
n
3
DQ[15..0]
UDQS_P
UDQS_N
To
LDQS_P
LDQS_N
Date:
File:
A4
Size
Title
Spartan-6 Bank 5
POMCB50DDR30W\E\
POMCB50DDR30UDQS0P
POMCB50DDR30UDQS0N
POMCB50DDR30UDM
POMCB50DDR30R\E\S\E\T\
POMCB50DDR30R\A\S\
POMCB50DDR30ODT
POMCB50DDR30LDQS0P
POMCB50DDR30LDQS0N
POMCB50DDR30LDM
POMCB50DDR30DQ0150000
POMCB50DDR30DQ15
POMCB50DDR30DQ14
POMCB50DDR30DQ13
POMCB50DDR30DQ12
POMCB50DDR30DQ11
POMCB50DDR30DQ10
POMCB50DDR30DQ9
POMCB50DDR30DQ8
POMCB50DDR30DQ7
POMCB50DDR30DQ6
POMCB50DDR30DQ5
POMCB50DDR30DQ4
POMCB50DDR30DQ3
POMCB50DDR30DQ2
POMCB50DDR30DQ1
POMCB50DDR30DQ0
POMCB50DDR30CKE
POMCB50DDR30CK0P
POMCB50DDR30CK0N
POMCB50DDR30C\A\S\
POMCB50DDR30BA020000
POMCB50DDR30BA2
POMCB50DDR30BA1
POMCB50DDR30BA0
POMCB50DDR30A0130000
POMCB50DDR30A13
POMCB50DDR30A12
POMCB50DDR30A11
POMCB50DDR30A10
POMCB50DDR30A9
POMCB50DDR30A8
POMCB50DDR30A7
POMCB50DDR30A6
POMCB50DDR30A5
POMCB50DDR30A4
POMCB50DDR30A3
POMCB50DDR30A2
POMCB50DDR30A1
POMCB50DDR30A0
POMCB50DDR3
MCB5_DDR3
4
Sheet 13 of
Drawn By:
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
29/03/2011
C:\Users\..\spartan6_bank5.SchDoc
RHINO
Number
Project
-
GND
PIC19702
PIC19701
IU-L JH II'
VREF_0V75_DDR3
PIR21802COR218
e
LDQS
LDQS
ap
C
RAS
CAS
UDM
LDM
ODT
CK_P
CK_N
WE
BA[2..0]
CKE
RESET
A[13..0]
4
-
1
Layout Notes:
1.) Ensure that ball H20 (a NO CONNECT pin) is not connected to any trace or plane
PIU350L21
DQ4
DQ5
DQ6
DQ7
LDQS
LDQS
DQ2
DQ3
DQ0
DQ1
DQ8
DQ9
DQ10
DQ11
UDQS
UDQS
DQ12
DQ13
DQ14
DQ15
of
ODT
CLK
CLK
WE
BA[2..0]
CKE
RESET
A[13..0]
II
1.0
65
Simon Scott
Revision
A
B
C
D
I
D
n
ty
RESET
A11
CKE
A12
A8
A9
A10
A4
WE
BA2
A7
A2
BA0
BA1
A0
A1
CLK
CLK
A3
ODT
A5
A6
A13
GND
DDR3_BUS
3
(
XC6SLX150T-4FGG676C
G20
B24
PIU350B24
A25
PIU350A25
K18
PIU350K18
K19
PIU350K19
D23
PIU350D23
C24
PIU350C24
H21
PIU350H21
H22
PIU350H22
F22
PIU350F22
G23
PIU350G23
J20
PIU350J20
J22
PIU350J22
E23
PIU350E23
E24
PIU350E24
L19
PIU350L19
K20
PIU350K20
C25
PIU350C25
C26
PIU350C26
B25
PIU350B25
B26
PIU350B26
K21
PIU350K21
K22
PIU350K22
M18
PIU350M18
M19
PIU350M19
F23
PIU350F23
G24
PIU350G24
J23
PIU350J23
J24
PIU350J24
E25
PIU350E25
E26
PIU350E26
D24
PIU350D24
D26
PIU350D26
F24
PIU350F24
F26
PIU350F26
H24
PIU350H24
H26
PIU350H26
G25
PIU350G25
G26
PIU350G26
K24
PIU350K24
K26
PIU350K26
J25
PIU350J25
J26
PIU350J26
M24
PIU350M24
M26
PIU350M26
L25
PIU350L25
L26
PIU350L26
N25
PIU350N25
N26
PIU350N26
M21
PIU350M21
M23
PIU350M23
L20
PIU350L20
L21
PIU350G20
H20
PIU350H20
f
er
si
ni
v
U
IO_L1P_A25_5
IO_L1N_A24_VREF_5
IO_L2P_M5A13_5
IO_L2N_M5A14_5
IO_L3P_M5RESET_5
IO_L3N_M5A11_5
IO_L4P_M5CKE_5
IO_L4N_M5A12_5
IO_L5P_M5A8_5
IO_L5N_M5A9_5
IO_L6P_M5A10_5
IO_L6N_M5A4_5
IO_L7P_M5WE_5
IO_L7N_M5BA2_5
IO_L8P_M5A7_5
IO_L8N_M5A2_5
IO_L9P_M5BA0_5
IO_L9N_M5BA1_5
IO_L10P_M5A0_5
IO_L10N_M5A1_5
IO_L11P_M5CLK_5
IO_L11N_M5CLKN_5
IO_L12P_M5A3_5
IO_L12N_M5ODT_5
IO_L13P_M5A5_5
IO_L13N_M5A6_5
IO_L14P_M5RASN_5
IO_L14N_M5CASN_5
IO_L15P_M5UDM_5
IO_L15N_M5LDM_5
IO_L16P_M5DQ4_5
IO_L16N_M5DQ5_5
IO_L17P_M5DQ6_5
IO_L17N_M5DQ7_5
IO_L18P_M5LDQS_5
IO_L18N_M5LDQSN_5
IO_L19P_M5DQ2_5
IO_L19N_M5DQ3_5
IO_L20P_M5DQ0_5
IO_L20N_M5DQ1_5
IO_L21P_M5DQ8_5
IO_L21N_M5DQ9_5
IO_L22P_M5DQ10_5
IO_L22N_M5DQ11_5
IO_L23P_M5UDQS_5
IO_L23N_M5UDQSN_5
IO_L24P_M5DQ12_5
IO_L24N_M5DQ13_5
IO_L25P_M5DQ14_5
IO_L25N_M5DQ15_5
IO_L26P_5
IO_L26N_VREF_5
IO_L27P_5
IO_L27N_5
VREF_0V75_DDR3
COC196
C196
100n
PIC19602 PIC19601
ll '
I
I
C
COU35F
U35F
2
I
B
A
1
r
BANK 5
r
I
r-
f-
I
r-
MGTREFCLK1N_245
MGTREFCLK1P_245
MGTREFCLK1N_123
MGTREFCLK1P_123
MGTREFCLK1N_101
MGTREFCLK1P_101
GND
XC6SLX150T-4FGG676C
PIU350AF17
AF17
MGTREFCLK1N_267
AE17
PIU350AE17 MGTREFCLK1P_267
PIU350AD12
AC12
PIU350AC12
AD12
PIU350B16
PIU350A16
A16
B16
PIU350D11
PIU350C11
C11
D11
AD16
PIU350AD16 MGTREFCLK0N_267
AC16
PIU350AC16 MGTREFCLK0P_267
PIU350AF11
AF11
MGTREFCLK0N_245
AE11
PIU350AE11 MGTREFCLK0P_245
C15
PIU350C15 MGTREFCLK0N_123
D15
PIU350D15 MGTREFCLK0P_123
PIU350A10
B6
A8
B8
D17
PIU350D17
C17
PIU350C17
PIU350B8
PIU350A8
PIU350D9
PIU350C9
C9
D9
PIU350B6
A6
PIU350A6
A18
B18
AD8
AC8
AF7
AE7
AF9
AE9
PIU350AD18
AD18 10GBE_1_RX2_N
AC18 10GBE_1_RX2_P
PIU350AC18
PIU350AE9
PIU350AF9
MGTTXN1_267
MGTTXP1_267
PIU350AE21
PIU350AF21
AF21
AE21
AD20 10GBE_1_RX3_N
MGTRXN1_267 PIU350AD20
AC20 10GBE_1_RX3_P
MGTRXP1_267 PIU350AC20
ap
PIC56001
PIC56101 PIC56102
C561
COC281100n
COC274100n
C560
PIC56002
PIC55901 PIC55902
COC273100n
C559
PIC55801 PIC55802
COC269100n
C558
132
GND
1
2
e
PIC55701 PIC55702
COC268100n
C557
COC267100n
C556
PIC55601 PIC55602
PIC55501 PIC55502
COC266100n
C555
COC265100n
C554
PIC55401 PIC55402
PIC32501 PIC32502
COC264100n
C325
COC263100n
C321
PIC32101 PIC32102
PIC31901 PIC31902
COC262100n
C319
COC261100n
C315
PIC31501 PIC31502
PIC31301 PIC31302
COC260100n
C313
COC259100n
C312
PIC31201 PIC31202
COC258100n
C308
PIC30801 PIC30802
COC257100n
C306
PIC30601 PIC30602
C
10GBE_1_RX0_N
10GBE_1_RX0_P
AD10 10GBE_1_RX1_N
AC10 10GBE_1_RX1_P
PIU350AC10
PIU350AD10
PIU350AE7
PIU350AF7
PIU350AC8
PIU350AD8
A20
B20
PIU350B20
PIU350A20
of
10GBE_0_RX3_N
10GBE_0_RX3_P
10GBE_0_RX2_N
10GBE_0_RX2_P
10GBE_0_RX1_N
10GBE_0_RX1_P
10GBE_0_RX0_N
10GBE_0_RX0_P
ty
PIU350D19
PIU350C19
C19
D19
PIU350B18
PIU350A18
AF19
MGTTXN0_267 PIU350AF19
AE19
MGTTXP0_267 PIU350AE19
MGTRXN0_267
MGTRXP0_267
MGTTXN1_245
MGTTXP1_245
MGTRXN1_245
MGTRXP1_245
MGTTXN0_245
MGTTXP0_245
MGTRXN0_245
MGTRXP0_245
MGTTXN1_123
MGTTXP1_123
MGTRXN1_123
MGTRXP1_123
MGTTXN0_123
MGTTXP0_123
er
si
MGTRXN0_123
MGTRXP0_123
C7
D7
PIU350D7
PIU350C7
TX3_N
TX3_P
RX3_N
RX3_P
TX2_N
TX2_P
RX2_N
RX2_P
To
TX1_N
TX1_P
RX1_N
RX1_P
TX0_N
TX0_P
RX0_N
RX0_P
,
3
4
PO10GBE010TX30P
PO10GBE010TX30N
PO10GBE010TX20P
PO10GBE010TX20N
PO10GBE010TX10P
PO10GBE010TX10N
PO10GBE010TX00P
PO10GBE010TX00N
PO10GBE010RX30P
PO10GBE010RX30N
PO10GBE010RX20P
PO10GBE010RX20N
PO10GBE010RX10P
PO10GBE010RX10N
PO10GBE010RX00P
PO10GBE010RX00N
PO10GBE01
10GBE_1
Date:
File:
A4
Size
Title
COC338 PIC3 902 C339
COC339 PIC340 2 C340
COC340 PIC34102 C341
COC341 PIC3420 C342
COC342 PIC34 02 C343
COC343
PIC3 802 C338
PIC3 801 4u7 PIC3 901 4u7 PIC340 1 4u7 PIC3410 4u7 PIC34201 4u7 PIC34 01 4u7
VCC_1V2_MGT
1.) Trace from MGTAVTTRCAL pin to 49R9 resistor must be same length and
geometry as trace from MGTRREF pin to other side of resistor
2.) Place decoupling caps as close to FPGA supply pins as possible
3.) The MGTRX/TX lines (to the CX4 connectors) must be routed as differential
pairs, with 50 ohms single-ended impedance and 100 ohms differential impedance.
Layout Notes:
PO10GBE000TX30P
PO10GBE000TX30N
PO10GBE000TX20P
PO10GBE000TX20N
PO10GBE000TX10P
PO10GBE000TX10N
PO10GBE000TX00P
PO10GBE000TX00N
PO10GBE000RX30P
PO10GBE000RX30N
PO10GBE000RX20P
PO10GBE000RX20N
PO10GBE000RX10P
PO10GBE000RX10N
PO10GBE000RX00P
PO10GBE000RX00N
PO10GBE00
10GBE_0
w
n
MGT_BUS
TX3_N
TX3_P
RX3_N
RX3_P
TX2_N
TX2_P
RX2_N
RX2_P
TX1_N
TX1_P
RX1_N
RX1_P
TX0_N
TX0_P
RX0_N
RX0_P
X
C354 PIC35 02 COC355
C355 PIC35602 COC356
C356 PIC35702 COC357
C357 PIC35802 C358
C359
C360 PIC36102 COC361
C361 PIC3620 C362
C352 PIC35302 C353
COC358 PIC35902 COC359
COC362 PIC36 02 C363
COC363 PIC350 2 C350
COC350 PIC35102 C351
COC351 PIC3520 COC352
COC353
PIC35402 COC354
PIC360 2 COC360
PIC35401 220n PIC35 01 220n PIC35601 220n PIC35701 220n PIC35801 220n PIC35901 220n PIC360 1 220n PIC36101 220n PIC36201 220n PIC36 01 220n PIC350 1 220n PIC3510 220n PIC35201 220n PIC35301 220n
MGT_CLK1_N
MGT_CLK1_P
MGTRREF_245
A10
MGTREFCLK0N_101
B10
PIU350B10 MGTREFCLK0P_101
49R9
AB10
PIR26901
PIU350AB10
COR269
R269
PIR26902
MGTRREF_101
MGTAVTTRCAL_101
MGTAVTTRCAL_245
MGTAVTTRX_101
MGTAVTTRX_123
MGTAVTTRX_245
MGTAVTTRX_267
MGTAVTTTX_101
MGTAVTTTX_123
MGTAVTTTX_245
MGTAVTTTX_267
ni
v
U
MGTTXN1_101
MGTTXP1_101
MGTRXN1_101
MGTRXP1_101
MGTTXN0_101
MGTTXP0_101
MGTRXN0_101
MGTRXP0_101
MGT_BUS
3
GND
4
Sheet 14 of
Drawn By:
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
29/03/2011
C:\Users\..\spartan6_mgt.SchDoc
RHINO
Number
Project
65
Simon Scott
Revision
1.0
COC344 PIC34502 C345
COC345 PIC34602 C346
COC346 PIC34702 C347
COC347 PIC34802 C348
COC348 PIC34902 C349
COC349
PIC34 02 C344
PIC34 01 220n PIC34501 220n PIC34601 220n PIC34701 220n PIC34801 220n PIC34901 220n
VCC_1V2_MGT
GND
Spartan-6 Multi-Gigabit Transceivers
~
II'
D
VCC_1V2_MGT
POMGT0CLKS0IN0MGT0CLK10P
POMGT0CLKS0IN0MGT0CLK10N
POMGT0CLKS0IN0MGT0CLK00P
POMGT0CLKS0IN0MGT0CLK00N
POMGT0CLKS0IN
MGT_CLKS_IN
MGT_CLK0_N
MGT_CLK0_P
MGT_CLKS
49R9
E9
PIR26801
PIU350E9
COR268
R268
PIR26802
PIU350D8
PIU350AB12
AB12
D8
D18
PIU350D18
AC9
PIU350AC9
AC19
PIU350AC19
A7
PIU350A7
A19
PIU350A19
AF8
PIU350AF8
AF20
PIU350AF20
E11
PIU350E11
PIU350C16
PIU350C10
MGTAVCC_101
MGTAVCC_123
MGTAVCC_245
MGTAVCC_267
MGTAVCCPLL0_101
MGTAVCCPLL0_123
MGTAVCCPLL0_245
MGTAVCCPLL0_267
MGTAVCCPLL1_101
MGTAVCCPLL1_123
MGTAVCCPLL1_245
MGTAVCCPLL1_267
COU35G
U35G
C10
C16
AD11
PIU350AD11
AD17
PIU350AD17
B11
PIU350B11
C14
PIU350C14
AE12
PIU350AE12
AD15
PIU350AD15
C12
PIU350C12
B15
PIU350B15
AD13
PIU350AD13
AE16
PIU350AE16
VCC_1V2_MGT
2
, r
C
B
A
1
r
~"II'
D
C
B
A
A
I
1
111'
I
ff111'
-
I, 1
X
GND
PIJ10014
PIJ10012
PIJ1008
PIJ10010
PIJ1006
PIJ1004
PIJ1002
CONN_EN
PIR23501
R235
10k
PIR23502COR235
'V
II'
GND
3
PID1201
COD12
D12
RED
PIR2310
R231
2k2
PIR23102COR231
W22
V19
Y19
CMPCS_B_2
f--
133
~
4
Sheet 15 of
Drawn By:
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
29/03/2011
C:\Users\..\spartan6_config.SchDoc
RHINO
Number
Project
Spartan-6 Configuration
1.0
65
Simon Scott
Revision
POCONF0DONE
CONF_DONE
-
Date:
File:
A4
Size
Title
XC6SLX150T-4FGG676C
PIU350Y19
PIU350V19
PIU350W22
VFS
RFUSE
A24
TCK
C23
TDI
G21
PIU350G21 TDO
F21
PIU350F21 TMS
PIU350C23
PIU350A24
AF2
PROGRAM_B_2
Y22
PIU350Y22 SUSPEND
PIU350AF2
DONE_2
COU35H
U35H
PIU350AF25
AF25
The DONE pin is an open-drain output. It is therefore
pulled-up to 3V3, and connected directly to the
AM3517, without going through the voltage translator
JTAG_HDR_EN
90120-0122
P1
COP1
1
2
PIP102
PIP101
w
n
GND
PID120
PIR2301
R230
169R
PIR2302 COR230
VCC_3V3_FPGA
(
2
PIJ10013
PIJ10011
1
2
3
4
5
6
7
8
9 10
11 12
13 14
ill
PIJ1007
PIJ1009
PIJ1005
PIJ1003
L
VCC_3V3_FPGA
To
00
VCC_3V3_FPGA
CONN_TDI
CONN_TMS
CONN_TCK
TDO
I
SBH11-PBPC-D07-ST-BK
.
PIJ1001
II IT
VCC_3V3_FPGA
J10
COJ10
111'
GND
TDO
I,
GND
GND
e
ap
C
CONN_EN
1
15
PIU39015
PIU3901
PIR23401
1k
PIR23302
PIR2901
111'
GND
-----111'
PIU3908
A/B
OE
I
CONN_TMS
3
1B
6
2B
10
PIU39010 3B
13
PIU39013 4B
If
PIU3906
PIU3903
of
4
7
9
PIU3909
12
PIU39012
PIU3907
PIU3904
!
1
A
B
C
D
I
D
I
CONN_TCK
CONN_TDI
TDO
1Y
2Y
3Y
4Y
SN74LVC257APW
ty
COU39
U39
R234
2k2
0R
PIR23202
R229
10k
PIR2902 COR229
VCC_3V3_FPGA
4
I
C
POFPGA0JTAG0TMS
POFPGA0JTAG0TDO
POFPGA0JTAG0TDI
POFPGA0JTAG0TCK
POFPGA0JTAG0T\R\S\T\
POFPGA0JTAG
FPGA_JTAG
Y II'
2
PIU3902 1A
5
PIU3905 2A
11
PIU39011 3A
14
PIU39014 4A
100n
~
GND
PIC20802
COC208
C208
PIC20801
POSUSPEND
SUSPEND
3
VCC_2V5_FPGA
PIR23402 COR234
COR233
R233
PIR23301
POCONF0PROGRAM0B
CONF_PROGRAM_B
COR232
R232
PIR23201
POR\E\S\E\T\
RESET
I,
TCK
TDI
TDO
TMS
TRST
JTAG_BUS
er
PIU39016 si
VCC_3V3_FPGA
ni
v
U
2
11 1'
B
General Notes:
1.) Install jumper to enable the JTAG programming header
2.) For final board, JTAG 14-pin header and jumper should not be populated
3.) The Spartan-6 JTAG pins have internal pull-up resistors
Layout Notes:
1.) Place "JTAG_HDR_EN" next to jumper on silkscreen
2.) Place "NOT_CONFIGD" next to LED on silkscreen
1
!
16
!
~
VCC
L
,.1~
GND
L
8
L
I
f-
f-
f-
I~
~
A
I
B
I
1
AD2
P4
P9
PIU350P9
T2
PIU350T2
T7
PIU350T7
W4
PIU350W4
W6
PIU350W6
Y2
PIU350Y2
I
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
V22
K11
K17
L12
PIU350L12
L14
PIU350L14
L16
PIU350L16
M11
PIU350M11
M12
PIU350M12
M13
PIU350M13
M14
PIU350M14
M15
PIU350M15
M16
PIU350M16
N12
PIU350N12
N13
PIU350N13
N15
PIU350N15
N16
PIU350N16
P11
PIU350P11
P12
PIU350P12
P14
PIU350P14
P15
PIU350P15
R11
PIU350R11
R12
PIU350R12
R13
PIU350R13
R14
PIU350R14
R15
PIU350R15
R16
PIU350R16
R17
PIU350R17
T11
PIU350T11
T13
PIU350T13
T15
PIU350T15
T17
PIU350T17
U10
PIU350U10
U16
VCC_1V2_FPGA
of
e
ap
C
To
3
w
n
A1
A11
A15
PIU350A15
A17
PIU350A17
A21
PIU350A21
A26
PIU350A26
A9
PIU350A9
AB16
PIU350AB16
AB2
PIU350AB2
AB20
PIU350AB20
AB25
PIU350AB25
AC11
PIU350AC11
AC13
PIU350AC13
AC15
PIU350AC15
AC17
PIU350AC17
AD19
PIU350AD19
AD21
PIU350AD21
AD7
PIU350AD7
AD9
PIU350AD9
AE10
PIU350AE10
AE18
PIU350AE18
AE20
PIU350AE20
AE22
PIU350AE22
AE6
PIU350AE6
AE8
PIU350AE8
AF1
PIU350AF1
AF10
PIU350AF10
AF12
PIU350AF12
AF16
PIU350AF16
AF18
PIU350AF18
AF26
PIU350AF26
B17
PIU350B17
B19
PIU350B19
B7
PIU350B7
B9
PIU350B9
C18
PIU350C18
C20
PIU350C20
C6
PIU350C6
C8
PIU350C8
D10
PIU350D10
D12
PIU350D12
D14
PIU350D14
D16
PIU350D16
D4
PIU350D4
E15
PIU350E15
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
E19
E22
E7
PIU350E7
F2
PIU350F2
F25
PIU350F25
G14
PIU350G14
H23
PIU350H23
H4
PIU350H4
J19
PIU350J19
J8
PIU350J8
K16
PIU350K16
K2
PIU350K2
K25
PIU350K25
L11
PIU350L11
L13
PIU350L13
L15
PIU350L15
L17
PIU350L17
M22
PIU350M22
M5
PIU350M5
N11
PIU350N11
N14
PIU350N14
P13
PIU350P13
P16
PIU350P16
P2
PIU350P2
P20
PIU350P20
P25
PIU350P25
P7
PIU350P7
T10
PIU350T10
T12
PIU350T12
T14
PIU350T14
T16
PIU350T16
T18
PIU350T18
T21
PIU350T21
T5
PIU350T5
U11
PIU350U11
U17
PIU350U17
V2
PIU350V2
V25
PIU350V25
V8
PIU350V8
Y10
PIU350Y10
Y14
PIU350Y14
Y23
PIU350Y23
Y4
PIU350Y4
Y7
PIU350Y7
PIU350E22
PIU350E19
134
-
4
Sheet 16 of
Drawn By:
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
29/03/2011
C:\Users\..\spartan6_power.SchDoc
RHINO
Number
Project
Spartan-6 Power
GND
4
-
Date:
File:
A4
Size
Title
XC6SLX150T-4FGG676C
PIU350A11
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
COU35J
U35J
PIU350A1
GND
II'
2
PIU350U16
PIU350K17
PIU350K11
ty
VCC_3V3_FPGA
er
si
ni
v
AA5
PIU350AA5
AB18
PIU350AB18
AB8
PIU350AB8
AC21
PIU350AC21
AC7
PIU350AC7
D20
PIU350D20
D6
PIU350D6
E17
PIU350E17
G5
PIU350G5
J10
PIU350J10
J18
PIU350J18
K13
PIU350K13
K15
PIU350K15
L18
PIU350L18
L22
PIU350L22
L5
PIU350L5
M17
PIU350M17
N10
PIU350N10
R22
PIU350R22
U12
PIU350U12
U14
PIU350U14
U18
PIU350U18
U6
PIU350U6
V17
PIU350V17
V9
PIU350V9
W13
PIU350W13
PIU350V22
U
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VBATT
II'
XC6SLX150T-4FGG676C
PIU350G22
PIU350D25
D25
G22
H25
PIU350H25
J21
PIU350J21
K23
PIU350K23
M20
PIU350M20
M25
PIU350M25
PIU350D2
D2
F4
PIU350F4
H2
PIU350H2
J6
PIU350J6
K4
PIU350K4
M2
PIU350M2
M7
PIU350M7
PIU350P4
PIU350AD2
PIU350AA20
PIU350AA14
AA14
AA20
AB6
PIU350AB6
AE14
PIU350AE14
AE23
PIU350AE23
AE4
PIU350AE4
W11
PIU350W11
W15
PIU350W15
Y18
PIU350Y18
Y8
PIU350Y8
PIU350P23
P23
T25
PIU350T25
W21
PIU350W21
W23
PIU350W23
Y25
PIU350Y25
PIU350AD25
P18
PIU350P18
PIU350AB23
AB23
AD25
COU35I
U35I
B13
VCCO_0
C22
PIU350C22 VCCO_0
C4
PIU350C4 VCCO_0
E21
PIU350E21
VCCO_0
F13
PIU350F13 VCCO_0
F8
PIU350F8 VCCO_0
G18
PIU350G18 VCCO_0
H11
PIU350H11 VCCO_0
H16
PIU350H16
VCCO_0
J14
PIU350J14 VCCO_0
PIU350B13
3
1.0
65
Simon Scott
Revision
A
B
C
D
I
D
VCC_1V5_FPGA
VCC_1V5_FPGA
VCC_2V5_FPGA
VCC_2V5_FPGA
VCC_3V3_FPGA
VCC_2V5_FPGA
2
I
C
1
I
e-
f-
f-
D
C
B
A
135
e
COC307
PIC307 2 C307
PIC307 1 4u7
GND
C314
PIC31402 COC314
PIC31401 4u7
1
2
Layout Notes:
1.) The 4u7 caps should be placed within 50mm of the outer edge of the FPGA
2.) The 1uF caps must be placed within 12mm of the outer edge of the FPGA. These caps must be placed as
close to the FPGA as possible, preferably on the reverse sideo of the PCB, within the FPGA footprint.
3.) Capacitor mounting should be optimised for low inductance
GND
COC320
PIC320 2 C320
PIC320 1 4u7
3
PIC29601 1u PIC29701 1u
3
C323 PIC32402 C324
COC322 PIC32 02 COC323
COC324
PIC32 02 C322
PIC32 01 1u PIC32 01 1u PIC32401 1u
w
n
COC309 PIC310 2 COC310
COC311
C310 PIC31 02 C311
PIC309 2 C309
PIC309 1 1u PIC310 1 1u PIC31 01 1u
PIC29501 1u
COC295 PIC29602 COC296
COC297
C296 PIC29702 C297
PIC29502 C295
To
VCC_2V5_FPGA
ap
C
GND
VCC_1V5_FPGA
of
PIC29301 4u7
COC293
PIC29302 C293
VCC_1V5_FPGA
ty
VCC_3V3_FPGA
GND
Decoupling caps for FPGA VCCO_4
Decoupling caps for FPGA VCCO_2
Decoupling caps for FPGA VCCO_0
er
si
ni
v
Decoupling caps for FPGA VCCAUX
U
Decoupling caps for FPGA VCCINT
GND
C316 PIC31702 COC317
C317 PIC31802 COC318
C318
PIC31602 COC316
PIC31601 1u PIC31701 1u PIC31801 1u
C299 PIC30 2 COC300
C300
PIC29 02 COC299
PIC29 01 4u7 PIC30 1 4u7
VCC_2V5_FPGA
COC305
C302 PIC30 2 COC303
C303 PIC30402 COC304
C304 PIC305 2 C305
PIC302 COC302
PIC302 1 1u PIC30 1 1u PIC30401 1u PIC305 1 1u
PIC28 01 1u PIC28901 1u PIC290 1 1u PIC2910 1u
PIC28501 4u7 PIC28601 4u7
GND
COC291
C288 PIC28902 COC289
C289 PIC290 2 COC290
C290 PIC29102 C291
PIC28 02 COC288
C285 PIC28602 COC286
C286
PIC28502 COC285
VCC_2V5_FPGA
GND
C270 PIC27102 COC271
C271 PIC27 02 COC272
C272
PIC270 2 COC270
PIC270 1 4u7 PIC2710 4u7 PIC27 01 4u7
VCC_3V3_FPGA
COC277 PIC27802 COC278
COC279 PIC280 2 C280
COC280
C275 PIC27602 COC276
C276 PIC27 02 C277
C278 PIC27902 C279
PIC27502 COC275
PIC27501 1u PIC27601 1u PIC27 01 1u PIC27801 1u PIC27901 1u PIC280 1 1u
PIC240 1 1u PIC2410 1u PIC24201 1u PIC24301 1u PIC24 01 1u PIC24501 1u PIC24601 1u PIC24701 1u PIC24801 1u PIC24901 1u
PIC210 1 4u7 PIC21 01 4u7 PIC21 01 4u7 PIC21301 4u7
GND
COC241 PIC24202 COC242
COC243 PIC24 02 C244
COC244 PIC24502 COC245
COC246 PIC24702 COC247
COC248 PIC24902 C249
COC249
PIC240 2 COC240
C240 PIC24102 C241
C242 PIC24302 C243
C245 PIC24602 C246
C247 PIC24802 C248
2
PIC210 2 COC210
C210 PIC21 02 COC211
C211 PIC21 02 COC212
C212 PIC21302 COC213
C213
VCC_1V2_FPGA
1
Date:
File:
A4
Size
Title
4
Sheet 17 of
Drawn By:
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
29/03/2011
C:\Users\..\spartan6_decoupling.SchDoc
RHINO
Number
Project
1.0
65
Simon Scott
Revision
Spartan-6 Supply Decoupling Caps
Decoupling caps for FPGA VCCO_5
Decoupling caps for FPGA VCCO_3
Decoupling caps for FPGA VCCO_1
4
D
C
B
A
I
I
R393
49R9
R394
49R9
R408
4k7
PIR4071 PIR408 1 PIR4091
e
RESET
CS
K1
PIU710K1 ODT
L8
PIU710L8 ZQ
T2
PIU710T2
L2
PIU710L2
w
PIU710A9 PIU710B3 PIU710E PIU710G8n
PIU710J2 PIU710J8 PIU710M PIU710M9 PIU710P PIU710P9 PIU710T1 PIU710T9 PIU710B PIU710B9 PIU710D1 PIU710D8 PIU710E2 PIU710E8 PIU710F9 PIU710G1 PIU710G9
To
K7
CK
J7
CK
K9
PIU710K9 CKE
PIU710J7
PIU710K7
== III'.........
136
I
ill'
GND
-
II'
-11
==
-11-11-11I- -11-11, -11-
I
III
I
\.
-11-11-11-11-11-11-
GND
-11- -11- 111'
-11- -11-11- -11-11- -11-11- -11-11- -11- f -11- -11-11--11-11--11-
3
GND
II'
2
LDQS_N
LDQS_P
PIU710G3
G3
F3
E7
D3
J1
J9
L1
PIU710L1
L9
PIU710L9
M7
PIU710M7
T7
PIU710T7
PIU710J9
PIU710J1
PIU710D3
PIU710E7
PIU710F3
LDM
UDM
UDQS_N
UDQS_P
PIU710C7
PIU710B7
B7
C7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
i 50_OHM
i 100R_DIFF
DQ[15..0]
29/03/2011
C:\Users\..\ram_ddr3.SchDoc
4
Sheet 18 of
Drawn By:
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
1.0
65
Simon Scott
Revision
Layout Notes:
1.) Place termination resistors close to IC pins
2.) Single ended bus lines must have 50 ohms trace impedance
3.) Differential pairs must have 100 ohm differential trace
impedance
NC
NC
NC
NC
NC
NC
LDM
UDM
LDQS
LDQS
UDQS
UDQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
E3
PIU710E3
F7
PIU710F7
F2
PIU710F2
F8
PIU710F8
H3
PIU710H3
H8
PIU710H8
G2
PIU710G2
H7
PIU710H7
D7
PIU710D7
C3
PIU710C3
C8
PIU710C8
C2
PIU710C2
A7
PIU710A7
A2
PIU710A2
B8
PIU710B8
A3
PIU710A3
COU1
U71
MT41J128M16HA-187E
GND
-
Date:
File:
C477 PIC47802 C478
C479 PIC480 2 C480
C482 PIC48302 C483
C487 PIC48 02 C488
COC2
COC3
COC5
COC7
COC8
COC10
COC11
COC12
COC13
COC15
COC16
COC17
PIC47502 C475
PIC47602 C476
PIC47 02 COC4
PIC47902 COC6
PIC48102 C481
PIC48202 COC9
PIC48 02 C484
PIC48502 C485
PIC48602 C486
PIC48702 COC14
PIC48902 C489
PIC490 2 C490
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
4u7
Title
PIC47501
PIC47601
PIC47 01
PIC47801
PIC47901
PIC480 1
PIC4810
PIC48201
PIC48301
PIC48 01
PIC48501
PIC48601
PIC48701
PIC48 01
PIC48901
PIC490 1
DDR3 RAM
C493 PIC49 02 C494
C495 PIC49602 C496
C498 PIC49 02 C499
C503 PIC50402 C504
COC18
COC19
COC21
COC23
COC24
COC26
COC27
COC28
COC29
COC31
COC32
PIC49102 C491
PIC4920 C492
PIC49302 COC20
PIC49502 COC22
PIC49702 C497
PIC49802 COC25
PIC50 2 C500
PIC50102 C501
PIC502 C502
PIC503 2 COC30
PIC50 2 C505
Size
Number
Project
PIC4910 100n PIC49201 100n PIC49301 100n PIC49 01 100n PIC49501 100n PIC49601 100n PIC49701 100n PIC49801 100n PIC49 01 100n PIC50 1 100n PIC50101 100n PIC502 1 100n PIC503 1 100n PIC50401 100n PIC50 1 100n
RHINO
A4
GND
I'
GND
L3
WE
K3
CAS
J3
PIU710J3 RAS
PIU710K3
PIU710L3
PIU710B2 PIU710D9 PIU710G7 PIU710K2 PIU710K8 PIU710N1 PIU710N9 PIU710R PIU710R9 PIU710A1 PIU710A8 PIU710C PIU710C9 PIU710D2 PIU710E9 PIU710F1 PIU710H2 PIU710H9 PIU710H1 PIU710M8
=
==
-
PIR406 1
R409
240R
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
M2
BA0
N8
BA1
M3
PIU710M3 BA2
PIU710N8
PIU710M2
N3
PIU710N3
P7
PIU710P7
P3
PIU710P3
N2
PIU710N2
P8
PIU710P8
P2
PIU710P2
R8
PIU710R8
R2
PIU710R2
T8
PIU710T8
R3
PIU710R3
L7
PIU710L7
R7
PIU710R7
N7
PIU710N7
T3
PIU710T3
ap
PIR40 1
R404
49R9
IIIIII
'~~~~
i
50_OHM
VTT_0V75_DDR3
R407
4k7
100R
PIR40502
C
PIR403 1
R403
49R9
100n
PIC47402
COC1
C474
PIC47401
lc.:
CK_N
CK_P
CKE
RESET
ODT
•
VCC_1V5_FPGA
'--+-+----+
PIR406 2 COR22 PIR4072 COR23
PIR408 2COR24
PIR4092 COR25
R406
4k7
PIR40501
R405
COR21
of
R402
49R9
-_
WE
CAS
RAS
ODT
PIR4021
ty
er
si
PIR401
R401
49R9
VCC_1V5_FPGA
Q!\
CK_N
CK_P
CKE
RESET
ODT
,------------
~
:
-
WE
CAS
RAS
~51: _____Ji'
,
UDQS_N
UDQS_P
LDQS_N
LDQS_P
LDM
UDM
_J
RESET
I
UDQS_N
UDQS_P
LDQS_N
LDQS_P
LDM
UDM
Ls:
•
•
•
•
DQ[15..0]
CK_N
CK_P
CKE
· .
.•
I
DQ[15..0]
100R_DIFF i
PIR40 1
R400
49R9
ni
v
U
PIR3901
R399
49R9
-
I
BA[2..0]
PIR39801
R398
49R9
•
•
•
•
•
,-
A[13..0]
PIR39701
R397
49R9
I
BA[2..0]
50_OHM
i
PIR39601
R396
49R9
VCC_1V5_FPGA
___S2
1
R392
49R9
III
DDR3_BUS
PODDR30BUS0W\E\0ram0ddr300
PODDR30BUS0UDQS0ram0ddr3000P
PODDR30BUS0UDQS0ram0ddr3000N
PODDR30BUS0UDM0ram0ddr300
PODDR30BUS0R\E\S\E\T\0ram0ddr300
PODDR30BUS0R\A\S\0ram0ddr300
PODDR30BUS0ODT0ram0ddr300
PODDR30BUS0LDQS0ram0ddr3000P
PODDR30BUS0LDQS0ram0ddr3000N
PODDR30BUS0LDM0ram0ddr300
PODDR30BUS0DQ01500000ram0ddr300
PODDR30BUS0DQ150ram0ddr300
PODDR30BUS0DQ140ram0ddr300
PODDR30BUS0DQ130ram0ddr300
PODDR30BUS0DQ120ram0ddr300
PODDR30BUS0DQ110ram0ddr300
PODDR30BUS0DQ100ram0ddr300
PODDR30BUS0DQ90ram0ddr300
PODDR30BUS0DQ80ram0ddr300
PODDR30BUS0DQ70ram0ddr300
PODDR30BUS0DQ60ram0ddr300
PODDR30BUS0DQ50ram0ddr300
PODDR30BUS0DQ40ram0ddr300
PODDR30BUS0DQ30ram0ddr300
PODDR30BUS0DQ20ram0ddr300
PODDR30BUS0DQ10ram0ddr300
PODDR30BUS0DQ00ram0ddr300
PODDR30BUS0CKE0ram0ddr300
PODDR30BUS0CK0ram0ddr3000P
PODDR30BUS0CK0ram0ddr3000N
PODDR30BUS0C\A\S\0ram0ddr300
PODDR30BUS0BA0200000ram0ddr300
PODDR30BUS0BA20ram0ddr300
PODDR30BUS0BA10ram0ddr300
PODDR30BUS0BA00ram0ddr300
PODDR30BUS0A01300000ram0ddr300
PODDR30BUS0A130ram0ddr300
PODDR30BUS0A120ram0ddr300
PODDR30BUS0A110ram0ddr300
PODDR30BUS0A100ram0ddr300
PODDR30BUS0A90ram0ddr300
PODDR30BUS0A80ram0ddr300
PODDR30BUS0A70ram0ddr300
PODDR30BUS0A60ram0ddr300
PODDR30BUS0A50ram0ddr300
PODDR30BUS0A40ram0ddr300
PODDR30BUS0A30ram0ddr300
PODDR30BUS0A20ram0ddr300
PODDR30BUS0A10ram0ddr300
PODDR30BUS0A00ram0ddr300
PODDR30BUS0ram0ddr300
R391
49R9
I I
A[13..0]
DDR3_BUS
PIR39501
R395
49R9
R390
49R9
PIR38501 PIR39502 COR11
PIR38601 PIR39602 COR12
PIR38701 PIR39702 COR13
PIR3801 PIR39802 COR14
PIR38901 PIR3902 COR15
PIR3901 PIR40 2 COR16
PIR3910 PIR4012 COR17
PIR39201 PIR402 COR18
PIR39 01 PIR403 2COR19
PIR39401 PIR40 2COR20
R389
49R9
4
I
D
C
-
BA0
BA1
BA2
R388
49R9
VREF_0V75_DDR3
51 _ __
i
50_OHM
WE
CAS
RAS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
R387
49R9
~
I-I-I--
BA[2..0]
A[13..0]
R386
49R9
I-I-I--
B
A
R385
49R9
PIR38502 COR1 PIR38602 COR2 PIR38702 COR3 PIR3802 COR4 PIR38902 COR5 PIR3902 COR6 PIR39102 COR7 PIR3920 COR8 PIR39 02COR9 PIR39402COR10
,---
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
VTT_0V75_DDR3
H1
M8
3
~
I-I-I--
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
I-I-I--
VREFDQ
VREFCA
2
,---
~~~~ !Q
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
1
L-
~________
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
I
I
r-
f-
D
C
B
A
I
I
R418
49R9
R419
49R9
R433
4k7
PIR43201 PIR43 01 PIR4301
e
RESET
CS
K1
PIU720K1 ODT
L8
PIU720L8 ZQ
T2
PIU720T2
L2
PIU720L2
w
PIU720A9 PIU720B3 PIU720E1 PIU720G8n
PIU720J2 PIU720J8 PIU720M1 PIU720M9 PIU720P1 PIU720P9 PIU720T1 PIU720T9 PIU720B1 PIU720B9 PIU720D1 PIU720D8 PIU720E PIU720E8 PIU720F9 PIU720G1 PIU720G9
To
K7
CK
J7
CK
K9
PIU720K9 CKE
PIU720J7
PIU720K7
== III'.........
137
I
ill'
GND
-
II'
-11
==
-11-11-11I- -11-11, -11-
I
III
I
\.
-11-11-11-11-11-11-
GND
-11- -11- 111'
-11- -11-11- -11-11- -11-11- -11-11- -11- f -11- -11-11--11-11--11-
3
GND
II'
2
LDQS_N
LDQS_P
PIU720G3
G3
F3
E7
D3
J1
J9
L1
PIU720L1
L9
PIU720L9
M7
PIU720M7
T7
PIU720T7
PIU720J9
PIU720J1
PIU720D3
PIU720E7
PIU720F3
LDM
UDM
UDQS_N
UDQS_P
PIU720C7
PIU720B7
B7
C7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
i 50_OHM
i 100R_DIFF
DQ[15..0]
29/03/2011
C:\Users\..\ram_ddr3.SchDoc
4
Sheet 19 of
Drawn By:
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
1.0
65
Simon Scott
Revision
Layout Notes:
1.) Place termination resistors close to IC pins
2.) Single ended bus lines must have 50 ohms trace impedance
3.) Differential pairs must have 100 ohm differential trace
impedance
NC
NC
NC
NC
NC
NC
LDM
UDM
LDQS
LDQS
UDQS
UDQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
E3
PIU720E3
F7
PIU720F7
F2
PIU720F2
F8
PIU720F8
H3
PIU720H3
H8
PIU720H8
G2
PIU720G2
H7
PIU720H7
D7
PIU720D7
C3
PIU720C3
C8
PIU720C8
C2
PIU720C2
A7
PIU720A7
A2
PIU720A2
B8
PIU720B8
A3
PIU720A3
COU1
U72
MT41J128M16HA-187E
GND
-
Date:
File:
C509 PIC510 2 C510
C511 PIC51202 C512
C514 PIC51502 C515
C519 PIC520 2 C520
COC2
COC3
COC5
COC7
COC8
COC10
COC11
COC12
COC13
COC15
COC16
COC17
PIC507 2 C507
PIC508 2 C508
PIC50902 COC4
PIC51 02 COC6
PIC51302 C513
PIC51402 COC9
PIC51602 C516
PIC51702 C517
PIC51802 C518
PIC51902 COC14
PIC52102 C521
PIC52 02 C522
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
4u7
Title
PIC507 1
PIC508 1
PIC50901
PIC510 1
PIC51 01
PIC51201
PIC51301
PIC51401
PIC51501
PIC51601
PIC51701
PIC51801
PIC51901
PIC520 1
PIC5210
PIC52 01
DDR3 RAM
C525 PIC52602 C526
C527 PIC52802 C528
C530 PIC53102 C531
C535 PIC53602 C536
COC18
COC19
COC21
COC23
COC24
COC26
COC27
COC28
COC29
COC31
COC32
PIC52302 C523
PIC52402 C524
PIC52502 COC20
PIC52702 COC22
PIC52902 C529
PIC530 2 COC25
PIC5320 C532
PIC53 02 C533
PIC53402 C534
PIC53 02 COC30
PIC53702 C537
Size
Number
Project
PIC52301 100n PIC52401 100n PIC52501 100n PIC52601 100n PIC52701 100n PIC52801 100n PIC52901 100n PIC530 1 100n PIC53101 100n PIC53201 100n PIC53 01 100n PIC53401 100n PIC53 01 100n PIC53601 100n PIC53701 100n
RHINO
A4
GND
I'
GND
L3
WE
K3
CAS
J3
PIU720J3 RAS
PIU720K3
PIU720L3
PIU720B2 PIU720D9 PIU720G7 PIU720K PIU720K8 PIU720N1 PIU720N9 PIU720R1 PIU720R9 PIU720A1 PIU720A8 PIU720C1 PIU720C9 PIU720D PIU720E9 PIU720F1 PIU720H PIU720H9 PIU720H1 PIU720M8
=
==
-
PIR4310
R434
240R
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
M2
BA0
N8
BA1
M3
PIU720M3 BA2
PIU720N8
PIU720M2
N3
PIU720N3
P7
PIU720P7
P3
PIU720P3
N2
PIU720N2
P8
PIU720P8
P2
PIU720P2
R8
PIU720R8
R2
PIU720R2
T8
PIU720T8
R3
PIU720R3
L7
PIU720L7
R7
PIU720R7
N7
PIU720N7
T3
PIU720T3
ap
PIR42901
R429
49R9
IIIIII
'~~~~
i
50_OHM
VTT_0V75_DDR3
R432
4k7
100R
PIR43002
C
PIR42801
R428
49R9
100n
PIC50602
COC1
C506
PIC50601
lc.:
CK_N
CK_P
CKE
RESET
ODT
•
VCC_1V5_FPGA
'--+-+----+
PIR43102 COR22 PIR4320 COR23
PIR43 02COR24
PIR4302 COR25
R431
4k7
PIR43001
R430
COR21
of
R427
49R9
-_
WE
CAS
RAS
ODT
PIR42701
ty
er
si
PIR42601
R426
49R9
VCC_1V5_FPGA
Q!\
CK_N
CK_P
CKE
RESET
ODT
,------------
~
:
-
WE
CAS
RAS
~51: _____Ji'
,
UDQS_N
UDQS_P
LDQS_N
LDQS_P
LDM
UDM
_J
RESET
I
UDQS_N
UDQS_P
LDQS_N
LDQS_P
LDM
UDM
Ls:
•
•
•
•
DQ[15..0]
CK_N
CK_P
CKE
· .
.•
I
DQ[15..0]
100R_DIFF i
PIR42501
R425
49R9
ni
v
U
PIR4201
R424
49R9
-
I
BA[2..0]
PIR42301
R423
49R9
•
•
•
•
•
,-
A[13..0]
PIR4201
R422
49R9
I
BA[2..0]
50_OHM
i
PIR4210
R421
49R9
VCC_1V5_FPGA
___S2
1
R417
49R9
III
DDR3_BUS
PODDR30BUS0W\E\0ram0ddr301
PODDR30BUS0UDQS0ram0ddr3010P
PODDR30BUS0UDQS0ram0ddr3010N
PODDR30BUS0UDM0ram0ddr301
PODDR30BUS0R\E\S\E\T\0ram0ddr301
PODDR30BUS0R\A\S\0ram0ddr301
PODDR30BUS0ODT0ram0ddr301
PODDR30BUS0LDQS0ram0ddr3010P
PODDR30BUS0LDQS0ram0ddr3010N
PODDR30BUS0LDM0ram0ddr301
PODDR30BUS0DQ01500000ram0ddr301
PODDR30BUS0DQ150ram0ddr301
PODDR30BUS0DQ140ram0ddr301
PODDR30BUS0DQ130ram0ddr301
PODDR30BUS0DQ120ram0ddr301
PODDR30BUS0DQ110ram0ddr301
PODDR30BUS0DQ100ram0ddr301
PODDR30BUS0DQ90ram0ddr301
PODDR30BUS0DQ80ram0ddr301
PODDR30BUS0DQ70ram0ddr301
PODDR30BUS0DQ60ram0ddr301
PODDR30BUS0DQ50ram0ddr301
PODDR30BUS0DQ40ram0ddr301
PODDR30BUS0DQ30ram0ddr301
PODDR30BUS0DQ20ram0ddr301
PODDR30BUS0DQ10ram0ddr301
PODDR30BUS0DQ00ram0ddr301
PODDR30BUS0CKE0ram0ddr301
PODDR30BUS0CK0ram0ddr3010P
PODDR30BUS0CK0ram0ddr3010N
PODDR30BUS0C\A\S\0ram0ddr301
PODDR30BUS0BA0200000ram0ddr301
PODDR30BUS0BA20ram0ddr301
PODDR30BUS0BA10ram0ddr301
PODDR30BUS0BA00ram0ddr301
PODDR30BUS0A01300000ram0ddr301
PODDR30BUS0A130ram0ddr301
PODDR30BUS0A120ram0ddr301
PODDR30BUS0A110ram0ddr301
PODDR30BUS0A100ram0ddr301
PODDR30BUS0A90ram0ddr301
PODDR30BUS0A80ram0ddr301
PODDR30BUS0A70ram0ddr301
PODDR30BUS0A60ram0ddr301
PODDR30BUS0A50ram0ddr301
PODDR30BUS0A40ram0ddr301
PODDR30BUS0A30ram0ddr301
PODDR30BUS0A20ram0ddr301
PODDR30BUS0A10ram0ddr301
PODDR30BUS0A00ram0ddr301
PODDR30BUS0ram0ddr301
R416
49R9
I I
A[13..0]
DDR3_BUS
PIR4201
R420
49R9
R415
49R9
PIR410 PIR420 COR11
PIR410 PIR4210 COR12
PIR4120 PIR420 COR13
PIR4130 PIR4230 COR14
PIR410 PIR420 COR15
PIR4150 PIR4250 COR16
PIR4160 PIR4260 COR17
PIR4170 PIR4270 COR18
PIR41801 PIR42802COR19
PIR41901 PIR42902COR20
R414
49R9
4
I
D
C
-
BA0
BA1
BA2
R413
49R9
VREF_0V75_DDR3
51 _ __
i
50_OHM
WE
CAS
RAS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
R412
49R9
~
I-I-I--
BA[2..0]
A[13..0]
R411
49R9
I-I-I--
B
A
R410
49R9
PIR4102 COR1 PIR4102 COR2 PIR4120 COR3 PIR41302 COR4 PIR4102 COR5 PIR41502 COR6 PIR41602 COR7 PIR41702 COR8 PIR41802COR9 PIR41902COR10
,---
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
VTT_0V75_DDR3
H1
M8
3
~
I-I-I--
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
I-I-I--
VREFDQ
VREFCA
2
,---
~~~~ !Q
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
1
L-
~________
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
I
I
r-
f-
D
C
B
A
A
I
1
vO 0 lJ
, !
d 101
!
I
11
,
I
lJlJ
I
)
.,
00
n
I
I--
138
5
PIC26701 4u7 PIC26801 4u7 PIC26901 4u7
F~"
PIC26501 4u7 PIC26 01 4u7
)
GND
PIC273014u7
H
GND
COC6
PIC27302C273
12P0V
6
GND
PIC274014u7 PIC28101 4u7
COC7
COC8
PIC27402C274
PIC28102 C281
VADJ
ZDOK_P0
ZDOK_N0
ZDOK_P1
ZDOK_N1
ZDOK_P2
ZDOK_N2
ZDOK_P3
ZDOK_N3
7
29/03/2011
C:\Users\..\fmc_hpc.SchDoc
RHINO
Number
Project
Revision
8
1.0
8
Sheet 20 of 65
Drawn By:
Simon Scott
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
FMC HPC Connector (top level)
I-Date:
File:
A3
Size
Title
xxxxxxxxxxxxxxxJ
4
I
F~h
COC4
COC5
C267 PIC26802 C268
PIC26702 COC3
PIC26902 C269
HA01_P
HA01_N
HA05_P
HA05_N
HA09_P
HA09_N
HA13_P
HA13_N
HA16_P
HA16_N
HA20_P
HA20_N
HB03_P
HB03_N
HB05_P
HB05_N
HB09_P
HB09_N
HB13_P
HB13_N
HB19_P
HB19_N
HB21_P
HB21_N
VADJ_1
-
3
I
r
COC1
C266
PIC26502 C265
PIC26 02 COC2
F~"
GND
3P3VAUX
w
n
ROW_E
ZDOK_P[3..0]
ZDOK_N[3..0]
I--
2
3P3V
To
1'1
VADJ
e
FMC_HPC_E
50R_SNGL_100R_DIFF i
I
Layout Notes:
1.) LA_xx_N/P signals must be routed with 50R single-ended impedance, and 100R differential impendance
2.) CLKx_M2C_N/P signals must be routed with 100R differential impedance
3.) All differential pair signals must be routed as differential pairs
\
ap
VREF_A_M2C
PRSNT_M2C_L
CLK0_M2C_P
CLK0_M2C_N
LA_P2
LA_N2
LA_P4
LA_N4
LA_P7
LA_N7
LA_P11
LA_N11
LA_P15
LA_N15
LA_P19
LA_N19
LA_P21
LA_N21
LA_P24
LA_N24
LA_P28
LA_N28
LA_P30
LA_N30
LA_P32
LA_N32
VADJ
TMS
TRST
,
ROW_K
IIIIII
VREF_A_M2C
PRSNT_M2C_L
CLK0_M2C_P
CLK0_M2C_N
LA02_P
LA02_N
LA04_P
LA04_N
LA07_P
LA07_N
LA11_P
LA11_N
LA15_P
LA15_N
LA19_P
LA19_N
LA21_P
LA21_N
LA24_P
LA24_N
LA28_P
LA28_N
LA30_P
LA30_N
LA32_P
LA32_N
VADJ_4
GA1
3P3V
3P3V
3P3V
,
ROW_J
)
i
fmc_hpc_j_k_gnd
fmc_hpc_j_k_gnd.SchDoc
(
C
JTAG
'6--'
ROW_H
)
FMC_HPC_H
3P3VAUX
TCK
TDI
TDO
~
[ IIII
TCK
TDI
TDO
3P3VAUX
TMS
TRST_L
GA1
3P3V_2
3P3V_3
3P3V_4
POFMC0BUS0ZDOK0P0300000fmc00
POFMC0BUS0ZDOK0P30fmc00
POFMC0BUS0ZDOK0P20fmc00
POFMC0BUS0ZDOK0P10fmc00
POFMC0BUS0ZDOK0P00fmc00
POFMC0BUS0ZDOK0N0300000fmc00
POFMC0BUS0ZDOK0N30fmc00
POFMC0BUS0ZDOK0N20fmc00
POFMC0BUS0ZDOK0N10fmc00
POFMC0BUS0ZDOK0N00fmc00
POFMC0BUS0VREF0A0M2C0fmc00
POFMC0BUS0VADJ0fmc00
POFMC0BUS0PRSNT0M2C0L0fmc00
POFMC0BUS0PG0C2M0fmc00
POFMC0BUS0LA0P03300000fmc00
POFMC0BUS0LA0P330fmc00
POFMC0BUS0LA0P320fmc00
POFMC0BUS0LA0P310fmc00
POFMC0BUS0LA0P300fmc00
POFMC0BUS0LA0P290fmc00
POFMC0BUS0LA0P280fmc00
POFMC0BUS0LA0P270fmc00
POFMC0BUS0LA0P260fmc00
POFMC0BUS0LA0P250fmc00
POFMC0BUS0LA0P240fmc00
POFMC0BUS0LA0P230fmc00
POFMC0BUS0LA0P220fmc00
POFMC0BUS0LA0P210fmc00
POFMC0BUS0LA0P200fmc00
POFMC0BUS0LA0P190fmc00
POFMC0BUS0LA0P180fmc00
POFMC0BUS0LA0P170fmc00
POFMC0BUS0LA0P160fmc00
POFMC0BUS0LA0P150fmc00
POFMC0BUS0LA0P140fmc00
POFMC0BUS0LA0P130fmc00
POFMC0BUS0LA0P120fmc00
POFMC0BUS0LA0P110fmc00
POFMC0BUS0LA0P100fmc00
POFMC0BUS0LA0P90fmc00
POFMC0BUS0LA0P80fmc00
POFMC0BUS0LA0P70fmc00
POFMC0BUS0LA0P60fmc00
POFMC0BUS0LA0P50fmc00
POFMC0BUS0LA0P40fmc00
POFMC0BUS0LA0P30fmc00
POFMC0BUS0LA0P20fmc00
POFMC0BUS0LA0P10fmc00
POFMC0BUS0LA0P00fmc00
POFMC0BUS0LA0N03300000fmc00
POFMC0BUS0LA0N330fmc00
POFMC0BUS0LA0N320fmc00
POFMC0BUS0LA0N310fmc00
POFMC0BUS0LA0N300fmc00
POFMC0BUS0LA0N290fmc00
POFMC0BUS0LA0N280fmc00
POFMC0BUS0LA0N270fmc00
POFMC0BUS0LA0N260fmc00
POFMC0BUS0LA0N250fmc00
POFMC0BUS0LA0N240fmc00
POFMC0BUS0LA0N230fmc00
POFMC0BUS0LA0N220fmc00
POFMC0BUS0LA0N210fmc00
POFMC0BUS0LA0N200fmc00
POFMC0BUS0LA0N190fmc00
POFMC0BUS0LA0N180fmc00
POFMC0BUS0LA0N170fmc00
POFMC0BUS0LA0N160fmc00
POFMC0BUS0LA0N150fmc00
POFMC0BUS0LA0N140fmc00
POFMC0BUS0LA0N130fmc00
POFMC0BUS0LA0N120fmc00
POFMC0BUS0LA0N110fmc00
POFMC0BUS0LA0N100fmc00
POFMC0BUS0LA0N90fmc00
POFMC0BUS0LA0N80fmc00
POFMC0BUS0LA0N70fmc00
POFMC0BUS0LA0N60fmc00
POFMC0BUS0LA0N50fmc00
POFMC0BUS0LA0N40fmc00
POFMC0BUS0LA0N30fmc00
POFMC0BUS0LA0N20fmc00
POFMC0BUS0LA0N10fmc00
POFMC0BUS0LA0N00fmc00
POFMC0BUS0JTAG0TMS0fmc00
POFMC0BUS0JTAG0TDO0fmc00
POFMC0BUS0JTAG0TDI0fmc00
POFMC0BUS0JTAG0TCK0fmc00
POFMC0BUS0JTAG0T\R\S\T\0fmc00
POFMC0BUS0JTAG0fmc00
POFMC0BUS0I2C0SDA0fmc00
POFMC0BUS0I2C0SCL0fmc00
POFMC0BUS0I2C0fmc00
POFMC0BUS0GA10fmc00
POFMC0BUS0GA00fmc00
POFMC0BUS0CLK10M2C0fmc000P
POFMC0BUS0CLK10M2C0fmc000N
POFMC0BUS0CLK00M2C0fmc000P
POFMC0BUS0CLK00M2C0fmc000N
POFMC0BUS012P0V0fmc00
POFMC0BUS03P3VAUX0fmc00
POFMC0BUS03P3V0fmc00
POFMC0BUS0fmc00
FMC_BUS
Tnw
,
CLK1_M2C_P
CLK1_M2C_N
LA00_P_CC
LA00_N_CC
LA03_P
LA03_N
LA08_P
LA08_N
LA12_P
LA12_N
LA16_P
LA16_N
LA20_P
LA20_N
LA22_P
LA22_N
LA25_P
LA25_N
LA29_P
LA29_N
LA31_P
LA31_N
LA33_P
LA33_N
VADJ_3
of
,
CLK1_M2C_P
CLK1_M2C_N
LA_P0
LA_N0
LA_P3
LA_N3
LA_P8
LA_N8
LA_P12
LA_N12
LA_P16
LA_N16
LA_P20
LA_N20
LA_P22
LA_N22
LA_P25
LA_N25
LA_P29
LA_N29
LA_P31
LA_N31
LA_P33
LA_N33
VADJ
ty
,
FMC_HPC_G
I2C
i
ROW_G
y
\
ROW_F
GA0
12P0V
12P0V
3P3V
I2C
GA0
GA1
JTAG
PRSNT_M2C_L
PG_C2M
VREF_A_M2C
VADJ
3P3VAUX
3P3V
12P0V
CLK0_M2C_P
CLK0_M2C_N
CLK1_M2C_P
CLK1_M2C_N
ZDOK_N[3..0]
ZDOK_P[3..0]
11Hi .
I2C
GA0
GA1
JTAG
PRSNT_M2C_L
PG_C2M
VREF_A_M2C
VADJ
3P3VAUX
3P3V
12P0V
CLK0_M2C_P
CLK0_M2C_N
CLK1_M2C_P
CLK1_M2C_N
ZDOK_P[3..0]
100R_DIFF
ZDOK_N[3..0]
i
LA_P[33..0]
LA_N[33..0]
FMC_BUS
7
A
--
A
B
C
D
I
D
!I ~
ROW_E
SCL
SDA
,L,
er
si
LA_P1
LA_N1
LA_P5
LA_N5
LA_P9
LA_N9
LA_P13
LA_N13
LA_P17
LA_N17
LA_P23
LA_N23
LA_P26
LA_N26
6
~
,-,
ROW_E
SCL
SDA
GA0
12P0V_1
12P0V_2
3P3V_1
ni
v
GND
PG_C2M
[xx
PG_C2M
GBTCLK0_M2C_P
GBTCLK0_M2C_N
LA01_P_CC
LA01_N_CC
LA05_P
LA05_N
LA09_P
LA09_N
LA13_P
LA13_N
LA17_P_CC
LA17_N_CC
LA23_P
LA23_N
LA26_P
LA26_N
FMC_HPC_D
5
-
I
C
I--
ROW_D
,
U
I--
ROW_C
xx
LA_P6
LA_N6
LA_P10
LA_N10
LA_P14
LA_N14
LA_P18
LA_N18
LA_P27
LA_N27
hi,
ROW_B
LA_N[33..0]
LA_P[33..0]
\ \
DP0_C2M_P
DP0_C2M_N
DP0_M2C_P
DP0_M2C_N
LA06_P
LA06_N
LA10_P
LA10_N
LA14_P
LA14_N
LA18_P_CC
LA18_N_CC
LA27_P
LA27_N
FMC_HPC_C
'6 '
50R_SNGL_100R_DIFF i
4
~ <;l ____ ~
'
fmc_hpc_e_f_g_h
fmc_hpc_e_f_g_h.SchDoc
3
-
ROW_A
fmc_hpc_a_b_c_d
fmc_hpc_a_b_c_d.SchDoc
2
(
B
1
I
f-
)
f-
f-
I--
I--
I--
I--
A
I
1
vO 0 lJ
, !
d 101
!
I
11
,
I
lJlJ
I
)
.,
00
n
I
I--
139
5
PIC28401 4u7 PIC28701 4u7 PIC29201 4u7
F~"
PIC28201 4u7 PIC28301 4u7
)
GND
PIC294014u7
H
GND
COC6
PIC29402C294
12P0V
6
GND
PIC298014u7 PIC30101 4u7
COC7
COC8
PIC29802C298
PIC30102 C301
VADJ
ZDOK_P0
ZDOK_N0
ZDOK_P1
ZDOK_N1
ZDOK_P2
ZDOK_N2
ZDOK_P3
ZDOK_N3
7
29/03/2011
C:\Users\..\fmc_hpc.SchDoc
RHINO
Number
Project
Revision
8
1.0
8
Sheet 21 of 65
Drawn By:
Simon Scott
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
FMC HPC Connector (top level)
I-Date:
File:
A3
Size
Title
xxxxxxxxxxxxxxxJ
4
I
F~h
COC4
COC5
C284 PIC28702 C287
PIC28402 COC3
PIC29202 C292
HA01_P
HA01_N
HA05_P
HA05_N
HA09_P
HA09_N
HA13_P
HA13_N
HA16_P
HA16_N
HA20_P
HA20_N
HB03_P
HB03_N
HB05_P
HB05_N
HB09_P
HB09_N
HB13_P
HB13_N
HB19_P
HB19_N
HB21_P
HB21_N
VADJ_1
-
3
I
r
COC1
C283
PIC28202 C282
PIC28302 COC2
F~"
GND
3P3VAUX
w
n
ROW_E
ZDOK_P[3..0]
ZDOK_N[3..0]
I--
2
3P3V
To
1'1
VADJ
e
FMC_HPC_E
50R_SNGL_100R_DIFF i
I
Layout Notes:
1.) LA_xx_N/P signals must be routed with 50R single-ended impedance, and 100R differential impendance
2.) CLKx_M2C_N/P signals must be routed with 100R differential impedance
3.) All differential pair signals must be routed as differential pairs
\
ap
VREF_A_M2C
PRSNT_M2C_L
CLK0_M2C_P
CLK0_M2C_N
LA_P2
LA_N2
LA_P4
LA_N4
LA_P7
LA_N7
LA_P11
LA_N11
LA_P15
LA_N15
LA_P19
LA_N19
LA_P21
LA_N21
LA_P24
LA_N24
LA_P28
LA_N28
LA_P30
LA_N30
LA_P32
LA_N32
VADJ
TMS
TRST
,
ROW_K
IIIIII
VREF_A_M2C
PRSNT_M2C_L
CLK0_M2C_P
CLK0_M2C_N
LA02_P
LA02_N
LA04_P
LA04_N
LA07_P
LA07_N
LA11_P
LA11_N
LA15_P
LA15_N
LA19_P
LA19_N
LA21_P
LA21_N
LA24_P
LA24_N
LA28_P
LA28_N
LA30_P
LA30_N
LA32_P
LA32_N
VADJ_4
GA1
3P3V
3P3V
3P3V
,
ROW_J
)
i
fmc_hpc_j_k_gnd
fmc_hpc_j_k_gnd.SchDoc
(
C
JTAG
'6--'
ROW_H
)
FMC_HPC_H
3P3VAUX
TCK
TDI
TDO
~
[ IIII
TCK
TDI
TDO
3P3VAUX
TMS
TRST_L
GA1
3P3V_2
3P3V_3
3P3V_4
POFMC0BUS0ZDOK0P0300000fmc01
POFMC0BUS0ZDOK0P30fmc01
POFMC0BUS0ZDOK0P20fmc01
POFMC0BUS0ZDOK0P10fmc01
POFMC0BUS0ZDOK0P00fmc01
POFMC0BUS0ZDOK0N0300000fmc01
POFMC0BUS0ZDOK0N30fmc01
POFMC0BUS0ZDOK0N20fmc01
POFMC0BUS0ZDOK0N10fmc01
POFMC0BUS0ZDOK0N00fmc01
POFMC0BUS0VREF0A0M2C0fmc01
POFMC0BUS0VADJ0fmc01
POFMC0BUS0PRSNT0M2C0L0fmc01
POFMC0BUS0PG0C2M0fmc01
POFMC0BUS0LA0P03300000fmc01
POFMC0BUS0LA0P330fmc01
POFMC0BUS0LA0P320fmc01
POFMC0BUS0LA0P310fmc01
POFMC0BUS0LA0P300fmc01
POFMC0BUS0LA0P290fmc01
POFMC0BUS0LA0P280fmc01
POFMC0BUS0LA0P270fmc01
POFMC0BUS0LA0P260fmc01
POFMC0BUS0LA0P250fmc01
POFMC0BUS0LA0P240fmc01
POFMC0BUS0LA0P230fmc01
POFMC0BUS0LA0P220fmc01
POFMC0BUS0LA0P210fmc01
POFMC0BUS0LA0P200fmc01
POFMC0BUS0LA0P190fmc01
POFMC0BUS0LA0P180fmc01
POFMC0BUS0LA0P170fmc01
POFMC0BUS0LA0P160fmc01
POFMC0BUS0LA0P150fmc01
POFMC0BUS0LA0P140fmc01
POFMC0BUS0LA0P130fmc01
POFMC0BUS0LA0P120fmc01
POFMC0BUS0LA0P110fmc01
POFMC0BUS0LA0P100fmc01
POFMC0BUS0LA0P90fmc01
POFMC0BUS0LA0P80fmc01
POFMC0BUS0LA0P70fmc01
POFMC0BUS0LA0P60fmc01
POFMC0BUS0LA0P50fmc01
POFMC0BUS0LA0P40fmc01
POFMC0BUS0LA0P30fmc01
POFMC0BUS0LA0P20fmc01
POFMC0BUS0LA0P10fmc01
POFMC0BUS0LA0P00fmc01
POFMC0BUS0LA0N03300000fmc01
POFMC0BUS0LA0N330fmc01
POFMC0BUS0LA0N320fmc01
POFMC0BUS0LA0N310fmc01
POFMC0BUS0LA0N300fmc01
POFMC0BUS0LA0N290fmc01
POFMC0BUS0LA0N280fmc01
POFMC0BUS0LA0N270fmc01
POFMC0BUS0LA0N260fmc01
POFMC0BUS0LA0N250fmc01
POFMC0BUS0LA0N240fmc01
POFMC0BUS0LA0N230fmc01
POFMC0BUS0LA0N220fmc01
POFMC0BUS0LA0N210fmc01
POFMC0BUS0LA0N200fmc01
POFMC0BUS0LA0N190fmc01
POFMC0BUS0LA0N180fmc01
POFMC0BUS0LA0N170fmc01
POFMC0BUS0LA0N160fmc01
POFMC0BUS0LA0N150fmc01
POFMC0BUS0LA0N140fmc01
POFMC0BUS0LA0N130fmc01
POFMC0BUS0LA0N120fmc01
POFMC0BUS0LA0N110fmc01
POFMC0BUS0LA0N100fmc01
POFMC0BUS0LA0N90fmc01
POFMC0BUS0LA0N80fmc01
POFMC0BUS0LA0N70fmc01
POFMC0BUS0LA0N60fmc01
POFMC0BUS0LA0N50fmc01
POFMC0BUS0LA0N40fmc01
POFMC0BUS0LA0N30fmc01
POFMC0BUS0LA0N20fmc01
POFMC0BUS0LA0N10fmc01
POFMC0BUS0LA0N00fmc01
POFMC0BUS0JTAG0TMS0fmc01
POFMC0BUS0JTAG0TDO0fmc01
POFMC0BUS0JTAG0TDI0fmc01
POFMC0BUS0JTAG0TCK0fmc01
POFMC0BUS0JTAG0T\R\S\T\0fmc01
POFMC0BUS0JTAG0fmc01
POFMC0BUS0I2C0SDA0fmc01
POFMC0BUS0I2C0SCL0fmc01
POFMC0BUS0I2C0fmc01
POFMC0BUS0GA10fmc01
POFMC0BUS0GA00fmc01
POFMC0BUS0CLK10M2C0fmc010P
POFMC0BUS0CLK10M2C0fmc010N
POFMC0BUS0CLK00M2C0fmc010P
POFMC0BUS0CLK00M2C0fmc010N
POFMC0BUS012P0V0fmc01
POFMC0BUS03P3VAUX0fmc01
POFMC0BUS03P3V0fmc01
POFMC0BUS0fmc01
FMC_BUS
Tnw
,
CLK1_M2C_P
CLK1_M2C_N
LA00_P_CC
LA00_N_CC
LA03_P
LA03_N
LA08_P
LA08_N
LA12_P
LA12_N
LA16_P
LA16_N
LA20_P
LA20_N
LA22_P
LA22_N
LA25_P
LA25_N
LA29_P
LA29_N
LA31_P
LA31_N
LA33_P
LA33_N
VADJ_3
of
,
CLK1_M2C_P
CLK1_M2C_N
LA_P0
LA_N0
LA_P3
LA_N3
LA_P8
LA_N8
LA_P12
LA_N12
LA_P16
LA_N16
LA_P20
LA_N20
LA_P22
LA_N22
LA_P25
LA_N25
LA_P29
LA_N29
LA_P31
LA_N31
LA_P33
LA_N33
VADJ
ty
,
FMC_HPC_G
I2C
i
ROW_G
y
\
ROW_F
GA0
12P0V
12P0V
3P3V
I2C
GA0
GA1
JTAG
PRSNT_M2C_L
PG_C2M
VREF_A_M2C
VADJ
3P3VAUX
3P3V
12P0V
CLK0_M2C_P
CLK0_M2C_N
CLK1_M2C_P
CLK1_M2C_N
ZDOK_N[3..0]
ZDOK_P[3..0]
11Hi .
I2C
GA0
GA1
JTAG
PRSNT_M2C_L
PG_C2M
VREF_A_M2C
VADJ
3P3VAUX
3P3V
12P0V
CLK0_M2C_P
CLK0_M2C_N
CLK1_M2C_P
CLK1_M2C_N
ZDOK_P[3..0]
100R_DIFF
ZDOK_N[3..0]
i
LA_P[33..0]
LA_N[33..0]
FMC_BUS
7
A
--
A
B
C
D
I
D
!I ~
ROW_E
SCL
SDA
,L,
er
si
LA_P1
LA_N1
LA_P5
LA_N5
LA_P9
LA_N9
LA_P13
LA_N13
LA_P17
LA_N17
LA_P23
LA_N23
LA_P26
LA_N26
6
~
,-,
ROW_E
SCL
SDA
GA0
12P0V_1
12P0V_2
3P3V_1
ni
v
GND
PG_C2M
[xx
PG_C2M
GBTCLK0_M2C_P
GBTCLK0_M2C_N
LA01_P_CC
LA01_N_CC
LA05_P
LA05_N
LA09_P
LA09_N
LA13_P
LA13_N
LA17_P_CC
LA17_N_CC
LA23_P
LA23_N
LA26_P
LA26_N
FMC_HPC_D
5
-
I
C
I--
ROW_D
,
U
I--
ROW_C
xx
LA_P6
LA_N6
LA_P10
LA_N10
LA_P14
LA_N14
LA_P18
LA_N18
LA_P27
LA_N27
hi,
ROW_B
LA_N[33..0]
LA_P[33..0]
\ \
DP0_C2M_P
DP0_C2M_N
DP0_M2C_P
DP0_M2C_N
LA06_P
LA06_N
LA10_P
LA10_N
LA14_P
LA14_N
LA18_P_CC
LA18_N_CC
LA27_P
LA27_N
FMC_HPC_C
'6 '
50R_SNGL_100R_DIFF i
4
~ <;l ____ ~
'
fmc_hpc_e_f_g_h
fmc_hpc_e_f_g_h.SchDoc
3
-
ROW_A
fmc_hpc_a_b_c_d
fmc_hpc_a_b_c_d.SchDoc
2
(
B
1
I
f-
)
f-
f-
I--
I--
I--
I--
A
I
A34
PIJ170A39
A39
PIJ170A38
A38
PIJ170A35
A35
PIJ170A34
DP5_C2M_N
DP5_C2M_P
DP4_C2M_N
DP4_C2M_P
I
140
1
DP5_C2M_N
DP5_C2M_P
DP4_C2M_N
DP4_C2M_P
DP3_C2M_N
DP3_C2M_P
\
2
ASP-134486-01
B25
PIJ170B25
B29
PIJ170B29
3
RES0
DP6_C2M_N
DP6_C2M_P
DP7_C2M_N
B40
PIJ170B40
B37
PIJ170B37
B36
PIJ170B36
B33
PIJ170B33
B32
DP7_C2M_P PIJ170B32
DP8_C2M_N
B28
DP8_C2M_P PIJ170B28
DP9_C2M_N
B24
PIJ170B24
B21
PIJ170B21
DP6_C2M_N
DP6_C2M_P
DP7_C2M_N
DP7_C2M_P
DP8_C2M_N
DP8_C2M_P
DP9_C2M_N
DP9_C2M_P
GBTCLK1_M2C_N
GBTCLK1_M2C_P
DP6_M2C_N
DP6_M2C_P
DP7_M2C_N
RES0
ty
4
I
er
si
DP7_M2C_P
of
LA27_P
LA18_N_CC
LA18_P_CC
LA14_N
LA14_P
LA10_N
LA10_P
LA06_N
ASP-134486-01
C26
PIJ170C26
C23
PIJ170C23
C22
PIJ170C22
C19
PIJ170C19
C18
C15
PIJ170C18
PIJ170C15
C14
PIJ170C14
C11
PIJ170C11
5
3P3V_1
12P0V_2
12P0V_1
GA0
w
n
3P3V_1
12P0V_2
12P0V_1
GA0
SDA
SCL
LA27_N
LA27_P
LA18_N_CC
LA18_P_CC
LA14_N
LA14_P
LA10_N
LA10_P
LA06_N
LA06_P
DP0_M2C_N
DP0_M2C_P
To
C39
PIJ170C39
C37
PIJ170C37
C35
PIJ170C35
C34
PIJ170C34
e
C30
PIJ170C30
C31
SDA PIJ170C31
SCL
C27
LA27_N PIJ170C27
ap
C
C7
PIJ170C7
C6
PIJ170C6
C10
LA06_P PIJ170C10
DP0_M2C_N
DP0_M2C_P
\
I
6
D24
PIJ170D24
D31
PIJ170D31
D30
PIJ170D30
D29
PIJ170D29
D27
PIJ170D27
D33
PIJ170D33
D35
PIJ170D40
D40
PIJ170D38
D38
PIJ170D36
D36
PIJ170D35
3P3V_4
3P3V_3
3P3V_2
GA1
TRST_L
TMS
3P3VAUX
TDO
TDI
TCK
LA26_N
LA26_P
LA23_N
LA23_P
r--
7
29/03/2011
C:\Users\..\fmc_hpc_a_b_c_d.SchDoc
RHINO
Number
Project
POROW0D0TRST0L0fmc0hpc0a0b0c0d1
POROW0D0TMS0fmc0hpc0a0b0c0d1
POROW0D0TDO0fmc0hpc0a0b0c0d1
POROW0D0TDI0fmc0hpc0a0b0c0d1
POROW0D0TCK0fmc0hpc0a0b0c0d1
POROW0D0PG0C2M0fmc0hpc0a0b0c0d1
POROW0D0LA260fmc0hpc0a0b0c0d10P
POROW0D0LA260fmc0hpc0a0b0c0d10N
POROW0D0LA230fmc0hpc0a0b0c0d10P
POROW0D0LA230fmc0hpc0a0b0c0d10N
POROW0D0LA170P0CC0fmc0hpc0a0b0c0d1
POROW0D0LA170N0CC0fmc0hpc0a0b0c0d1
POROW0D0LA130fmc0hpc0a0b0c0d10P
POROW0D0LA130fmc0hpc0a0b0c0d10N
POROW0D0LA090fmc0hpc0a0b0c0d10P
POROW0D0LA090fmc0hpc0a0b0c0d10N
POROW0D0LA050fmc0hpc0a0b0c0d10P
POROW0D0LA050fmc0hpc0a0b0c0d10N
POROW0D0LA010P0CC0fmc0hpc0a0b0c0d1
POROW0D0LA010N0CC0fmc0hpc0a0b0c0d1
POROW0D0GBTCLK00M2C0fmc0hpc0a0b0c0d10P
POROW0D0GBTCLK00M2C0fmc0hpc0a0b0c0d10N
POROW0D0GA10fmc0hpc0a0b0c0d1
POROW0D03P3VAUX0fmc0hpc0a0b0c0d1
POROW0D03P3V040fmc0hpc0a0b0c0d1
POROW0D03P3V030fmc0hpc0a0b0c0d1
POROW0D03P3V020fmc0hpc0a0b0c0d1
POROW0D0fmc0hpc0a0b0c0d1
ROW_D
Revision
1.0
8
Sheet 22 of 65
Drawn By:
Simon Scott
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
FMC HPC Connector (Rows A, B, C, D)
3P3V_4
3P3V_3
3P3V_2
GA1
D34
TRST_L PIJ170D34
TMS
D32
3P3VAUX PIJ170D32
TDO
TDI
TCK
LA26_N
D26
LA26_P PIJ170D26
LA23_N
LA17_N_CC
LA17_P_CC
LA13_N
LA13_P
LA09_N
r--
Date:
File:
A3
D21
PIJ170D21
D20
PIJ170D20
D18
PIJ170D18
D17
PIJ170D17
LA09_P
LA05_N
LA05_P
LA01_N_CC
\
Size
D14
D15
PIJ170D15
PIJ170D14
D12
PIJ170D12
D11
PIJ170D11
D23
LA23_P PIJ170D23
LA17_N_CC
LA17_P_CC
LA13_N
LA13_P
LA09_N
LA09_P
LA05_N
LA05_P
LA01_P_CC
GBTCLK0_M2C_N
GBTCLK0_M2C_P
PG_C2M
FMC_HPC_D
1
Title
ASP-134486-01
D8
PIJ170D8
D5
PIJ170D5
D4
PIJ170D4
D1
PIJ170D1
D9
LA01_N_CC PIJ170D9
LA01_P_CC
GBTCLK0_M2C_N
GBTCLK0_M2C_P
PG_C2M
8
A
B
C
D
I
D
A30
PIJ170A30
A31
DP3_C2M_N PIJ170A31
DP3_C2M_P
DP2_C2M_N
DP2_C2M_P
DP9_C2M_P
GBTCLK1_M2C_N
B20
PIJ170B20
B17
B16
PIJ170B17
PIJ170B16
B13
PIJ170B13
B12
PIJ170B12
DP8_M2C_N
DP8_M2C_P
DP9_M2C_N
I
ASP-134486-01
A26
PIJ170A26
DP1_C2M_N
DP1_C2M_P
GBTCLK1_M2C_P
DP6_M2C_N
DP6_M2C_P
DP7_M2C_N
DP7_M2C_P
ni
v
DP0_C2M_N
Row D
COJ17D
J17D
7
~
A27
DP2_C2M_N PIJ170A27
DP2_C2M_P
PIJ170A23
A23
PIJ170A22
DP5_M2C_N
DP5_M2C_P
DP4_M2C_N
DP4_M2C_P
(
A22
PIJ170A19
A19
PIJ170A18
A18
PIJ170A15
A15
A14
PIJ170A14
DP3_M2C_N
B8
PIJ170B8
B9
DP8_M2C_N PIJ170B9
DP8_M2C_P
B5
PIJ170B5
C3
PIJ170C3
DP0_C2M_P
FMC_HPC_C
(
DP1_C2M_N
A11
PIJ170A11
DP3_M2C_P
DP2_M2C_N
DP9_M2C_N
DP0_C2M_N
DP0_C2M_P
C2
PIJ170C2
POROW0C0SDA0fmc0hpc0a0b0c0d1
POROW0C0SCL0fmc0hpc0a0b0c0d1
POROW0C0LA270fmc0hpc0a0b0c0d10P
POROW0C0LA270fmc0hpc0a0b0c0d10N
POROW0C0LA180P0CC0fmc0hpc0a0b0c0d1
POROW0C0LA180N0CC0fmc0hpc0a0b0c0d1
POROW0C0LA140fmc0hpc0a0b0c0d10P
POROW0C0LA140fmc0hpc0a0b0c0d10N
POROW0C0LA100fmc0hpc0a0b0c0d10P
POROW0C0LA100fmc0hpc0a0b0c0d10N
POROW0C0LA060fmc0hpc0a0b0c0d10P
POROW0C0LA060fmc0hpc0a0b0c0d10N
POROW0C0GA00fmc0hpc0a0b0c0d1
POROW0C0DP00M2C0fmc0hpc0a0b0c0d10P
POROW0C0DP00M2C0fmc0hpc0a0b0c0d10N
POROW0C0DP00C2M0fmc0hpc0a0b0c0d10P
POROW0C0DP00C2M0fmc0hpc0a0b0c0d10N
POROW0C012P0V020fmc0hpc0a0b0c0d1
POROW0C012P0V010fmc0hpc0a0b0c0d1
POROW0C03P3V010fmc0hpc0a0b0c0d1
POROW0C0fmc0hpc0a0b0c0d1
ROW_C
~
DP1_C2M_P
DP5_M2C_N
DP5_M2C_P
DP4_M2C_N
DP4_M2C_P
DP3_M2C_N
A10
DP3_M2C_P PIJ170A10
PIJ170A7
A7
I I !I! ! ! ! ! ! I! !
DP2_M2C_N
DP2_M2C_P
DP9_M2C_P
Row C
COJ17C
J17C
6
I
C
!! !!! !!
A6
PIJ170A6
B4
PIJ170B4
(
DP2_M2C_P
DP9_M2C_P
CLK_DIR
~
B
I
DP1_M2C_N
~
A3
U
FMC_HPC_B
-
PIJ170A3
CLK_DIR
B1
PIJ170B1
5
-
Row B
POROW0B0RES00fmc0hpc0a0b0c0d1
POROW0B0GBTCLK10M2C0fmc0hpc0a0b0c0d10P
POROW0B0GBTCLK10M2C0fmc0hpc0a0b0c0d10N
POROW0B0DP90M2C0fmc0hpc0a0b0c0d10P
POROW0B0DP90M2C0fmc0hpc0a0b0c0d10N
POROW0B0DP90C2M0fmc0hpc0a0b0c0d10P
POROW0B0DP90C2M0fmc0hpc0a0b0c0d10N
POROW0B0DP80M2C0fmc0hpc0a0b0c0d10P
POROW0B0DP80M2C0fmc0hpc0a0b0c0d10N
POROW0B0DP80C2M0fmc0hpc0a0b0c0d10P
POROW0B0DP80C2M0fmc0hpc0a0b0c0d10N
POROW0B0DP70M2C0fmc0hpc0a0b0c0d10P
POROW0B0DP70M2C0fmc0hpc0a0b0c0d10N
POROW0B0DP70C2M0fmc0hpc0a0b0c0d10P
POROW0B0DP70C2M0fmc0hpc0a0b0c0d10N
POROW0B0DP60M2C0fmc0hpc0a0b0c0d10P
POROW0B0DP60M2C0fmc0hpc0a0b0c0d10N
POROW0B0DP60C2M0fmc0hpc0a0b0c0d10P
POROW0B0DP60C2M0fmc0hpc0a0b0c0d10N
POROW0B0CLK0DIR0fmc0hpc0a0b0c0d1
POROW0B0fmc0hpc0a0b0c0d1
ROW_B
-
COJ17B
J17B
4
-
DP1_M2C_P
FMC_HPC_A
POROW0A0DP50M2C0fmc0hpc0a0b0c0d10P
POROW0A0DP50M2C0fmc0hpc0a0b0c0d10N
POROW0A0DP50C2M0fmc0hpc0a0b0c0d10P
POROW0A0DP50C2M0fmc0hpc0a0b0c0d10N
POROW0A0DP40M2C0fmc0hpc0a0b0c0d10P
POROW0A0DP40M2C0fmc0hpc0a0b0c0d10N
POROW0A0DP40C2M0fmc0hpc0a0b0c0d10P
POROW0A0DP40C2M0fmc0hpc0a0b0c0d10N
POROW0A0DP30M2C0fmc0hpc0a0b0c0d10P
POROW0A0DP30M2C0fmc0hpc0a0b0c0d10N
POROW0A0DP30C2M0fmc0hpc0a0b0c0d10P
POROW0A0DP30C2M0fmc0hpc0a0b0c0d10N
POROW0A0DP20M2C0fmc0hpc0a0b0c0d10P
POROW0A0DP20M2C0fmc0hpc0a0b0c0d10N
POROW0A0DP20C2M0fmc0hpc0a0b0c0d10P
POROW0A0DP20C2M0fmc0hpc0a0b0c0d10N
POROW0A0DP10M2C0fmc0hpc0a0b0c0d10P
POROW0A0DP10M2C0fmc0hpc0a0b0c0d10N
POROW0A0DP10C2M0fmc0hpc0a0b0c0d10P
POROW0A0DP10C2M0fmc0hpc0a0b0c0d10N
POROW0A0fmc0hpc0a0b0c0d1
ROW_A
3
(
DP1_M2C_N
DP1_M2C_P
-
A2
PIJ170A2
2
-
Row A
COJ17A
J17A
1
-
I
r-
r-
r-
r-
\
r-
f-
f-
A
I
A34
PIJ180A39
A39
PIJ180A38
A38
PIJ180A35
A35
PIJ180A34
DP5_C2M_N
DP5_C2M_P
DP4_C2M_N
DP4_C2M_P
I
141
1
DP5_C2M_N
DP5_C2M_P
DP4_C2M_N
DP4_C2M_P
DP3_C2M_N
DP3_C2M_P
\
2
ASP-134486-01
B25
PIJ180B25
B29
PIJ180B29
3
RES0
DP6_C2M_N
DP6_C2M_P
DP7_C2M_N
B40
PIJ180B40
B37
PIJ180B37
B36
PIJ180B36
B33
PIJ180B33
B32
DP7_C2M_P PIJ180B32
DP8_C2M_N
B28
DP8_C2M_P PIJ180B28
DP9_C2M_N
B24
PIJ180B24
B21
PIJ180B21
DP6_C2M_N
DP6_C2M_P
DP7_C2M_N
DP7_C2M_P
DP8_C2M_N
DP8_C2M_P
DP9_C2M_N
DP9_C2M_P
GBTCLK1_M2C_N
GBTCLK1_M2C_P
DP6_M2C_N
DP6_M2C_P
DP7_M2C_N
RES0
ty
4
I
er
si
DP7_M2C_P
of
LA27_P
LA18_N_CC
LA18_P_CC
LA14_N
LA14_P
LA10_N
LA10_P
LA06_N
ASP-134486-01
C26
PIJ180C26
C23
PIJ180C23
C22
PIJ180C22
C19
PIJ180C19
C18
C15
PIJ180C18
PIJ180C15
C14
PIJ180C14
C11
PIJ180C11
5
3P3V_1
12P0V_2
12P0V_1
GA0
w
n
3P3V_1
12P0V_2
12P0V_1
GA0
SDA
SCL
LA27_N
LA27_P
LA18_N_CC
LA18_P_CC
LA14_N
LA14_P
LA10_N
LA10_P
LA06_N
LA06_P
DP0_M2C_N
DP0_M2C_P
To
C39
PIJ180C39
C37
PIJ180C37
C35
PIJ180C35
C34
PIJ180C34
e
C30
PIJ180C30
C31
SDA PIJ180C31
SCL
C27
LA27_N PIJ180C27
ap
C
C7
PIJ180C7
C6
PIJ180C6
C10
LA06_P PIJ180C10
DP0_M2C_N
DP0_M2C_P
\
I
6
D24
PIJ180D24
D31
PIJ180D31
D30
PIJ180D30
D29
PIJ180D29
D27
PIJ180D27
D33
PIJ180D33
D35
PIJ180D40
D40
PIJ180D38
D38
PIJ180D36
D36
PIJ180D35
3P3V_4
3P3V_3
3P3V_2
GA1
TRST_L
TMS
3P3VAUX
TDO
TDI
TCK
LA26_N
LA26_P
LA23_N
LA23_P
r--
7
29/03/2011
C:\Users\..\fmc_hpc_a_b_c_d.SchDoc
RHINO
Number
Project
POROW0D0TRST0L0fmc0hpc0a0b0c0d2
POROW0D0TMS0fmc0hpc0a0b0c0d2
POROW0D0TDO0fmc0hpc0a0b0c0d2
POROW0D0TDI0fmc0hpc0a0b0c0d2
POROW0D0TCK0fmc0hpc0a0b0c0d2
POROW0D0PG0C2M0fmc0hpc0a0b0c0d2
POROW0D0LA260fmc0hpc0a0b0c0d20P
POROW0D0LA260fmc0hpc0a0b0c0d20N
POROW0D0LA230fmc0hpc0a0b0c0d20P
POROW0D0LA230fmc0hpc0a0b0c0d20N
POROW0D0LA170P0CC0fmc0hpc0a0b0c0d2
POROW0D0LA170N0CC0fmc0hpc0a0b0c0d2
POROW0D0LA130fmc0hpc0a0b0c0d20P
POROW0D0LA130fmc0hpc0a0b0c0d20N
POROW0D0LA090fmc0hpc0a0b0c0d20P
POROW0D0LA090fmc0hpc0a0b0c0d20N
POROW0D0LA050fmc0hpc0a0b0c0d20P
POROW0D0LA050fmc0hpc0a0b0c0d20N
POROW0D0LA010P0CC0fmc0hpc0a0b0c0d2
POROW0D0LA010N0CC0fmc0hpc0a0b0c0d2
POROW0D0GBTCLK00M2C0fmc0hpc0a0b0c0d20P
POROW0D0GBTCLK00M2C0fmc0hpc0a0b0c0d20N
POROW0D0GA10fmc0hpc0a0b0c0d2
POROW0D03P3VAUX0fmc0hpc0a0b0c0d2
POROW0D03P3V040fmc0hpc0a0b0c0d2
POROW0D03P3V030fmc0hpc0a0b0c0d2
POROW0D03P3V020fmc0hpc0a0b0c0d2
POROW0D0fmc0hpc0a0b0c0d2
ROW_D
Revision
1.0
8
Sheet 23 of 65
Drawn By:
Simon Scott
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
FMC HPC Connector (Rows A, B, C, D)
3P3V_4
3P3V_3
3P3V_2
GA1
D34
TRST_L PIJ180D34
TMS
D32
3P3VAUX PIJ180D32
TDO
TDI
TCK
LA26_N
D26
LA26_P PIJ180D26
LA23_N
LA17_N_CC
LA17_P_CC
LA13_N
LA13_P
LA09_N
r--
Date:
File:
A3
D21
PIJ180D21
D20
PIJ180D20
D18
PIJ180D18
D17
PIJ180D17
LA09_P
LA05_N
LA05_P
LA01_N_CC
\
Size
D14
D15
PIJ180D15
PIJ180D14
D12
PIJ180D12
D11
PIJ180D11
D23
LA23_P PIJ180D23
LA17_N_CC
LA17_P_CC
LA13_N
LA13_P
LA09_N
LA09_P
LA05_N
LA05_P
LA01_P_CC
GBTCLK0_M2C_N
GBTCLK0_M2C_P
PG_C2M
FMC_HPC_D
1
Title
ASP-134486-01
D8
PIJ180D8
D5
PIJ180D5
D4
PIJ180D4
D1
PIJ180D1
D9
LA01_N_CC PIJ180D9
LA01_P_CC
GBTCLK0_M2C_N
GBTCLK0_M2C_P
PG_C2M
8
A
B
C
D
I
D
A30
PIJ180A30
A31
DP3_C2M_N PIJ180A31
DP3_C2M_P
DP2_C2M_N
DP2_C2M_P
DP9_C2M_P
GBTCLK1_M2C_N
B20
PIJ180B20
B17
B16
PIJ180B17
PIJ180B16
B13
PIJ180B13
B12
PIJ180B12
DP8_M2C_N
DP8_M2C_P
DP9_M2C_N
I
ASP-134486-01
A26
PIJ180A26
DP1_C2M_N
DP1_C2M_P
GBTCLK1_M2C_P
DP6_M2C_N
DP6_M2C_P
DP7_M2C_N
DP7_M2C_P
ni
v
DP0_C2M_N
Row D
COJ18D
J18D
7
~
A27
DP2_C2M_N PIJ180A27
DP2_C2M_P
PIJ180A23
A23
PIJ180A22
DP5_M2C_N
DP5_M2C_P
DP4_M2C_N
DP4_M2C_P
(
A22
PIJ180A19
A19
PIJ180A18
A18
PIJ180A15
A15
A14
PIJ180A14
DP3_M2C_N
B8
PIJ180B8
B9
DP8_M2C_N PIJ180B9
DP8_M2C_P
B5
PIJ180B5
C3
PIJ180C3
DP0_C2M_P
FMC_HPC_C
(
DP1_C2M_N
A11
PIJ180A11
DP3_M2C_P
DP2_M2C_N
DP9_M2C_N
DP0_C2M_N
DP0_C2M_P
C2
PIJ180C2
POROW0C0SDA0fmc0hpc0a0b0c0d2
POROW0C0SCL0fmc0hpc0a0b0c0d2
POROW0C0LA270fmc0hpc0a0b0c0d20P
POROW0C0LA270fmc0hpc0a0b0c0d20N
POROW0C0LA180P0CC0fmc0hpc0a0b0c0d2
POROW0C0LA180N0CC0fmc0hpc0a0b0c0d2
POROW0C0LA140fmc0hpc0a0b0c0d20P
POROW0C0LA140fmc0hpc0a0b0c0d20N
POROW0C0LA100fmc0hpc0a0b0c0d20P
POROW0C0LA100fmc0hpc0a0b0c0d20N
POROW0C0LA060fmc0hpc0a0b0c0d20P
POROW0C0LA060fmc0hpc0a0b0c0d20N
POROW0C0GA00fmc0hpc0a0b0c0d2
POROW0C0DP00M2C0fmc0hpc0a0b0c0d20P
POROW0C0DP00M2C0fmc0hpc0a0b0c0d20N
POROW0C0DP00C2M0fmc0hpc0a0b0c0d20P
POROW0C0DP00C2M0fmc0hpc0a0b0c0d20N
POROW0C012P0V020fmc0hpc0a0b0c0d2
POROW0C012P0V010fmc0hpc0a0b0c0d2
POROW0C03P3V010fmc0hpc0a0b0c0d2
POROW0C0fmc0hpc0a0b0c0d2
ROW_C
~
DP1_C2M_P
DP5_M2C_N
DP5_M2C_P
DP4_M2C_N
DP4_M2C_P
DP3_M2C_N
A10
DP3_M2C_P PIJ180A10
PIJ180A7
A7
I I !I! ! ! ! ! ! I! !
DP2_M2C_N
DP2_M2C_P
DP9_M2C_P
Row C
COJ18C
J18C
6
I
C
!! !!! !!
A6
PIJ180A6
B4
PIJ180B4
(
DP2_M2C_P
DP9_M2C_P
CLK_DIR
~
B
I
DP1_M2C_N
~
A3
U
FMC_HPC_B
-
PIJ180A3
CLK_DIR
B1
PIJ180B1
5
-
Row B
POROW0B0RES00fmc0hpc0a0b0c0d2
POROW0B0GBTCLK10M2C0fmc0hpc0a0b0c0d20P
POROW0B0GBTCLK10M2C0fmc0hpc0a0b0c0d20N
POROW0B0DP90M2C0fmc0hpc0a0b0c0d20P
POROW0B0DP90M2C0fmc0hpc0a0b0c0d20N
POROW0B0DP90C2M0fmc0hpc0a0b0c0d20P
POROW0B0DP90C2M0fmc0hpc0a0b0c0d20N
POROW0B0DP80M2C0fmc0hpc0a0b0c0d20P
POROW0B0DP80M2C0fmc0hpc0a0b0c0d20N
POROW0B0DP80C2M0fmc0hpc0a0b0c0d20P
POROW0B0DP80C2M0fmc0hpc0a0b0c0d20N
POROW0B0DP70M2C0fmc0hpc0a0b0c0d20P
POROW0B0DP70M2C0fmc0hpc0a0b0c0d20N
POROW0B0DP70C2M0fmc0hpc0a0b0c0d20P
POROW0B0DP70C2M0fmc0hpc0a0b0c0d20N
POROW0B0DP60M2C0fmc0hpc0a0b0c0d20P
POROW0B0DP60M2C0fmc0hpc0a0b0c0d20N
POROW0B0DP60C2M0fmc0hpc0a0b0c0d20P
POROW0B0DP60C2M0fmc0hpc0a0b0c0d20N
POROW0B0CLK0DIR0fmc0hpc0a0b0c0d2
POROW0B0fmc0hpc0a0b0c0d2
ROW_B
-
COJ18B
J18B
4
-
DP1_M2C_P
FMC_HPC_A
POROW0A0DP50M2C0fmc0hpc0a0b0c0d20P
POROW0A0DP50M2C0fmc0hpc0a0b0c0d20N
POROW0A0DP50C2M0fmc0hpc0a0b0c0d20P
POROW0A0DP50C2M0fmc0hpc0a0b0c0d20N
POROW0A0DP40M2C0fmc0hpc0a0b0c0d20P
POROW0A0DP40M2C0fmc0hpc0a0b0c0d20N
POROW0A0DP40C2M0fmc0hpc0a0b0c0d20P
POROW0A0DP40C2M0fmc0hpc0a0b0c0d20N
POROW0A0DP30M2C0fmc0hpc0a0b0c0d20P
POROW0A0DP30M2C0fmc0hpc0a0b0c0d20N
POROW0A0DP30C2M0fmc0hpc0a0b0c0d20P
POROW0A0DP30C2M0fmc0hpc0a0b0c0d20N
POROW0A0DP20M2C0fmc0hpc0a0b0c0d20P
POROW0A0DP20M2C0fmc0hpc0a0b0c0d20N
POROW0A0DP20C2M0fmc0hpc0a0b0c0d20P
POROW0A0DP20C2M0fmc0hpc0a0b0c0d20N
POROW0A0DP10M2C0fmc0hpc0a0b0c0d20P
POROW0A0DP10M2C0fmc0hpc0a0b0c0d20N
POROW0A0DP10C2M0fmc0hpc0a0b0c0d20P
POROW0A0DP10C2M0fmc0hpc0a0b0c0d20N
POROW0A0fmc0hpc0a0b0c0d2
ROW_A
3
(
DP1_M2C_N
DP1_M2C_P
-
A2
PIJ180A2
2
-
Row A
COJ18A
J18A
1
-
I
r-
r-
r-
r-
\
r-
f-
f-
A
I
142
E30
PIJ170E34
E34
PIJ170E33
E33
PIJ170E31
E31
PIJ170E30
E37
PIJ170E37
E39
VADJ_1 PIJ170E39
HB21_N
E36
HB21_P PIJ170E36
HB19_N
HB19_P
HB13_N
HB13_P
VADJ_1
HB21_N
HB21_P
HB19_N
HB19_P
HB13_N
HB13_P
HB09_N
HB09_P
2
ASP-134486-01
F23
PIJ170F23
F22
PIJ170F22
F20
PIJ170F20
F19
PIJ170F19
F17
F16
PIJ170F17
PIJ170F16
F14
PIJ170F14
F13
PIJ170F13
F26
PIJ170F26
F34
PIJ170F34
F32
PIJ170F32
F31
PIJ170F31
F29
PIJ170F29
F37
PIJ170F37
1
3
VADJ_2
F40
PIJ170F40
F38
HB20_N PIJ170F38
HB20_P
F35
HB16_N PIJ170F35
HB16_P
HB12_N
HB12_P
HB08_N
F28
HB08_P PIJ170F28
HB04_N
F25
HB04_P PIJ170F25
HB02_N
HB02_P
HA19_N
HA19_P
HA15_N
HA15_P
HA12_N
HA12_P
ty
er
si
VADJ_2
HB20_N
HB20_P
HB16_N
HB16_P
HB12_N
HB12_P
HB08_N
HB08_P
HB04_N
HB04_P
HB02_N
HB02_P
HA19_N
HA19_P
HA15_N
HA15_P
HA12_N
HA12_P
HA08_N
HA08_P
4
I
1
E27
PIJ170E27
E28
HB09_N PIJ170E28
HB09_P
HB05_N
HB05_P
HB03_N
HB03_P
HA20_N
HA20_P
HA16_N
HA16_P
HA13_N
F10
PIJ170F10
HA04_N
HA04_P
HA00_N_CC
ni
v
F8
PIJ170F8
F7
PIJ170F7
F11
HA08_N PIJ170F11
HA08_P
HA04_N
HA04_P
F5
PIJ170F5
HA00_P_CC
of
ASP-134486-01
G10
PIJ170G10
G9
PIJ170G9
G7
PIJ170G7
G6
PIJ170G6
G3
PIJ170G3
G2
PIJ170G2
LA22_P
LA20_N
LA20_P
LA16_N
LA16_P
LA12_N
LA12_P
LA08_N
G37
PIJ170G37
5
G39
VADJ_3 PIJ170G39
LA33_N
w
n
VADJ_3
LA33_N
LA33_P
LA31_N
LA31_P
LA29_N
LA29_P
LA25_N
LA25_P
LA22_N
LA22_P
LA20_N
LA20_P
LA16_N
LA16_P
LA12_N
LA12_P
LA08_N
LA08_P
LA03_N
LA03_P
LA00_N_CC
LA00_P_CC
CLK1_M2C_N
CLK1_M2C_P
To
G34
PIJ170G34
G33
PIJ170G33
G31
PIJ170G31
G30
PIJ170G30
G36
LA33_P PIJ170G36
LA31_N
LA31_P
LA29_N
LA29_P
e
G27
PIJ170G27
G28
LA25_N PIJ170G28
LA25_P
G25
LA22_N PIJ170G25
G24
PIJ170G24
G22
PIJ170G22
G21
PIJ170G21
G19
PIJ170G19
G18
G16
PIJ170G18
PIJ170G16
G15
PIJ170G15
G13
PIJ170G13
G12
LA08_P PIJ170G12
LA03_N
LA03_P
LA00_N_CC
LA00_P_CC
CLK1_M2C_N
CLK1_M2C_P
ap
C
Row G
6
6
I
-
I
H25
PIJ170H25
H32
PIJ170H32
H31
PIJ170H31
H29
PIJ170H29
H28
PIJ170H28
H35
PIJ170H35
H40
PIJ170H40
H38
PIJ170H38
VADJ_4
LA32_N
LA32_P
LA30_N
LA30_P
LA28_N
LA28_P
LA24_N
LA24_P
LA21_N
LA21_P
LA19_N
8
r--
7
29/03/2011
C:\Users\..\fmc_hpc_e_f_g_h.SchDoc
RHINO
Number
Project
Revision
1.0
POROW0H0VREF0A0M2C0fmc0hpc0e0f0g0h1
POROW0H0VADJ040fmc0hpc0e0f0g0h1
POROW0H0PRSNT0M2C0L0fmc0hpc0e0f0g0h1
POROW0H0LA320fmc0hpc0e0f0g0h10P
POROW0H0LA320fmc0hpc0e0f0g0h10N
POROW0H0LA300fmc0hpc0e0f0g0h10P
POROW0H0LA300fmc0hpc0e0f0g0h10N
POROW0H0LA280fmc0hpc0e0f0g0h10P
POROW0H0LA280fmc0hpc0e0f0g0h10N
POROW0H0LA240fmc0hpc0e0f0g0h10P
POROW0H0LA240fmc0hpc0e0f0g0h10N
POROW0H0LA210fmc0hpc0e0f0g0h10P
POROW0H0LA210fmc0hpc0e0f0g0h10N
POROW0H0LA190fmc0hpc0e0f0g0h10P
POROW0H0LA190fmc0hpc0e0f0g0h10N
POROW0H0LA150fmc0hpc0e0f0g0h10P
POROW0H0LA150fmc0hpc0e0f0g0h10N
POROW0H0LA110fmc0hpc0e0f0g0h10P
POROW0H0LA110fmc0hpc0e0f0g0h10N
POROW0H0LA070fmc0hpc0e0f0g0h10P
POROW0H0LA070fmc0hpc0e0f0g0h10N
POROW0H0LA040fmc0hpc0e0f0g0h10P
POROW0H0LA040fmc0hpc0e0f0g0h10N
POROW0H0LA020fmc0hpc0e0f0g0h10P
POROW0H0LA020fmc0hpc0e0f0g0h10N
POROW0H0CLK00M2C0fmc0hpc0e0f0g0h10P
POROW0H0CLK00M2C0fmc0hpc0e0f0g0h10N
POROW0H0fmc0hpc0e0f0g0h1
ROW_H
8
Sheet 24 of 65
Drawn By:
Simon Scott
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
FMC HPC Connector (Rows E, F, G, H)
VADJ_4
LA32_N
H37
LA32_P PIJ170H37
LA30_N
H34
LA30_P PIJ170H34
LA28_N
LA28_P
LA24_N
LA24_P
H26
LA21_N PIJ170H26
LA21_P
LA19_P
LA15_N
LA15_P
LA11_N
LA11_P
LA07_N
LA07_P
LA04_N
LA04_P
r--
Date:
File:
A3
H22
PIJ170H22
H20
PIJ170H20
H19
PIJ170H19
H17
PIJ170H17
H16
H14
PIJ170H16
PIJ170H14
H13
PIJ170H13
H11
PIJ170H11
H23
LA19_N PIJ170H23
LA19_P
LA15_N
LA15_P
LA11_N
LA11_P
LA07_N
LA07_P
LA04_N
LA02_N
LA02_P
CLK0_M2C_N
CLK0_M2C_P
PRSNT_M2C_L
VREF_A_M2C
FMC_HPC_H
1
Size
Title
H8
PIJ170H8
H7
PIJ170H7
H5
PIJ170H5
H4
PIJ170H4
H2
PIJ170H2
H1
PIJ170H1
H10
LA04_P PIJ170H10
LA02_N
LA02_P
CLK0_M2C_N
CLK0_M2C_P
PRSNT_M2C_L
VREF_A_M2C
ASP-134486-01
Row H
COJ17H
J17H
POROW0G0VADJ030fmc0hpc0e0f0g0h1
POROW0G0LA330fmc0hpc0e0f0g0h10P
POROW0G0LA330fmc0hpc0e0f0g0h10N
POROW0G0LA310fmc0hpc0e0f0g0h10P
POROW0G0LA310fmc0hpc0e0f0g0h10N
POROW0G0LA290fmc0hpc0e0f0g0h10P
POROW0G0LA290fmc0hpc0e0f0g0h10N
POROW0G0LA250fmc0hpc0e0f0g0h10P
POROW0G0LA250fmc0hpc0e0f0g0h10N
POROW0G0LA220fmc0hpc0e0f0g0h10P
POROW0G0LA220fmc0hpc0e0f0g0h10N
POROW0G0LA200fmc0hpc0e0f0g0h10P
POROW0G0LA200fmc0hpc0e0f0g0h10N
POROW0G0LA160fmc0hpc0e0f0g0h10P
POROW0G0LA160fmc0hpc0e0f0g0h10N
POROW0G0LA120fmc0hpc0e0f0g0h10P
POROW0G0LA120fmc0hpc0e0f0g0h10N
POROW0G0LA080fmc0hpc0e0f0g0h10P
POROW0G0LA080fmc0hpc0e0f0g0h10N
POROW0G0LA030fmc0hpc0e0f0g0h10P
POROW0G0LA030fmc0hpc0e0f0g0h10N
POROW0G0LA000P0CC0fmc0hpc0e0f0g0h1
POROW0G0LA000N0CC0fmc0hpc0e0f0g0h1
POROW0G0CLK10M2C0fmc0hpc0e0f0g0h10P
POROW0G0CLK10M2C0fmc0hpc0e0f0g0h10N
POROW0G0fmc0hpc0e0f0g0h1
ROW_G
7
A
B
C
D
I
D
E24
PIJ170E24
PIJ170E22
E22
PIJ170E21
E21
PIJ170E19
E19
PIJ170E18
E18
PIJ170E16
E16
E15
PIJ170E15
E25
HB05_N PIJ170E25
HB05_P
HB03_N
E13
PIJ170E13
(
HB03_P
HA20_N
HA20_P
HA16_N
HA16_P
HA13_N
HA13_P
HA09_N
HA09_P
U
HA00_N_CC
F4
PIJ170F4
PG_M2C
FMC_HPC_G
(
ASP-134486-01
PIJ170E10
E10
E9
PIJ170E9
HA05_N
HA05_P
HA00_P_CC
F1
PIJ170F1
COJ17G
J17G
POROW0F0VADJ020fmc0hpc0e0f0g0h1
POROW0F0PG0M2C0fmc0hpc0e0f0g0h1
POROW0F0HB200fmc0hpc0e0f0g0h10P
POROW0F0HB200fmc0hpc0e0f0g0h10N
POROW0F0HB160fmc0hpc0e0f0g0h10P
POROW0F0HB160fmc0hpc0e0f0g0h10N
POROW0F0HB120fmc0hpc0e0f0g0h10P
POROW0F0HB120fmc0hpc0e0f0g0h10N
POROW0F0HB080fmc0hpc0e0f0g0h10P
POROW0F0HB080fmc0hpc0e0f0g0h10N
POROW0F0HB040fmc0hpc0e0f0g0h10P
POROW0F0HB040fmc0hpc0e0f0g0h10N
POROW0F0HB020fmc0hpc0e0f0g0h10P
POROW0F0HB020fmc0hpc0e0f0g0h10N
POROW0F0HA190fmc0hpc0e0f0g0h10P
POROW0F0HA190fmc0hpc0e0f0g0h10N
POROW0F0HA150fmc0hpc0e0f0g0h10P
POROW0F0HA150fmc0hpc0e0f0g0h10N
POROW0F0HA120fmc0hpc0e0f0g0h10P
POROW0F0HA120fmc0hpc0e0f0g0h10N
POROW0F0HA080fmc0hpc0e0f0g0h10P
POROW0F0HA080fmc0hpc0e0f0g0h10N
POROW0F0HA040fmc0hpc0e0f0g0h10P
POROW0F0HA040fmc0hpc0e0f0g0h10N
POROW0F0HA000P0CC0fmc0hpc0e0f0g0h1
POROW0F0HA000N0CC0fmc0hpc0e0f0g0h1
POROW0F0fmc0hpc0e0f0g0h1
ROW_F
5
I
C
E7
PIJ170E7
E12
HA13_P PIJ170E12
HA09_N
HA09_P
HA05_N
E6
PIJ170E6
HA01_N
PG_M2C
(
B
I
HA05_P
E3
Row F
FMC_HPC_F
-
HA01_P
COJ17F
J17F
4
-
PIJ170E3
E2
PIJ170E2
-
POROW0E0VADJ010fmc0hpc0e0f0g0h1
POROW0E0HB210fmc0hpc0e0f0g0h10P
POROW0E0HB210fmc0hpc0e0f0g0h10N
POROW0E0HB190fmc0hpc0e0f0g0h10P
POROW0E0HB190fmc0hpc0e0f0g0h10N
POROW0E0HB130fmc0hpc0e0f0g0h10P
POROW0E0HB130fmc0hpc0e0f0g0h10N
POROW0E0HB090fmc0hpc0e0f0g0h10P
POROW0E0HB090fmc0hpc0e0f0g0h10N
POROW0E0HB050fmc0hpc0e0f0g0h10P
POROW0E0HB050fmc0hpc0e0f0g0h10N
POROW0E0HB030fmc0hpc0e0f0g0h10P
POROW0E0HB030fmc0hpc0e0f0g0h10N
POROW0E0HA200fmc0hpc0e0f0g0h10P
POROW0E0HA200fmc0hpc0e0f0g0h10N
POROW0E0HA160fmc0hpc0e0f0g0h10P
POROW0E0HA160fmc0hpc0e0f0g0h10N
POROW0E0HA130fmc0hpc0e0f0g0h10P
POROW0E0HA130fmc0hpc0e0f0g0h10N
POROW0E0HA090fmc0hpc0e0f0g0h10P
POROW0E0HA090fmc0hpc0e0f0g0h10N
POROW0E0HA050fmc0hpc0e0f0g0h10P
POROW0E0HA050fmc0hpc0e0f0g0h10N
POROW0E0HA010fmc0hpc0e0f0g0h10P
POROW0E0HA010fmc0hpc0e0f0g0h10N
POROW0E0fmc0hpc0e0f0g0h1
ROW_E
3
-
HA01_N_CC
HA01_P_CC
FMC_HPC_E
2
-
Row E
COJ17E
J17E
1
-
I
r-
r-
r-
r-
\
r-
f-
\
f-
A
I
143
E30
PIJ180E34
E34
PIJ180E33
E33
PIJ180E31
E31
PIJ180E30
E37
PIJ180E37
E39
VADJ_1 PIJ180E39
HB21_N
E36
HB21_P PIJ180E36
HB19_N
HB19_P
HB13_N
HB13_P
VADJ_1
HB21_N
HB21_P
HB19_N
HB19_P
HB13_N
HB13_P
HB09_N
HB09_P
2
ASP-134486-01
F23
PIJ180F23
F22
PIJ180F22
F20
PIJ180F20
F19
PIJ180F19
F17
F16
PIJ180F17
PIJ180F16
F14
PIJ180F14
F13
PIJ180F13
F26
PIJ180F26
F34
PIJ180F34
F32
PIJ180F32
F31
PIJ180F31
F29
PIJ180F29
F37
PIJ180F37
1
3
VADJ_2
F40
PIJ180F40
F38
HB20_N PIJ180F38
HB20_P
F35
HB16_N PIJ180F35
HB16_P
HB12_N
HB12_P
HB08_N
F28
HB08_P PIJ180F28
HB04_N
F25
HB04_P PIJ180F25
HB02_N
HB02_P
HA19_N
HA19_P
HA15_N
HA15_P
HA12_N
HA12_P
ty
er
si
VADJ_2
HB20_N
HB20_P
HB16_N
HB16_P
HB12_N
HB12_P
HB08_N
HB08_P
HB04_N
HB04_P
HB02_N
HB02_P
HA19_N
HA19_P
HA15_N
HA15_P
HA12_N
HA12_P
HA08_N
HA08_P
4
I
1
E27
PIJ180E27
E28
HB09_N PIJ180E28
HB09_P
HB05_N
HB05_P
HB03_N
HB03_P
HA20_N
HA20_P
HA16_N
HA16_P
HA13_N
F10
PIJ180F10
HA04_N
HA04_P
HA00_N_CC
ni
v
F8
PIJ180F8
F7
PIJ180F7
F11
HA08_N PIJ180F11
HA08_P
HA04_N
HA04_P
F5
PIJ180F5
HA00_P_CC
of
ASP-134486-01
G10
PIJ180G10
G9
PIJ180G9
G7
PIJ180G7
G6
PIJ180G6
G3
PIJ180G3
G2
PIJ180G2
LA22_P
LA20_N
LA20_P
LA16_N
LA16_P
LA12_N
LA12_P
LA08_N
G37
PIJ180G37
5
G39
VADJ_3 PIJ180G39
LA33_N
w
n
VADJ_3
LA33_N
LA33_P
LA31_N
LA31_P
LA29_N
LA29_P
LA25_N
LA25_P
LA22_N
LA22_P
LA20_N
LA20_P
LA16_N
LA16_P
LA12_N
LA12_P
LA08_N
LA08_P
LA03_N
LA03_P
LA00_N_CC
LA00_P_CC
CLK1_M2C_N
CLK1_M2C_P
To
G34
PIJ180G34
G33
PIJ180G33
G31
PIJ180G31
G30
PIJ180G30
G36
LA33_P PIJ180G36
LA31_N
LA31_P
LA29_N
LA29_P
e
G27
PIJ180G27
G28
LA25_N PIJ180G28
LA25_P
G25
LA22_N PIJ180G25
G24
PIJ180G24
G22
PIJ180G22
G21
PIJ180G21
G19
PIJ180G19
G18
G16
PIJ180G18
PIJ180G16
G15
PIJ180G15
G13
PIJ180G13
G12
LA08_P PIJ180G12
LA03_N
LA03_P
LA00_N_CC
LA00_P_CC
CLK1_M2C_N
CLK1_M2C_P
ap
C
Row G
6
6
I
-
I
H25
PIJ180H25
H32
PIJ180H32
H31
PIJ180H31
H29
PIJ180H29
H28
PIJ180H28
H35
PIJ180H35
H40
PIJ180H40
H38
PIJ180H38
VADJ_4
LA32_N
LA32_P
LA30_N
LA30_P
LA28_N
LA28_P
LA24_N
LA24_P
LA21_N
LA21_P
LA19_N
8
r--
7
29/03/2011
C:\Users\..\fmc_hpc_e_f_g_h.SchDoc
RHINO
Number
Project
Revision
1.0
POROW0H0VREF0A0M2C0fmc0hpc0e0f0g0h2
POROW0H0VADJ040fmc0hpc0e0f0g0h2
POROW0H0PRSNT0M2C0L0fmc0hpc0e0f0g0h2
POROW0H0LA320fmc0hpc0e0f0g0h20P
POROW0H0LA320fmc0hpc0e0f0g0h20N
POROW0H0LA300fmc0hpc0e0f0g0h20P
POROW0H0LA300fmc0hpc0e0f0g0h20N
POROW0H0LA280fmc0hpc0e0f0g0h20P
POROW0H0LA280fmc0hpc0e0f0g0h20N
POROW0H0LA240fmc0hpc0e0f0g0h20P
POROW0H0LA240fmc0hpc0e0f0g0h20N
POROW0H0LA210fmc0hpc0e0f0g0h20P
POROW0H0LA210fmc0hpc0e0f0g0h20N
POROW0H0LA190fmc0hpc0e0f0g0h20P
POROW0H0LA190fmc0hpc0e0f0g0h20N
POROW0H0LA150fmc0hpc0e0f0g0h20P
POROW0H0LA150fmc0hpc0e0f0g0h20N
POROW0H0LA110fmc0hpc0e0f0g0h20P
POROW0H0LA110fmc0hpc0e0f0g0h20N
POROW0H0LA070fmc0hpc0e0f0g0h20P
POROW0H0LA070fmc0hpc0e0f0g0h20N
POROW0H0LA040fmc0hpc0e0f0g0h20P
POROW0H0LA040fmc0hpc0e0f0g0h20N
POROW0H0LA020fmc0hpc0e0f0g0h20P
POROW0H0LA020fmc0hpc0e0f0g0h20N
POROW0H0CLK00M2C0fmc0hpc0e0f0g0h20P
POROW0H0CLK00M2C0fmc0hpc0e0f0g0h20N
POROW0H0fmc0hpc0e0f0g0h2
ROW_H
8
Sheet 25 of 65
Drawn By:
Simon Scott
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
FMC HPC Connector (Rows E, F, G, H)
VADJ_4
LA32_N
H37
LA32_P PIJ180H37
LA30_N
H34
LA30_P PIJ180H34
LA28_N
LA28_P
LA24_N
LA24_P
H26
LA21_N PIJ180H26
LA21_P
LA19_P
LA15_N
LA15_P
LA11_N
LA11_P
LA07_N
LA07_P
LA04_N
LA04_P
r--
Date:
File:
A3
H22
PIJ180H22
H20
PIJ180H20
H19
PIJ180H19
H17
PIJ180H17
H16
H14
PIJ180H16
PIJ180H14
H13
PIJ180H13
H11
PIJ180H11
H23
LA19_N PIJ180H23
LA19_P
LA15_N
LA15_P
LA11_N
LA11_P
LA07_N
LA07_P
LA04_N
LA02_N
LA02_P
CLK0_M2C_N
CLK0_M2C_P
PRSNT_M2C_L
VREF_A_M2C
FMC_HPC_H
1
Size
Title
H8
PIJ180H8
H7
PIJ180H7
H5
PIJ180H5
H4
PIJ180H4
H2
PIJ180H2
H1
PIJ180H1
H10
LA04_P PIJ180H10
LA02_N
LA02_P
CLK0_M2C_N
CLK0_M2C_P
PRSNT_M2C_L
VREF_A_M2C
ASP-134486-01
Row H
COJ18H
J18H
POROW0G0VADJ030fmc0hpc0e0f0g0h2
POROW0G0LA330fmc0hpc0e0f0g0h20P
POROW0G0LA330fmc0hpc0e0f0g0h20N
POROW0G0LA310fmc0hpc0e0f0g0h20P
POROW0G0LA310fmc0hpc0e0f0g0h20N
POROW0G0LA290fmc0hpc0e0f0g0h20P
POROW0G0LA290fmc0hpc0e0f0g0h20N
POROW0G0LA250fmc0hpc0e0f0g0h20P
POROW0G0LA250fmc0hpc0e0f0g0h20N
POROW0G0LA220fmc0hpc0e0f0g0h20P
POROW0G0LA220fmc0hpc0e0f0g0h20N
POROW0G0LA200fmc0hpc0e0f0g0h20P
POROW0G0LA200fmc0hpc0e0f0g0h20N
POROW0G0LA160fmc0hpc0e0f0g0h20P
POROW0G0LA160fmc0hpc0e0f0g0h20N
POROW0G0LA120fmc0hpc0e0f0g0h20P
POROW0G0LA120fmc0hpc0e0f0g0h20N
POROW0G0LA080fmc0hpc0e0f0g0h20P
POROW0G0LA080fmc0hpc0e0f0g0h20N
POROW0G0LA030fmc0hpc0e0f0g0h20P
POROW0G0LA030fmc0hpc0e0f0g0h20N
POROW0G0LA000P0CC0fmc0hpc0e0f0g0h2
POROW0G0LA000N0CC0fmc0hpc0e0f0g0h2
POROW0G0CLK10M2C0fmc0hpc0e0f0g0h20P
POROW0G0CLK10M2C0fmc0hpc0e0f0g0h20N
POROW0G0fmc0hpc0e0f0g0h2
ROW_G
7
A
B
C
D
I
D
E24
PIJ180E24
PIJ180E22
E22
PIJ180E21
E21
PIJ180E19
E19
PIJ180E18
E18
PIJ180E16
E16
E15
PIJ180E15
E25
HB05_N PIJ180E25
HB05_P
HB03_N
E13
PIJ180E13
(
HB03_P
HA20_N
HA20_P
HA16_N
HA16_P
HA13_N
HA13_P
HA09_N
HA09_P
U
HA00_N_CC
F4
PIJ180F4
PG_M2C
FMC_HPC_G
(
ASP-134486-01
PIJ180E10
E10
E9
PIJ180E9
HA05_N
HA05_P
HA00_P_CC
F1
PIJ180F1
COJ18G
J18G
POROW0F0VADJ020fmc0hpc0e0f0g0h2
POROW0F0PG0M2C0fmc0hpc0e0f0g0h2
POROW0F0HB200fmc0hpc0e0f0g0h20P
POROW0F0HB200fmc0hpc0e0f0g0h20N
POROW0F0HB160fmc0hpc0e0f0g0h20P
POROW0F0HB160fmc0hpc0e0f0g0h20N
POROW0F0HB120fmc0hpc0e0f0g0h20P
POROW0F0HB120fmc0hpc0e0f0g0h20N
POROW0F0HB080fmc0hpc0e0f0g0h20P
POROW0F0HB080fmc0hpc0e0f0g0h20N
POROW0F0HB040fmc0hpc0e0f0g0h20P
POROW0F0HB040fmc0hpc0e0f0g0h20N
POROW0F0HB020fmc0hpc0e0f0g0h20P
POROW0F0HB020fmc0hpc0e0f0g0h20N
POROW0F0HA190fmc0hpc0e0f0g0h20P
POROW0F0HA190fmc0hpc0e0f0g0h20N
POROW0F0HA150fmc0hpc0e0f0g0h20P
POROW0F0HA150fmc0hpc0e0f0g0h20N
POROW0F0HA120fmc0hpc0e0f0g0h20P
POROW0F0HA120fmc0hpc0e0f0g0h20N
POROW0F0HA080fmc0hpc0e0f0g0h20P
POROW0F0HA080fmc0hpc0e0f0g0h20N
POROW0F0HA040fmc0hpc0e0f0g0h20P
POROW0F0HA040fmc0hpc0e0f0g0h20N
POROW0F0HA000P0CC0fmc0hpc0e0f0g0h2
POROW0F0HA000N0CC0fmc0hpc0e0f0g0h2
POROW0F0fmc0hpc0e0f0g0h2
ROW_F
5
I
C
E7
PIJ180E7
E12
HA13_P PIJ180E12
HA09_N
HA09_P
HA05_N
E6
PIJ180E6
HA01_N
PG_M2C
(
B
I
HA05_P
E3
Row F
FMC_HPC_F
-
HA01_P
COJ18F
J18F
4
-
PIJ180E3
E2
PIJ180E2
-
POROW0E0VADJ010fmc0hpc0e0f0g0h2
POROW0E0HB210fmc0hpc0e0f0g0h20P
POROW0E0HB210fmc0hpc0e0f0g0h20N
POROW0E0HB190fmc0hpc0e0f0g0h20P
POROW0E0HB190fmc0hpc0e0f0g0h20N
POROW0E0HB130fmc0hpc0e0f0g0h20P
POROW0E0HB130fmc0hpc0e0f0g0h20N
POROW0E0HB090fmc0hpc0e0f0g0h20P
POROW0E0HB090fmc0hpc0e0f0g0h20N
POROW0E0HB050fmc0hpc0e0f0g0h20P
POROW0E0HB050fmc0hpc0e0f0g0h20N
POROW0E0HB030fmc0hpc0e0f0g0h20P
POROW0E0HB030fmc0hpc0e0f0g0h20N
POROW0E0HA200fmc0hpc0e0f0g0h20P
POROW0E0HA200fmc0hpc0e0f0g0h20N
POROW0E0HA160fmc0hpc0e0f0g0h20P
POROW0E0HA160fmc0hpc0e0f0g0h20N
POROW0E0HA130fmc0hpc0e0f0g0h20P
POROW0E0HA130fmc0hpc0e0f0g0h20N
POROW0E0HA090fmc0hpc0e0f0g0h20P
POROW0E0HA090fmc0hpc0e0f0g0h20N
POROW0E0HA050fmc0hpc0e0f0g0h20P
POROW0E0HA050fmc0hpc0e0f0g0h20N
POROW0E0HA010fmc0hpc0e0f0g0h20P
POROW0E0HA010fmc0hpc0e0f0g0h20N
POROW0E0fmc0hpc0e0f0g0h2
ROW_E
3
-
HA01_N_CC
HA01_P_CC
FMC_HPC_E
2
-
Row E
COJ18E
J18E
1
-
I
r-
r-
r-
r-
\
r-
f-
\
f-
I
HA22_P
J24
J31
PIJ170J31
J34
PIJ170J39
J39
J37
PIJ170J37
PIJ170J36
J36
PIJ170J34
VIO_B_M2C_1
HB18_N
HB18_P
HB15_N
144
I
2
HB14_P
HB17_N_CC
HB17_P_CC
HB14_N
3
VIO_B_M2C_2
ASP-134486-01
K31
PIJ170K31
PIJ170K40
K40
K38
PIJ170K38
K37
PIJ170K37
K35
K34
PIJ170K35
PIJ170K34
K32
HB10_N PIJ170K32
HB10_P
K29
K28
PIJ170K28
K26
PIJ170K26
K25
PIJ170K25
K23
PIJ170K23
HB06_N_CC PIJ170K29
HB06_P_CC
HB00_N_CC
HB00_P_CC
HA23_N
VIO_B_M2C_2
HB17_N_CC
HB17_P_CC
HB14_N
HB14_P
HB10_N
HB10_P
HB06_N_CC
HB06_P_CC
HB00_N_CC
HB00_P_CC
HA23_N
HA23_P
HA21_N
,
4
of
GND_24
PIJ170B7
B7
GND_26
GND_27
GND_28
GND_29
B11
PIJ170B11
B14
PIJ170B14
B15
PIJ170B15
B18
PIJ170B18
GND_30
GND_31
GND_32
B22
PIJ170B22
B23
PIJ170B23
e
B19
PIJ170B19
GND_34
5
Row C GND
w
n
C32
C28
PIJ170C28
C29
PIJ170C29
PIJ170C32
C33
PIJ170C33
C36
PIJ170C36
C38
PIJ170C38
C13
C9
PIJ170C9
C12
PIJ170C12
PIJ170C13
C16
PIJ170C16
C17
PIJ170C17
C20
PIJ170C20
C21
PIJ170C21
C24
PIJ170C24
D22
PIJ170D22
D25
PIJ170D25
D28
PIJ170D28
D37
PIJ170D37
D39
C1
PIJ170D39
PIJ170C1
C4
PIJ170C4
C5
PIJ170C5
D16
PIJ170D16
6
D2
D3
PIJ170D3
D6
PIJ170D6
D7
PIJ170D7
D10
PIJ170D10
GND_61 PIJ170D2
GND_62
GND_63
GND_64
GND_65
D13
GND_66 PIJ170D13
GND_67
D19
GND_68 PIJ170D19
GND_69
GND_70
GND_71
GND_72
GND_73
GND_41
GND_42
GND_43
C8
GND_44 PIJ170C8
GND_45
GND_46
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
C25
GND_53 PIJ170C25
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
C40
GND_60 PIJ170C40
I"
GND
I"
GND
GND_40
GND_39
GND_38
GND_37
GND_36
ASP-134486-01
B39
PIJ170B39
PIJ170B38
B38
B35
PIJ170B35
PIJ170B34
B34
B31
PIJ170B31
PIJ170B30 GND_35
B30
B27
PIJ170B27
PIJ170B26 GND_33
B26
Row A GND
To
GND_25
B10
PIJ170B10
ap
C
GND_23
!
VIO_B_M2C_1
HB18_N
HB18_P
HB15_P
HB11_N
HB11_P
HB07_N
HB07_P
HB01_N
HB01_P
K20
PIJ170K20
K22
HA23_P PIJ170K22
HA21_N
HA21_P
HA17_N_CC
HA17_P_CC
GND_22
B6
PIJ170B6
GND_21
GND_20
GND_19
GND_18
PIJ170B3
B3
B2
PIJ170B2
A40
PIJ170A40
A37
PIJ170A37
A36
PIJ170A36
!
HB15_N
J33
HB15_P PIJ170J33
HB11_N
J30
PIJ170J28
J28
PIJ170J27
J27
J25
PIJ170J25
PIJ170J24
HB11_P PIJ170J30
HB07_N
HB07_P
HB01_N
HB01_P
HA22_N
HA22_P
K17
PIJ170K17
K19
HA21_P PIJ170K19
HA17_N_CC
K16
PIJ170K16
HA10_N
HA10_P
HA06_N
HA06_P
HA02_N
ty
er
si
HA02_P
!
F2
-
,I"
-
GND_113
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_104
Row H GND
Row E GND
H21
PIJ170H21
H36
J1
J5
PIJ170J5
J4
PIJ170J4
PIJ170J1
H39
PIJ170H39
PIJ170H36
H33
PIJ170H33
H30
H27
PIJ170H30
PIJ170H27
J32
J29
PIJ170J32
PIJ170J29
J26
J23
PIJ170J26
PIJ170J23
J20
J17
PIJ170J20
PIJ170J17
J14
PIJ170J14
J11
PIJ170J11
J38
PIJ170J38
K15
PIJ170K15
K36
PIJ170K36
K33
PIJ170K33
K30
K27
PIJ170K30
PIJ170K27
K24
K21
PIJ170K24
PIJ170K21
K39
GND_159 PIJ170K39
GND_158
GND_157
GND_156
GND_155
GND_154
GND_153
K18
GND_152 PIJ170K18
GND_151
K12
K9
PIJ170K9
K6
K3
PIJ170K6
PIJ170K3
K2
PIJ170K2
GND_150 PIJ170K12
GND_149
GND_148
GND_147
GND_146
J40
GND_145 PIJ170J40
GND_144
J35
GND_143 PIJ170J35
GND_142
GND_141
GND_140
GND_139
GND_138
GND_137
GND_136
GND_135
J8
GND_134 PIJ170J8
GND_133
GND_132
GND_131
GND_130
GND_129
GND_128
GND_127
GND_126
GND
r-
7
29/03/2011
C:\Users\..\fmc_hpc_j_k_gnd.SchDoc
RHINO
Number
Project
Revision
1.0
8
Sheet 26 of 65
Drawn By:
Simon Scott
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
FMC HPC Connector (Rows J, K and Ground)
ASP-134486-01
PIJ170G1 GND_103
G1
PIJ170G4
G4
PIJ170G5 GND_105
G5
PIJ170G8
G8
G11
PIJ170G11
PIJ170G14
G14
G17
PIJ170G17
PIJ170G20
G20
G23
PIJ170G23
H15
H18
PIJ170H18
PIJ170H15
r-
Date:
File:
A3
Size
GND_115
GND_116
GND_117
GND_89
PIJ170G26 GND_112
G26
G29
PIJ170G29
1111
Title
GND_91
PIJ170G32 GND_114
G32
G35
PIJ170G35
G38
PIJ170G38
G40
PIJ170G40
PIJ170F2
F3
F6
PIJ170F3 GND_90
PIJ170F6
H9
H12
PIJ170H12
PIJ170H9
H6
PIJ170H6
H24
GND_125 PIJ170H24
GND_124
GND_123
GND_122
GND_121
GND_120
GND_119
H3
GND_118 PIJ170H3
8
I''I',
GND
GND_93
GND_94
GND_95
GND_96
GND_97
GND_98
GND_99
PIJ170F9 GND_92
F9
F12
PIJ170F12
F15
PIJ170F15
F18
PIJ170F18
F21
PIJ170F21
F24
PIJ170F24
F27
PIJ170F27
F30
PIJ170F30
GND_100
GND_101
F33
PIJ170F33
GND_102
F36
PIJ170F36
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87
GND_88
GND_80
GND_79
GND_78
GND_77
GND_76
GND_75
F39
PIJ170F39
E20
PIJ170E20
E23
PIJ170E23
E26
PIJ170E26
E29
PIJ170E29
E32
PIJ170E32
E35
PIJ170E35
E38
PIJ170E38
E40
PIJ170E40
E17
PIJ170E17
E14
PIJ170E14
E11
PIJ170E11
E8
PIJ170E8
E5
PIJ170E5
E4
PIJ170E4
E1
PIJ170E1
GND_74
COJ17K
J17K
7
!!
1
J21
PIJ170J21
J22
HA22_N PIJ170J22
HA18_N
HA18_P
HA17_P_CC
K14
PIJ170K14
K13
PIJ170K13
K11
K10
PIJ170K11
PIJ170K10
K8
PIJ170K8
K7
PIJ170K7
!
A
B
C
D
I
D
J18
PIJ170J18
HA14_N
HA10_N
HA10_P
HA06_N
HA06_P
HA02_N
HA02_P
GND_17
-
ASP-134486-01
J16
PIJ170J16
HA14_P
HA11_N
HA11_P
HA07_N
HA07_P
HA03_N
GND_16
A33
PIJ170A33
GND_15
GND_14
GND_13
GND_12
GND_11
GND_10
GND_9
GND_8
GND_7
GND_6
GND_5
GND_4
GND_3
GND_2
A32
PIJ170A32
A29
PIJ170A29
A28
PIJ170A28
!
J19
HA18_N PIJ170J19
HA18_P
HA14_N
PIJ170J15
J15
PIJ170J13
J13
PIJ170J12
J12
PIJ170J10
J10
J9
PIJ170J9
CLK2_BIDIR_N
CLK2_BIDIR_P
VREF_B_M2C
!
HA14_P
HA11_N
HA11_P
J7
PIJ170J7
K4
PIJ170K4
K5
CLK2_BIDIR_N PIJ170K5
CLK2_BIDIR_P
FMC_HPC_K
ni
v
K1
PIJ170K1
A25
PIJ170A25
A24
PIJ170A24
A21
PIJ170A21
A20
PIJ170A20
A17
PIJ170A17
A16
PIJ170A16
A13
PIJ170A13
!
HA07_N
HA07_P
HA03_N
HA03_P
CLK3_BIDIR_N
VREF_B_M2C
A9
A12
PIJ170A12
PIJ170A9
A8
PIJ170A8
PIJ170A5
A5
A4
PIJ170A4
6
I
C
J3
PIJ170J3
Row K
COJ17J
J17J
POROW0K0VREF0B0M2C0fmc0hpc0j0k0gnd1
POROW0K0VIO0B0M2C020fmc0hpc0j0k0gnd1
POROW0K0HB170P0CC0fmc0hpc0j0k0gnd1
POROW0K0HB170N0CC0fmc0hpc0j0k0gnd1
POROW0K0HB140fmc0hpc0j0k0gnd10P
POROW0K0HB140fmc0hpc0j0k0gnd10N
POROW0K0HB100fmc0hpc0j0k0gnd10P
POROW0K0HB100fmc0hpc0j0k0gnd10N
POROW0K0HB060P0CC0fmc0hpc0j0k0gnd1
POROW0K0HB060N0CC0fmc0hpc0j0k0gnd1
POROW0K0HB000P0CC0fmc0hpc0j0k0gnd1
POROW0K0HB000N0CC0fmc0hpc0j0k0gnd1
POROW0K0HA230fmc0hpc0j0k0gnd10P
POROW0K0HA230fmc0hpc0j0k0gnd10N
POROW0K0HA210fmc0hpc0j0k0gnd10P
POROW0K0HA210fmc0hpc0j0k0gnd10N
POROW0K0HA170P0CC0fmc0hpc0j0k0gnd1
POROW0K0HA170N0CC0fmc0hpc0j0k0gnd1
POROW0K0HA100fmc0hpc0j0k0gnd10P
POROW0K0HA100fmc0hpc0j0k0gnd10N
POROW0K0HA060fmc0hpc0j0k0gnd10P
POROW0K0HA060fmc0hpc0j0k0gnd10N
POROW0K0HA020fmc0hpc0j0k0gnd10P
POROW0K0HA020fmc0hpc0j0k0gnd10N
POROW0K0CLK20BIDIR0fmc0hpc0j0k0gnd10P
POROW0K0CLK20BIDIR0fmc0hpc0j0k0gnd10N
POROW0K0fmc0hpc0j0k0gnd1
ROW_K
COJ17L
J17L
5
A1
PIJ170A1
GND_1
!
J6
HA03_P PIJ170J6
CLK3_BIDIR_P
FMC_HPC_J
U
4
r
CLK3_BIDIR_N
CLK3_BIDIR_P
J2
PIJ170J2
POROW0J0VIO0B0M2C010fmc0hpc0j0k0gnd1
POROW0J0HB180fmc0hpc0j0k0gnd10P
POROW0J0HB180fmc0hpc0j0k0gnd10N
POROW0J0HB150fmc0hpc0j0k0gnd10P
POROW0J0HB150fmc0hpc0j0k0gnd10N
POROW0J0HB110fmc0hpc0j0k0gnd10P
POROW0J0HB110fmc0hpc0j0k0gnd10N
POROW0J0HB070fmc0hpc0j0k0gnd10P
POROW0J0HB070fmc0hpc0j0k0gnd10N
POROW0J0HB010fmc0hpc0j0k0gnd10P
POROW0J0HB010fmc0hpc0j0k0gnd10N
POROW0J0HA220fmc0hpc0j0k0gnd10P
POROW0J0HA220fmc0hpc0j0k0gnd10N
POROW0J0HA180fmc0hpc0j0k0gnd10P
POROW0J0HA180fmc0hpc0j0k0gnd10N
POROW0J0HA140fmc0hpc0j0k0gnd10P
POROW0J0HA140fmc0hpc0j0k0gnd10N
POROW0J0HA110fmc0hpc0j0k0gnd10P
POROW0J0HA110fmc0hpc0j0k0gnd10N
POROW0J0HA070fmc0hpc0j0k0gnd10P
POROW0J0HA070fmc0hpc0j0k0gnd10N
POROW0J0HA030fmc0hpc0j0k0gnd10P
POROW0J0HA030fmc0hpc0j0k0gnd10N
POROW0J0CLK30BIDIR0fmc0hpc0j0k0gnd10P
POROW0J0CLK30BIDIR0fmc0hpc0j0k0gnd10N
POROW0J0fmc0hpc0j0k0gnd1
ROW_J
3
I!!!!!!!!!!!!
Row J
COJ17I
J17I
2
I!!!!!!!!!!!!
B
I
Row B GND
-
Row D GND
-
Row F GND
-
Row J GND
A
1
1111111111111
Row K GND
I!!!!!!!!!!!!
Row G GND
-
I
r-
r-
r-
r-
r-
f-
I
f-
I
HA22_P
J24
J31
PIJ180J31
J34
PIJ180J39
J39
J37
PIJ180J37
PIJ180J36
J36
PIJ180J34
VIO_B_M2C_1
HB18_N
HB18_P
HB15_N
145
I
2
HB14_P
HB17_N_CC
HB17_P_CC
HB14_N
3
VIO_B_M2C_2
ASP-134486-01
K31
PIJ180K31
PIJ180K40
K40
K38
PIJ180K38
K37
PIJ180K37
K35
K34
PIJ180K35
PIJ180K34
K32
HB10_N PIJ180K32
HB10_P
K29
K28
PIJ180K28
K26
PIJ180K26
K25
PIJ180K25
K23
PIJ180K23
HB06_N_CC PIJ180K29
HB06_P_CC
HB00_N_CC
HB00_P_CC
HA23_N
VIO_B_M2C_2
HB17_N_CC
HB17_P_CC
HB14_N
HB14_P
HB10_N
HB10_P
HB06_N_CC
HB06_P_CC
HB00_N_CC
HB00_P_CC
HA23_N
HA23_P
HA21_N
,
4
of
GND_24
PIJ180B7
B7
GND_26
GND_27
GND_28
GND_29
B11
PIJ180B11
B14
PIJ180B14
B15
PIJ180B15
B18
PIJ180B18
GND_30
GND_31
GND_32
B22
PIJ180B22
B23
PIJ180B23
e
B19
PIJ180B19
GND_34
5
Row C GND
w
n
C32
C28
PIJ180C28
C29
PIJ180C29
PIJ180C32
C33
PIJ180C33
C36
PIJ180C36
C38
PIJ180C38
C13
C9
PIJ180C9
C12
PIJ180C12
PIJ180C13
C16
PIJ180C16
C17
PIJ180C17
C20
PIJ180C20
C21
PIJ180C21
C24
PIJ180C24
D22
PIJ180D22
D25
PIJ180D25
D28
PIJ180D28
D37
PIJ180D37
D39
C1
PIJ180D39
PIJ180C1
C4
PIJ180C4
C5
PIJ180C5
D16
PIJ180D16
6
D2
D3
PIJ180D3
D6
PIJ180D6
D7
PIJ180D7
D10
PIJ180D10
GND_61 PIJ180D2
GND_62
GND_63
GND_64
GND_65
D13
GND_66 PIJ180D13
GND_67
D19
GND_68 PIJ180D19
GND_69
GND_70
GND_71
GND_72
GND_73
GND_41
GND_42
GND_43
C8
GND_44 PIJ180C8
GND_45
GND_46
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
C25
GND_53 PIJ180C25
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
C40
GND_60 PIJ180C40
I"
GND
I"
GND
GND_40
GND_39
GND_38
GND_37
GND_36
ASP-134486-01
B39
PIJ180B39
PIJ180B38
B38
B35
PIJ180B35
PIJ180B34
B34
B31
PIJ180B31
PIJ180B30 GND_35
B30
B27
PIJ180B27
PIJ180B26 GND_33
B26
Row A GND
To
GND_25
B10
PIJ180B10
ap
C
GND_23
!
VIO_B_M2C_1
HB18_N
HB18_P
HB15_P
HB11_N
HB11_P
HB07_N
HB07_P
HB01_N
HB01_P
K20
PIJ180K20
K22
HA23_P PIJ180K22
HA21_N
HA21_P
HA17_N_CC
HA17_P_CC
GND_22
B6
PIJ180B6
GND_21
GND_20
GND_19
GND_18
PIJ180B3
B3
B2
PIJ180B2
A40
PIJ180A40
A37
PIJ180A37
A36
PIJ180A36
!
HB15_N
J33
HB15_P PIJ180J33
HB11_N
J30
PIJ180J28
J28
PIJ180J27
J27
J25
PIJ180J25
PIJ180J24
HB11_P PIJ180J30
HB07_N
HB07_P
HB01_N
HB01_P
HA22_N
HA22_P
K17
PIJ180K17
K19
HA21_P PIJ180K19
HA17_N_CC
K16
PIJ180K16
HA10_N
HA10_P
HA06_N
HA06_P
HA02_N
ty
er
si
HA02_P
!
F2
-
,I"
-
GND_113
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_104
Row H GND
Row E GND
H21
PIJ180H21
H36
J1
J5
PIJ180J5
J4
PIJ180J4
PIJ180J1
H39
PIJ180H39
PIJ180H36
H33
PIJ180H33
H30
H27
PIJ180H30
PIJ180H27
J32
J29
PIJ180J32
PIJ180J29
J26
J23
PIJ180J26
PIJ180J23
J20
J17
PIJ180J20
PIJ180J17
J14
PIJ180J14
J11
PIJ180J11
J38
PIJ180J38
K15
PIJ180K15
K36
PIJ180K36
K33
PIJ180K33
K30
K27
PIJ180K30
PIJ180K27
K24
K21
PIJ180K24
PIJ180K21
K39
GND_159 PIJ180K39
GND_158
GND_157
GND_156
GND_155
GND_154
GND_153
K18
GND_152 PIJ180K18
GND_151
K12
K9
PIJ180K9
K6
K3
PIJ180K6
PIJ180K3
K2
PIJ180K2
GND_150 PIJ180K12
GND_149
GND_148
GND_147
GND_146
J40
GND_145 PIJ180J40
GND_144
J35
GND_143 PIJ180J35
GND_142
GND_141
GND_140
GND_139
GND_138
GND_137
GND_136
GND_135
J8
GND_134 PIJ180J8
GND_133
GND_132
GND_131
GND_130
GND_129
GND_128
GND_127
GND_126
GND
r-
7
29/03/2011
C:\Users\..\fmc_hpc_j_k_gnd.SchDoc
RHINO
Number
Project
Revision
1.0
8
Sheet 27 of 65
Drawn By:
Simon Scott
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
FMC HPC Connector (Rows J, K and Ground)
ASP-134486-01
PIJ180G1 GND_103
G1
PIJ180G4
G4
PIJ180G5 GND_105
G5
PIJ180G8
G8
G11
PIJ180G11
PIJ180G14
G14
G17
PIJ180G17
PIJ180G20
G20
G23
PIJ180G23
H15
H18
PIJ180H18
PIJ180H15
r-
Date:
File:
A3
Size
GND_115
GND_116
GND_117
GND_89
PIJ180G26 GND_112
G26
G29
PIJ180G29
1111
Title
GND_91
PIJ180G32 GND_114
G32
G35
PIJ180G35
G38
PIJ180G38
G40
PIJ180G40
PIJ180F2
F3
F6
PIJ180F3 GND_90
PIJ180F6
H9
H12
PIJ180H12
PIJ180H9
H6
PIJ180H6
H24
GND_125 PIJ180H24
GND_124
GND_123
GND_122
GND_121
GND_120
GND_119
H3
GND_118 PIJ180H3
8
I''I',
GND
GND_93
GND_94
GND_95
GND_96
GND_97
GND_98
GND_99
PIJ180F9 GND_92
F9
F12
PIJ180F12
F15
PIJ180F15
F18
PIJ180F18
F21
PIJ180F21
F24
PIJ180F24
F27
PIJ180F27
F30
PIJ180F30
GND_100
GND_101
F33
PIJ180F33
GND_102
F36
PIJ180F36
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87
GND_88
GND_80
GND_79
GND_78
GND_77
GND_76
GND_75
F39
PIJ180F39
E20
PIJ180E20
E23
PIJ180E23
E26
PIJ180E26
E29
PIJ180E29
E32
PIJ180E32
E35
PIJ180E35
E38
PIJ180E38
E40
PIJ180E40
E17
PIJ180E17
E14
PIJ180E14
E11
PIJ180E11
E8
PIJ180E8
E5
PIJ180E5
E4
PIJ180E4
E1
PIJ180E1
GND_74
COJ18K
J18K
7
!!
1
J21
PIJ180J21
J22
HA22_N PIJ180J22
HA18_N
HA18_P
HA17_P_CC
K14
PIJ180K14
K13
PIJ180K13
K11
K10
PIJ180K11
PIJ180K10
K8
PIJ180K8
K7
PIJ180K7
!
A
B
C
D
I
D
J18
PIJ180J18
HA14_N
HA10_N
HA10_P
HA06_N
HA06_P
HA02_N
HA02_P
GND_17
-
ASP-134486-01
J16
PIJ180J16
HA14_P
HA11_N
HA11_P
HA07_N
HA07_P
HA03_N
GND_16
A33
PIJ180A33
GND_15
GND_14
GND_13
GND_12
GND_11
GND_10
GND_9
GND_8
GND_7
GND_6
GND_5
GND_4
GND_3
GND_2
A32
PIJ180A32
A29
PIJ180A29
A28
PIJ180A28
!
J19
HA18_N PIJ180J19
HA18_P
HA14_N
PIJ180J15
J15
PIJ180J13
J13
PIJ180J12
J12
PIJ180J10
J10
J9
PIJ180J9
CLK2_BIDIR_N
CLK2_BIDIR_P
VREF_B_M2C
!
HA14_P
HA11_N
HA11_P
J7
PIJ180J7
K4
PIJ180K4
K5
CLK2_BIDIR_N PIJ180K5
CLK2_BIDIR_P
FMC_HPC_K
ni
v
K1
PIJ180K1
A25
PIJ180A25
A24
PIJ180A24
A21
PIJ180A21
A20
PIJ180A20
A17
PIJ180A17
A16
PIJ180A16
A13
PIJ180A13
!
HA07_N
HA07_P
HA03_N
HA03_P
CLK3_BIDIR_N
VREF_B_M2C
A9
A12
PIJ180A12
PIJ180A9
A8
PIJ180A8
PIJ180A5
A5
A4
PIJ180A4
6
I
C
J3
PIJ180J3
Row K
COJ18J
J18J
POROW0K0VREF0B0M2C0fmc0hpc0j0k0gnd2
POROW0K0VIO0B0M2C020fmc0hpc0j0k0gnd2
POROW0K0HB170P0CC0fmc0hpc0j0k0gnd2
POROW0K0HB170N0CC0fmc0hpc0j0k0gnd2
POROW0K0HB140fmc0hpc0j0k0gnd20P
POROW0K0HB140fmc0hpc0j0k0gnd20N
POROW0K0HB100fmc0hpc0j0k0gnd20P
POROW0K0HB100fmc0hpc0j0k0gnd20N
POROW0K0HB060P0CC0fmc0hpc0j0k0gnd2
POROW0K0HB060N0CC0fmc0hpc0j0k0gnd2
POROW0K0HB000P0CC0fmc0hpc0j0k0gnd2
POROW0K0HB000N0CC0fmc0hpc0j0k0gnd2
POROW0K0HA230fmc0hpc0j0k0gnd20P
POROW0K0HA230fmc0hpc0j0k0gnd20N
POROW0K0HA210fmc0hpc0j0k0gnd20P
POROW0K0HA210fmc0hpc0j0k0gnd20N
POROW0K0HA170P0CC0fmc0hpc0j0k0gnd2
POROW0K0HA170N0CC0fmc0hpc0j0k0gnd2
POROW0K0HA100fmc0hpc0j0k0gnd20P
POROW0K0HA100fmc0hpc0j0k0gnd20N
POROW0K0HA060fmc0hpc0j0k0gnd20P
POROW0K0HA060fmc0hpc0j0k0gnd20N
POROW0K0HA020fmc0hpc0j0k0gnd20P
POROW0K0HA020fmc0hpc0j0k0gnd20N
POROW0K0CLK20BIDIR0fmc0hpc0j0k0gnd20P
POROW0K0CLK20BIDIR0fmc0hpc0j0k0gnd20N
POROW0K0fmc0hpc0j0k0gnd2
ROW_K
COJ18L
J18L
5
A1
PIJ180A1
GND_1
!
J6
HA03_P PIJ180J6
CLK3_BIDIR_P
FMC_HPC_J
U
4
r
CLK3_BIDIR_N
CLK3_BIDIR_P
J2
PIJ180J2
POROW0J0VIO0B0M2C010fmc0hpc0j0k0gnd2
POROW0J0HB180fmc0hpc0j0k0gnd20P
POROW0J0HB180fmc0hpc0j0k0gnd20N
POROW0J0HB150fmc0hpc0j0k0gnd20P
POROW0J0HB150fmc0hpc0j0k0gnd20N
POROW0J0HB110fmc0hpc0j0k0gnd20P
POROW0J0HB110fmc0hpc0j0k0gnd20N
POROW0J0HB070fmc0hpc0j0k0gnd20P
POROW0J0HB070fmc0hpc0j0k0gnd20N
POROW0J0HB010fmc0hpc0j0k0gnd20P
POROW0J0HB010fmc0hpc0j0k0gnd20N
POROW0J0HA220fmc0hpc0j0k0gnd20P
POROW0J0HA220fmc0hpc0j0k0gnd20N
POROW0J0HA180fmc0hpc0j0k0gnd20P
POROW0J0HA180fmc0hpc0j0k0gnd20N
POROW0J0HA140fmc0hpc0j0k0gnd20P
POROW0J0HA140fmc0hpc0j0k0gnd20N
POROW0J0HA110fmc0hpc0j0k0gnd20P
POROW0J0HA110fmc0hpc0j0k0gnd20N
POROW0J0HA070fmc0hpc0j0k0gnd20P
POROW0J0HA070fmc0hpc0j0k0gnd20N
POROW0J0HA030fmc0hpc0j0k0gnd20P
POROW0J0HA030fmc0hpc0j0k0gnd20N
POROW0J0CLK30BIDIR0fmc0hpc0j0k0gnd20P
POROW0J0CLK30BIDIR0fmc0hpc0j0k0gnd20N
POROW0J0fmc0hpc0j0k0gnd2
ROW_J
3
I!!!!!!!!!!!!
Row J
COJ18I
J18I
2
I!!!!!!!!!!!!
B
I
Row B GND
-
Row D GND
-
Row F GND
-
Row J GND
A
1
1111111111111
Row K GND
I!!!!!!!!!!!!
Row G GND
-
I
r-
r-
r-
r-
r-
f-
I
f-
L
1
I
TYPE_SENSE
1
PIU6304
GND
2OUT
1OUT
PIU6307
GND
2
GND
3
of
GND
B
Y
VCC
4
PIU6504
5
PIU6505
R327
120R
PIC43802
PIC43801
PIR32701
GND
47k
PIR46902
R469
COR5
PIR46901
PIC5620
PIC56201
VIN
VIN
ON
GND
3
PIU640C1
4
-III'
"
146
C442
10u
-
29/03/2011
C:\Users\..\cx4.SchDoc
RHINO
Number
Project
4
Sheet 28 of
Drawn By:
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
CX4 10Gbps Ethernet Connector
PIR3201
R332
100R
D44
GRN
1.1
65
Simon Scott
Revision
-
Date:
File:
A4
Size
Title
C441
10n
OPTICAL_VCC
PID4 02 COD2
OPTICAL
PWR
P
I
D
4
0
1
PIC4 102
PIC4 20
COC4
COC5
PIR320 COR6
PIC4 10
PIC4 201
_- H
I r--~
PIU640B1
A1
B1
PIU640A1
1.) Place the 2 LEDs next to the CX4 connector
2.) Place the text "FAULT" and "PWR" next to the respective LEDs, on the silkscreen
3.) Route the TX and RX lines as differential pairs, with 50 ohms single ended impedance
and 100 ohms differential impedance
Layout Notes:
VOUT
VOUT
111'
GND
C562
COC11
4u7
TPS22924C
PIU640C2
PIU640B2
C2
GND
w
n
COU2
U64
PIU640A2
A2
B2
To
VCC_3V3_FPGA
e
10n
COC1
C438
C440
COC3
100n
GND
PIC4 0 2
PIC4 0 1
COD1OPTICAL
D43
RED FAULT
PIR3270 COR1
PID4301
ap
C
VCC_3V3_FPGA
SN74AHC1G08DBVR
PIU6503
2
PIU6502
A
COU3
U65
GND
1
PIU6501
C439
COC2
100n
GND
PIC43902
PIC43901
1
PIU6301
7
PIJ150M2
COC7
COC10
PIC209 2 C209
PIC21402 COC8
C214 PIC21502 COC9
C215 PIC21602 C216
PIC209 1 1n PIC21401 100n PIC21501 1n PIC21601 100n
T ~III'
GND
+
-
+
-
PIU6308
PIJ150M
ty
"1
TLV3702QDRQ1
PIU6306
2IN+
2IN-
3
PIU6303 1IN+
2
PIU6302 1IN-
PIU6305
FCN-268D008-G/1D
VCC_3V3_FPGA
COU1
U63
UL
5
6
S15
S16
PIJ150S16
OPTICAL_VCC
TYPE_SENSE
GND
PID4302
OPTICAL_VCC
11
PIR3 01
R333
3k9
TX3+
TX3-
PIJ150S15
G9
PIJ150G9
G8
PIJ150G8
er
si
SIG_GND
VCC/SIG_GND
G7
PIJ150G7
9,
PIR3 0 1
PIR3 02COR7
TX2+
TX2-
S13
S14
PIJ150S14
PIJ150S13
TX1+
TX1-
ni
v
TYP_SEN/SIG_GND
G6
PIJ150G6
G5
PIJ150G5
G4
PIJ150G4
G3
PIJ150G3
G2
PIJ150G2
G1
PIJ150G1
3
~
10n
C443
COC6
R330
6k8
PIR3 0 2COR4
PIR32901
3k9
S11
S12
PIJ150S12
PIJ150S11
TX0+
TX0-
SIG_GND
SIG_GND
SIG_GND
FAULT/SIG_GND
r1H II'
PIC4 302
PIC4 301
PIR32801
R329
COR3
S10
PIJ150S10
S9
PIJ150S9
U
SIG_GND
ODIS/SIG_GND
2
B
A
C
D
I
D
J
4k7
I
R328
COR2
PIR32902
TX3_P
TX3_N
TX2_P
TX2_N
:'
:
--,- ---H 2:
~-1
PIR3280
TX1_P
TX1_N
TX0_P
TX0_N
RX2+
RX2-
S7
RX3+
S8
PIJ150S8 RX3-
PIJ150S7
S5
PIJ150S5
S6
PIJ150S6
S3
RX1+
S4
PIJ150S4 RX1-
PIJ150S3
--(- - -(-
C
TX3_P
TX3_N
-- -1- ___ -
TX2_P
TX2_N
TX1_P
TX1_N
TX0_P
TX0_N
RX3_P
RX3_N
RX2_P
RX2_N
RX1_P
RX1_N
~-
VCC_3V3_FPGA
POCX40BUS0TX30cx4000P
POCX40BUS0TX30cx4000N
POCX40BUS0TX20cx4000P
POCX40BUS0TX20cx4000N
POCX40BUS0TX10cx4000P
POCX40BUS0TX10cx4000N
POCX40BUS0TX00cx4000P
POCX40BUS0TX00cx4000N
POCX40BUS0RX30cx4000P
POCX40BUS0RX30cx4000N
POCX40BUS0RX20cx4000P
POCX40BUS0RX20cx4000N
POCX40BUS0RX10cx4000P
POCX40BUS0RX10cx4000N
POCX40BUS0RX00cx4000P
POCX40BUS0RX00cx4000N
POCX40BUS0cx400
CX4_BUS
RX3_P
RX3_N
RX2_P
RX2_N
RX1_P
RX1_N
RX0_P
RX0_N
COJ1
J15
S1
PIJ150S1 RX0+
S2
PIJ150S2 RX0-
~
B
A
RX0_P
RX0_N
.-'- +~--- - --~-~-
OJ, ---
VCC
MGT_BUS
100R_DIFF
i
r-~ ~ -~-- -~ ~ -j-\
~~II'
8
I
~~II'
GND
1
~
,,
~
l
JiH II'
Tt
4
11
11 1'
M1
II'
"II
M2
"
~
I
C1
1
T
c-
:
L
1
I
TYPE_SENSE
1
PIU604
GND
2OUT
1OUT
PIU6607
GND
2
GND
3
of
GND
B
Y
VCC
4
PIU6804
5
PIU6805
R334
120R
PIC4 02
PIC4 01
PIR3401
GND
47k
PIR47002
R470
COR5
PIR47001
PIC56302
PIC56301
VIN
VIN
ON
GND
3
PIU670C1
4
-III'
"
147
C448
10u
-
29/03/2011
C:\Users\..\cx4.SchDoc
RHINO
Number
Project
4
Sheet 29 of
Drawn By:
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
CX4 10Gbps Ethernet Connector
PIR3901
R339
100R
D46
GRN
1.1
65
Simon Scott
Revision
-
Date:
File:
A4
Size
Title
C447
10n
OPTICAL_VCC
PID4602 COD2
OPTICAL
PWR
P
I
D
4
6
0
1
PIC4 702
PIC4 802
COC4
COC5
PIR3902 COR6
PIC4 701
PIC4 801
_- H
I r--~
PIU670B1
A1
B1
PIU670A1
1.) Place the 2 LEDs next to the CX4 connector
2.) Place the text "FAULT" and "PWR" next to the respective LEDs, on the silkscreen
3.) Route the TX and RX lines as differential pairs, with 50 ohms single ended impedance
and 100 ohms differential impedance
Layout Notes:
VOUT
VOUT
111'
GND
C563
COC11
4u7
TPS22924C
PIU670C2
PIU670B2
C2
GND
w
n
COU2
U67
PIU670A2
A2
B2
To
VCC_3V3_FPGA
e
10n
COC1
C444
C446
COC3
100n
GND
PIC4 602
PIC4 601
COD1OPTICAL
D45
RED FAULT
PIR3402 COR1
PID4501
ap
C
VCC_3V3_FPGA
SN74AHC1G08DBVR
PIU6803
2
PIU6802
A
COU3
U68
GND
1
PIU6801
C445
COC2
100n
GND
PIC4 502
PIC4 501
1
PIU6601
7
PIJ160M2
COC7
COC10
PIC21702 C217
PIC21802 COC8
C218 PIC21902 COC9
C219 PIC2 0 2 C220
PIC21701 1n PIC21801 100n PIC21901 1n PIC2 0 1 100n
T ~III'
GND
+
-
+
-
PIU608
PIJ160M
ty
"1
TLV3702QDRQ1
PIU6606
2IN+
2IN-
3
PIU6603 1IN+
2
PIU6602 1IN-
PIU6605
FCN-268D008-G/1D
VCC_3V3_FPGA
COU1
U66
UL
5
6
S15
S16
PIJ160S16
OPTICAL_VCC
TYPE_SENSE
GND
PID4502
OPTICAL_VCC
11
PIR340 1
R340
3k9
TX3+
TX3-
PIJ160S15
G9
PIJ160G9
G8
PIJ160G8
er
si
SIG_GND
VCC/SIG_GND
G7
PIJ160G7
9,
PIR3 701
PIR340 2COR7
TX2+
TX2-
S13
S14
PIJ160S14
PIJ160S13
TX1+
TX1-
ni
v
TYP_SEN/SIG_GND
G6
PIJ160G6
G5
PIJ160G5
G4
PIJ160G4
G3
PIJ160G3
G2
PIJ160G2
G1
PIJ160G1
3
~
10n
C449
COC6
R337
6k8
PIR3 702COR4
PIR3 601
3k9
S11
S12
PIJ160S12
PIJ160S11
TX0+
TX0-
SIG_GND
SIG_GND
SIG_GND
FAULT/SIG_GND
r1H II'
PIC4 902
PIC4 901
PIR3501
R336
COR3
S10
PIJ160S10
S9
PIJ160S9
U
SIG_GND
ODIS/SIG_GND
2
B
A
C
D
I
D
J
4k7
I
R335
COR2
PIR3 602
TX3_P
TX3_N
TX2_P
TX2_N
:'
:
--,- ---H 2:
~-1
PIR3502
TX1_P
TX1_N
TX0_P
TX0_N
RX2+
RX2-
S7
RX3+
S8
PIJ160S8 RX3-
PIJ160S7
S5
PIJ160S5
S6
PIJ160S6
S3
RX1+
S4
PIJ160S4 RX1-
PIJ160S3
--(- - -(-
C
TX3_P
TX3_N
-- -1- ___ -
TX2_P
TX2_N
TX1_P
TX1_N
TX0_P
TX0_N
RX3_P
RX3_N
RX2_P
RX2_N
RX1_P
RX1_N
~-
VCC_3V3_FPGA
POCX40BUS0TX30cx4010P
POCX40BUS0TX30cx4010N
POCX40BUS0TX20cx4010P
POCX40BUS0TX20cx4010N
POCX40BUS0TX10cx4010P
POCX40BUS0TX10cx4010N
POCX40BUS0TX00cx4010P
POCX40BUS0TX00cx4010N
POCX40BUS0RX30cx4010P
POCX40BUS0RX30cx4010N
POCX40BUS0RX20cx4010P
POCX40BUS0RX20cx4010N
POCX40BUS0RX10cx4010P
POCX40BUS0RX10cx4010N
POCX40BUS0RX00cx4010P
POCX40BUS0RX00cx4010N
POCX40BUS0cx401
CX4_BUS
RX3_P
RX3_N
RX2_P
RX2_N
RX1_P
RX1_N
RX0_P
RX0_N
COJ1
J16
S1
PIJ160S1 RX0+
S2
PIJ160S2 RX0-
~
B
A
RX0_P
RX0_N
.-'- +~--- - --~-~-
OJ, ---
VCC
MGT_BUS
100R_DIFF
i
r-~ ~ -~-- -~ ~ -j-\
~~II'
8
I
~~II'
GND
1
~
,,
~
l
JiH II'
Tt
4
11
11 1'
M1
II'
"II
M2
"
~
I
C1
1
T
c-
:
I
~
I
)
'r
1-
I~
I
PIC50 1
PIC50 2
1
~~II
A5
A6
S_IN-
L3
M1
MDIO
L1
PIU20L1 INT
H8
PIU20L4
XTAL2
88E1111-BAB
XTAL1
J9
PIU20J9
125CLK
SEL_FREQ
PIU20H9
H9
K2
PIU20K2
PIU20H8
COMA
PIU20K3 RESET
K3
L4
PIU20M1
PIU20L3 MDC
A7
S_OUT+
A8
PIU20A8 S_OUT-
PIU20A7
A3
A4
PIU20A4
S_CLK-
PIU20A3 S_IN+
PIU20A6
PIU20A5 S_CLK+
COL
f::=
f::=
I-3
= >-1 1
COTP1
TP1
M5
M6
PIU20M6
PIU20M5
PITP10
PITP20
r-
r=
r=
t=
i=
=
t=
148
M2
PIU20M2
PIR4501
PIR4502
R45
COR45
4k99
GND
TDO_3V3
5
TCK
TDI
TDO
TMS
TRST
6
10
13
PIU3013
PIU3010
GND
PIU307
3OE
4OE
3
1Y PIU303
6
2Y PIU306
8
3Y PIU308
11
4Y PIU3011
COU3
U3
SN74LVC125AD
GND
JTAG_BUS
1OE
2OE
PIU3014
VCC_3V3_FPGA
PID4801
PID4802
D47
COD43
1A
TDO_2V5
1
2
3
Date:
File:
A3
Size
Title
GND
GND
1
2
TRCT3
TRD3-
16
15
PID201
PID20
6
DIR
5
PIU405
7
PID302
PID301
D3
COD3
ORNG
8
PIC5 202
PID401
PID402
JTAG
POJTAG0TMS
POJTAG0TDO
POJTAG0TDI
POJTAG0TCK
POJTAG0T\R\S\T\
POJTAG
D4
COD4
ORNG
GND
1.1
8
Sheet 30 of 65
Drawn By:
Simon Scott
Revision
VCC_2V5_FPGA
COC441
C553
PIC5 301 1n
PIC5 302
PIJ20M1
COC440
C552
M1 PIC5 201 100n
M2
PIJ20M2
GND
LED Silkscreen Text:
Left LED: 1000MBPS
Middle LED: RX
Right LED: TX
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
29/03/2011
C:\Users\..\1gbps_ethernet.SchDoc
RHINO
D2
COD2
GRN
VCC_3V3_FPGA
VCC_3V3_FPGA
PIU406
1 Gbps Ethernet PHY
Number
Project
ORG_LED+_GRN_LED0826-1X1T-43-F
PIJ2015
PIJ2016 ORG_LED-_GRN_LED+
PIJ2014
8
PIJ208 TRD4+
7
PIJ207 TRCT4
9
PIJ209 TRD4-
PIJ202
PIJ201
4
TDO_3V3
B PIU404
VCCB
SN74LVC1T45DBVR
PIU402
PIU403 A
TRD2+
TRCT2
TRD2-
TRD1-
3
PIJ203
TRD3+
RJ45_YLW_LED
120R
120R
PIR4402
PIR4302
100R
PIR4002
120R
PIR3402
PIR3601
VCCA
U4
COU4
100R
PIR3602
COR36
R36
D48
COD44
1A
COR44
R44
R43
COR43
PIR4401
PIR4301
COR40
R40
PIR4001
COR34
R34
6
5
PIJ205
PIJ206
4
PIJ204
PIJ2010
10
TRD1+
COJ2
J2
12
PIJ2012
TRCT1
11
PIJ2011
14
YLW_LED+
RJ45_YLW_LED
13
PIJ2013 YLW_LED-
COC47 100n
C47
PIC4701 PIC4702
COC46 100n
C46
PIC4601 PIC4602
COC45 100n
C45
PIC4501 PIC4502
COC44
C44
100n
PIC4401 PIC4402
PIR3401
PIU401
VCC_2V5_FPGA
PID4702
PID4701
VCC_3V3_FPGA
GND
GND
GND
GND
r-
4
GND
w
n
GND
1.) PHY address is 0x01
2.) Config settings: pause disabled, full auto negotiation (slave preferred), crossover enabled, 125MHz clock output
disabled, set to GMII copper mode, sleep disabled, MDIO interface enabled
3.) Although the JTAG pins are powered off VDDOX (2.5V), they are 3.3V tolerant
4.) LEDs on RJ45 connector: Green LED indicates link up, Yellow LED indicates traffic
RSET
TCK
TDI
TDO
TMS
TRST PIU20M9
L9
PIU20L9
L7
PIU20L7
TDO_2V5
K8
PIU20K8
L8
PIU20L8
M9
To
1
4
PIU304
PIU301
PIU305
PIU302
100n
PIC4801 PIC4802
2
1A
5
2A
9
LED_RX PIU309
3A
LED_TX PIU3012
12
4A
VCC_2V5_FPGA
e
LED_TX
D8
CONFIG0 PIU20D8
E9
CONFIG1 PIU20E9
F8
PIU20F8
CONFIG2
G7
CONFIG3 PIU20G7
F9
CONFIG4 PIU20F9
G9
CONFIG5 PIU20G9
LED_RX
G8
CONFIG6 PIU20G8
HSDAC+
HSDAC-
COTP2
TP2
COC48
C48
PIR150 PIR160 PIR1701 PIR180 PIR190 PIR20 1 PIR210 PIR2 01
AVDD_2V5_1GPHY
Place the four 100nF caps
as close to the connector
pins as possible
GND
r-
2
LED_RX
LED_TX
ap
C9
D9
PIU20D9
PIU20C9
111
General Notes:
LED_RX
LED_TX
E8
LED_DUPLEX PIU20E8
PIC4301 10n
c
1
=
-
GND
PIU20D4 PIU20D5 PIU20D6 PIU20E4 PIU20E5 PIU20E6 PIU20F4 PIU20F5 PIU20F6 PIU20G4 PIU20G5 PIU20G6 PIU20H4 PIU20H5 PIU20H6 PIU20J4 PIU20J5 PIU20J6 PIU20K4 PIU20K5 PIU20K6 PIU20L5 PIU20L6 PIU20H7
C
C8
B8
A9
PIU20A9
PIU20B8
PIU20C8
COC43
PIC4302 C43
f---
~II
1.) HSDAC+ and HSDAC- pins must be left unconnected, but should be attached to test points
2.) The traces for the GMII bus must have 50 ohms impedance
3.) The 22 ohm termination resistors must be placed as close to the 88E1111 IC as possible
4.) The MDIx+/- traces must be routed as differential pairs, with 100 ohms diff impedance
5.) Place the 3 LEDs next to the RJ45 connector, with the silkscreen labels alongside
6.) Bypass capacitors should be distributed amongst the IC supply pins, and placed as close to the pins as
possible. Preference should be given to the placement of low value caps
GND
C50
COC50
18p
COR42
R42
4k7
1
PIX204
B5
B6
PIU20B6
LED_LINK10
LED_LINK100
LED_LINK1000
of
GND
PIC4201 10n
I~
ABMM2-25.000MHZ-E2-T
PIR4201
PIR420
PIR3902
ty
COC42
PIC4202 C42
Decoupling caps for
AVDD pins
7
f---
Layout Notes:
I
4
3
4k7
COR41
R41
5R6
33R
RXD3
RXD4
RXD5
RXD6
RXD7
PIR3702 PIU20B5 CRS
,---
GND GND
~
PIX203
PIR410
PIR4102
RXD0
RXD1
PIR2902 PIU20C3 RXD2
MDI3_P
MDI3_N
PIC4101 10n
PIR1502 PIR1602 PIR1702 PIR1802 PIR1902 PIR20 PIR210 PIR2 0
PIC40 1 10n
COC41
PIC4102 C41
GND
PIC3401 10u PIC3501 100n PIC3601100n PIC3701 10n PIC3801 10n PIC3901 1n
COC34 PIC3502 C35
COC35 PIC3602C36
COC36 PIC3702 C37
COC37 PIC3802 C38
COC38 PIC3902 C39
COC39
PIC3402 C34
AVDD_2V5_1GPHY
I...
GND
I
11
PIX202
VCC_2V5_FPGA
r
I
18p
COR37
R37
COR39
R39
PIR3901
PIR3701
PIR3501
PIR3301
PIR3201
COR32
R32
COR33
R33
COR35
R35
PIR3101
COR31
R31
PIR3001
PIU20D3
B2
D3
C3
B3
PIU20B3
C4
PIU20C4
A1
PIU20A1
A2
PIU20A2
C5
PIU20C5
PIU20B2
PIR2802
5R6
5R6
5R6
33R
PIR3002
5R6
PIR3102
5R6
PIR3202
5R6
PIR3302
5R6
PIR3502
PIR2702
UUH
I
I
PIC4901
COR28
R28
COR29
R29
COR30
R30
PIR2901
PIR2801
i
2
COR27
R27
PIR2701
N8
MDI3+ PIU20N8
N9
MDI3- PIU20N9
MDI1_P
MDI1_N
MDI2_P
MDI2_N
MDI0_P
MDI0_N
0-
111
RESET
COMA
COR26
R26
PIR2601
PIU20N4
PIU20N3
N3
N4
N1
N2
PIU20N2
PIU20N1
i 100R_DIFF
PIL102
6
COR15 COR16 COR17 COR18 COR19 COR20 COR21 COR22
lll'
MDC
MDIO
INT
COR25
R25
PIR2501
5R6
C1
PIU20C1 RX_CLK
5R6
B1
PIR2502 PIU20B1 RX_DV
5R6
D2
PIR2602 PIU20D2 RX_ER
K7
G1
PIU20G1
PIU20K7
N6
MDI2+ PIU20N6
N7
MDI2- PIU20N7
MDI1+
MDI1-
MDI0+
MDI0-
NC
NC
COC40
PIC40 2 C40
COL1
L1
PIL101
IT
GIGE_CTRL
COR24
R24
PIR2401
--
CRS
COL
RXD0
RXD1
RXD2
RXD3
RXD4
RXD5
RXD6
RXD7
RX_CLK
RX_DV
RX_ER
er
si
ni
v
U
Place these resistors
and caps close to the
88E1111 IC
Decoupling caps for
VDDO pins
fr f
H I
C49
COC49
TXD0
G2
PIU20G2 TXD1
G3
PIU20G3 TXD2
H2
PIU20H2 TXD3
H1
PIU20H1
TXD4
H3
PIU20H3 TXD5
J1
PIU20J1 TXD6
J2
PIU20J2
TXD7
F2
F1
PIU20F1
-
II
I,
A
B
C
D
I
D
\
-
II
,I
"'"
PIC4902
PIR2402
TX_ER
PIU20F2
-r- 1tr - .
- -
+
COX2
X2
--
D
1
-
~
II
•
~i-'
PIX201
TXD0
TXD1
TXD2
TXD3
TXD4
TXD5
TXD6
TXD7
GTX_CLK
TX_CLK
E2
E1
PIU20E1
TX_EN
D1
PIU20D1
PIU20E2
PIC3 01 1n
VCC_2V5_FPGA
c-
POCTRL0R\E\S\E\T\
POCTRL0MDIO
POCTRL0MDC
POCTRL0I\N\T\
POCTRL0COMA
POCTRL
CTRL
- -
-
~i-'
C
POGMII0TXD7
POGMII0TXD6
POGMII0TXD5
POGMII0TXD4
POGMII0TXD3
POGMII0TXD2
POGMII0TXD1
POGMII0TXD0
POGMII0TX0ER
POGMII0TX0EN
POGMII0TX0CLK
POGMII0RXD7
POGMII0RXD6
POGMII0RXD5
POGMII0RXD4
POGMII0RXD3
POGMII0RXD2
POGMII0RXD1
POGMII0RXD0
POGMII0RX0ER
POGMII0RX0DV
POGMII0RX0CLK
POGMII0GTX0CLK
POGMII0CRS
POGMII0COL
POGMII
GMII
~ --
TXD0
TXD1
TXD2
TXD3
TXD4
TXD5
TXD6
TXD7
,
TX_EN
TX_ER
,
,
,
5R6
PIR2302
oi
GTX_CLK
I--
COR23
VCC_2V5_FPGA
PIU20J7 PIU20J3 PIU20F3 PIU20E7 PIU20E3 PIU20D7 PIU20C7 PIU20C6 PIU20N5 PIU20M8 PIU20M7 PIU20M4 PIU20M3 PIU20B7 PIU20K1 PIU20C PIU20B4 PIU20L PIU20K9 PIU20J8 PIU20F7 PIU20B9
r=
R23
PIR2301
COU2
U2
I--
GTX_CLK
TX_CLK
TX_EN
TX_ER
GMII
50_OHM
i
AVDD_2V5_1GPHY
J7
J3
F3
E7
E3
D7
C7
C6
VCC_1V2_FPGA
GND
t=
B
GND
PIC2 01 10u PIC2301 10u PIC2401 100n PIC2501 100n PIC2601 100n PIC2701 100n PIC2801 10n PIC2901 10n PIC30 1 10n PIC3101 10n PIC3201 1n
COC23 PIC2402 C24
COC24 PIC2502 C25
COC25 PIC2602 COC26
COC28 PIC2902 C29
COC29 PIC30 2 C30
COC30 PIC3102 C31
COC31 PIC3202 COC32
PIC2 02 COC22
C22 PIC2302 C23
C26 PIC2702 COC27
C27 PIC2802 C28
C32 PIC3 02 COC33
C33
N5
M8
M7
M4
M3
B7
A
Decoupling caps for
DVDD pins
t=
'---
VDDO
VDDO
VDDO
PIC2101 1n
K1
C2
B4
VDDOX
VDDOX
PIC1501 10u PIC1601 100n PIC1701 100n PIC1801 100n PIC1901 100n PIC20 1 1n
J8
F7
B9
PIC1502 COC15
C15 PIC1602 COC16
C16 PIC1702 COC17
C17 PIC1802 COC18
C18 PIC1902 COC19
C19 PIC20 2 COC20
C20 PIC2102 COC21
C21
VCC_2V5_FPGA
R16
VCC_1V2_FPGA
R15
49R9
5
R17
49R9
4
R19
3
1=
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
~
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
2
If
~
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
:<l __
~
L
•
D4
D5
D6
E4
E5
E6
F4
F5
F6
G4
G5
G6
H4
H5
H6
J4
J5
J6
K4
K5
K6
L5
L6
9
~
I
H7
D
,
,
I
VSSC
R18
49R9
1
L2
K9
r=
III
14
0
[
VCC
0
GND
-
H 1J1H
7
~
VDDOH
VDDOH
VDDOH
R20
---1f---1f---1f~f~f~ff- Yf-YII
49R9
-
~f~ff- Yf- YII
R21
-Ie
49R9
-
,--1f~f~fe--1fe--1fe--1fe--1fe--1fR22
I49R9
r-
~H
~H
e--1 H
e--1 H
49R9
r i ll'
49R9
r-
f- r1ff-1ff-1ff-1ff-1fe--1f-YI
I
r-
r-
I
r-
r-
r-
I--
I--
149
V
1
-.JII'
I'
V
USER_LED0
I
"I
YLW
"I
YLW
COD30
D30
COD31
D31
YLW
PIR2501
PID320
PID3201
USER_LED2
PIR25401
PID3102
PID310
USER_LED3
COD29
D29
USER_LED1
"
YLW
COD33
D33
PIR25701
PID3402
PID3401
YLW
COD34
D34
COD35
D35
YLW
... (S-
"
71
... (S-
"
...(S-
3
PID2702
GPIO15
COD27
D27
3.3V
4
Sheet 31 of
Drawn By:
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
29/03/2011
C:\Users\..\spartan6_gpio.SchDoc
RHINO
Number
Project
f-Date:
File:
PID2701
D23
COD23
3.3V
GPIO11
COD19
D19
3.3V
GPIO7
Spartan-6 GPIO Header and LEDs
PID2602
~
A4
Size
Title
'l..oIII
~
PID2502
COD26
D26
3.3V
GPIO14
PID230
PID2301
-it
PID160
COD20
D20
3.3V
PID20 1
PID20 2
PID1602
COD16
D16
3.3V
PID2401
PID2802
65
Simon Scott
1.0
COD28
D28
3.3V
PID2801
PID240
D24
COD24
3.3V
Revision
-
JII'
I'
GND
COD36
D36
YLW
PIR25901
PID3602
PID3601
R259
120R
PIR25801
PID3502
PID3501
R258
120R
PID2601
GPIO10
D22
COD22
3.3V
PID1901
PID1902
PID1502
COD15
D15
3.3V
GPIO3
~
2
COD32
D32
YLW
PIR25601
PID3 02
PID3 01
R257
120R
COD25
D25
3.3V
GPIO13
PID2 02
GPIO6
COD18
D18
3.3V
PID150
'l..t
PIR25301
PID30 2
PID30 1
V
R256
120R
USER_LED4
R255
120R
v
R254
120R
USER_LED5
R253
120R
V
PIR25902 COR259
USER_LED6
PIR25802 COR258
v
PIR25702COR257
USER_LED7
PIR25602 COR256
PID2 01
~
~
PID2501
PID2102
GPIO9
D21
COD21
3.3V
PID1801
PID1802
COD14
D14
3.3V
GPIO2
'l..oIII
PIR2501
PID2902
PID2901
F-~ ~~ ~~ F-I
~
R252
120R
/
PIR2502 COR255
'l..oIII
~
GPIO12
'1..0lil
PID210
~
GPIO8
COD17
D17
3.3V
GPIO5
PID1402
't..iI
~
PIR25402 COR254
PID1701
PID1702
PID1401
'l..oIII
PIR25302COR253
GPIO4
PID1302
COD13
D13
3.3V
GPIO1
't..iI
~
~
PIR2502 COR252
w
n
GND
PID1301
GND
...111'
D
USER_LED[7..0]
5
PIU4305
GPIO0
't..iI
~
USER_LED[7..0]
POUSER0LED070000
POUSER0LED7
POUSER0LED6
POUSER0LED5
POUSER0LED4
POUSER0LED3
POUSER0LED2
POUSER0LED1
POUSER0LED0
To
ESDA5V3SC6
PIU4306
6
4
PIU4304
2
PIU4302
5
PIU4105
2
PIU4102
GPIO1
GPIO3
GPIO5
GPIO7
GPIO9
GPIO11
GPIO13
GPIO15
4
't..iI
GND
COU43
U43
PIU4303
3
100R
100R
100R
PIR24102
100R
PIR24302
100R
PIR24502
100R
PIR24702
100R
PIR24902
100R
PIR25102
PIR23902
PIR23702
ESDA5V3SC6
PIU4301
1
6
PIU4106
4
PIU4104
3
PIU4103
e
ap
COU41
U41
1
PIU4101
I;:! r~ ~~ F;:!
ESDA5V3SC6
PIU4206
6
4
C
COR237
R237
COR239
R239
COR241
R241
PIR24101
COR243
R243
PIR24301
COR245
R245
PIR24501
COR247
R247
PIR24701
COR249
R249
PIR24901
COR251
R251
PIR25101
PIR23901
PIR23701
't..iI
~
PIU4204
3
PIU4203
ty
GND
of
PIP2018
PIP2020
PIP2016
PIP2014
PIP2012
PIP208
PIP2010
PIP206
PIP204
't..iI
~
PIU4205
1
PIU4201
GND
2
4
6
8
10
12
14
16
18
20
90131-0130
PIP2017
PIP2019
1
3
5
7
9
11
13
15
17
19
er
si
ni
v
U
PIP2015
PIP2013
PIP2011
PIP207
PIP209
PIP205
PIP203
PIP202
3
't..iI
~
5
PIU4202
COU42
U42
PIU4006
6
4
PIU4004
3
PIU4003
1
PIU4001
F~ ~~ ~~ F-I
ESDA5V3SC6
PIU4005
100R
100R
100R
PIR24002
100R
PIR24202
100R
PIR24402
100R
PIR24602
100R
PIR24802
100R
PIR25002
PIR23802
PIR23602
COP2
P2
PIP201
~;:!
2
PIR25001
PIR24401
COR244
R244
COR246
R246
PIR24601
COR248
R248
PIR24801
COR250
R250
PIR24001
COR242
R242
PIR24201
COU40
U40
PIU4002
5
COR236
R236
COR238
R238
COR240
R240
PIR23801
PIR23601
PIF102
500mA Resettable
YII'
2
GPIO0
GPIO2
GPIO4
GPIO6
GPIO8
GPIO10
GPIO12
GPIO14
COF1
F1
PIF101
VCC_2V5_FPGA
I;:! ~~ ~~
~
C
GPIO[15..0]
2
r1
11 '
B
A
~
POGPIO3
POGPIO2
POGPIO1
POGPIO0
POGPIO0150000
POGPIO15
POGPIO14
POGPIO13
POGPIO12
POGPIO11
POGPIO10
POGPIO7
POGPIO6
POGPIO5
POGPIO4
POGPIO9
POGPIO8
GPIO[15..0]
1
A
D
C
B
1
f-
111'
f-
...(S-
...(St
...(St
"I
... (S-
f-
"I
...(S-
100n
COC202
C202
U
100R_DIFF
i
OUT_P
OUT_N
R221
82R
R222
82R
PIR2102 COR221 PIR2 02COR222
lll'
I.
130R
130R
COR223 COR224
R223
R224
-,,
,
~ ,,,,
,,
,,
1'
~
I
11
150
I
3
0R
II'
J
I
I
MGT_CLK0_N
MGT_CLK0_P
MGT_CLK1_N
MGT_CLK1_P
MGT_CLKS
4
Sheet 32 of
Drawn By:
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
SYS_CLK_N
SYS_CLK_P
FPGA_SYS_CLK
29/03/2011
C:\Users\..\spartan6_clocks.SchDoc
RHINO
Number
Project
Date:
File:
J
Spartan-6 Clocks
,,
,,
,,
,
,,,
,
A4
SYS_CLK_N
SYS_CLK_P
100R_DIFF
i
GND
-,,
Size
Title
PIR22702
0R
PIR22802
PIR2 601
R226
150R
PIC20602100n
COC206
C206
PIC20601
MGT_CLK_0_N
MGT_CLK_0_P
MGT_CLK_1_N
MGT_CLK_1_P
h
2
COR227
R227
PIR22701
R228
COR228
PIR22801
100n
PIC20502
100R_DIFF
i
POMGT0CLKS0MGT0CLK10P
POMGT0CLKS0MGT0CLK10N
POMGT0CLKS0MGT0CLK00P
POMGT0CLKS0MGT0CLK00N
POMGT0CLKS
MGT_CLKS
('
65
Simon Scott
Revision
1.0
POFPGA0SYS0CLK0SYS0CLK0P
POFPGA0SYS0CLK0SYS0CLK0N
POFPGA0SYS0CLK
FPGA_SYS_CLK
~
-
1
~
GND
GND
10n
w
n
COC207
C207
PIR2 501
100n
PIC20402
COC205
C205
PIC20501
PIR2 502COR225 PIR2 602COR226
R225
150R
COC204
C204
PIC20401
100n
PIC20302
~'Sl_
,-- - i, ~ '
01,,
,
:,
CCPD-033-50-100.000
100MHz Oscillator
GND
PIU3805
4
PIU3804
5
6
l
OUT
OUT
VCC
r1H II'
To
PIC207 2
PIC207 1
8
PIU3608
COC203
C203
PIC20301
,,
PIU3806
e
ap
GND
PIU3601 PIU3601 PIU36017 PIU3602 PIU360 PIU3604
9
PIU3609
10
PIU36010
12
11
PIU36011
PIU36012
PIR2 0 1
- -,
:,,
PIU3803
VAC_REF
OUTN0
OUTP0
OUTN1
OUTP1
COU36
U36
CDCLVP1102
PIR21901
R220
150R
S
3
U38
COU38
1
OE
2
PIU3802 NC
r:::::::n II'
-----, I,
C
INP
PIU3605 PIU36015 PIU36014 PIU36013
I
PIU3801
of
100n
COC200
C200
INN
PIC20 1
15
14
13
~
VCC_3V3_FPGA
1'
GND
11
11
GND
6
PIU3606
7
PIU3607
ty
niPIR2302 PIR2402
ve
PIR2301 PIR2 401 rs
i
PIR210 PIR2 01
1u
COC199
C199
GND
PIC19 01
R219
150R
GND
4
/'
1.) Place decoupling caps as close to the power pins of each clock IC as possible
2.) Place 82R and 130R termination resistors, on pins 6 and 7 of CDCLVP1102, as close to the input pins as possible
3.) Place the 150R and 100nF termination resistors and caps as close to the output pins of the CDCLVP1102 device as possible
4.) Place the 0R resistors as close as possible to the pins of the CCPD-033 IC
5
OUT PIU3705
4
OUT PIU3704
VCC
6
PIU3706
GND
PIC20 2
PIC20 1
PIC20 2
PIR21902COR219 PIR2 0 2COR220
.-'
Layout Notes:
SN10GE156
156.25MHz Oscillator
~
GND
GND
10n
COC201
C201
PIC19 02
3
~1
4=-
B
A
C
D
I
D
U1
3
PIU3703
GND
COU37
U37
1
PIU3701 OE
2
PIU3702 NC
PIC201 2
PIC201
:$L
,,
,,
,
,,
,
~~ J
C
4u7
COC198
C198
GND
PIC19801
PIL702
on
=
B
A
PIL701
COL7
L7
2
5
PIC19802
c-11H II'
VCC
VCC_3V3_FPGA
H II'
GND
GND
PWRPAD
~ HII'
=~
1
16
17
1
E
NC
NC
NC
~ll'
==
--~
NC
NC
NC
4=:sL
--
2
3
4
~\
,,,-- - ,,
01,,
1
f-
>
I
f-
f-
I
1
\
GND
GND
PIU501
3
SYS_BOOT6
9
2Y1 PIU509
SYS_BOOT7
7
2Y2 PIU507
SYS_BOOT4
5
2Y3 PIU505
SYS_BOOT5
3
2Y4 PIU503
I
4
POETH0PWRDWN
ETH_PWRDWN
POUSB0OTG0VBUS
POUSB0OTG0ID
POUSB0OTG0DRVVBUS
POUSB0OTG0DP
POUSB0OTG0DM
POUSB0OTG
USB_OTG
POHS0USB10STP
POHS0USB10NXT
POHS0USB10DIR
POHS0USB10DATA7
POHS0USB10DATA6
POHS0USB10DATA5
POHS0USB10DATA4
POHS0USB10DATA3
POHS0USB10DATA2
POHS0USB10DATA1
POHS0USB10DATA0
POHS0USB10CLK
POHS0USB1
HS_USB1
USB_OTG
HS_USB1
1588_GPIO[3..0]
am3517_decoupling
1588_GPIO[3..0]
PO15880GPIO030000
PO15880GPIO3
PO15880GPIO2
PO15880GPIO1
PO15880GPIO0
USB_I2C_EN
POUSB0I2C0EN
DBG_UART0
PODBG0UART00TX
PODBG0UART00RX
PODBG0UART00RTS
PODBG0UART00CTS
PODBG0UART0
RS232_CTRL
PORS2320CTRL0RI
PORS2320CTRL0I\N\V\A\L\I\D\
PORS2320CTRL0DTR
PORS2320CTRL0DSR
PORS2320CTRL0DCD
PORS2320CTRL
POAUDIO0DATA0LRCOUT
POAUDIO0DATA0LRCIN
POAUDIO0DATA0DAC0DIN
POAUDIO0DATA0BCLK
POAUDIO0DATA0ADC0DOUT
POAUDIO0DATA
AUDIO_DATA
DDC_I2C
PODDC0I2C0SDA
PODDC0I2C0SCL
PODDC0I2C
POFMC010CTRL0PG0C2M
POFMC010CTRL0P\R\S\N\T\0\M\2\C\
POFMC010CTRL0I2C0SDA
POFMC010CTRL0I2C0SCL
POFMC010CTRL0GA1
POFMC010CTRL0GA0
POFMC010CTRL
FMC_1_CTRL
POFMC000CTRL0PG0C2M
POFMC000CTRL0P\R\S\N\T\0\M\2\C\
POFMC000CTRL0I2C0SDA
POFMC000CTRL0I2C0SCL
POFMC000CTRL0GA1
POFMC000CTRL0GA0
POFMC000CTRL
FMC_0_CTRL
5
RTC_SQW/INT
PORTC0SQW0I\N\T\
RTC_SQW/INT
GND
PID602
PID601
PROC_LED_0
COD6
D6
YLW
8
Date:
File:
A3
Size
Title
I~
7
29/03/2011
C:\Users\..\am3517.SchDoc
RHINO
Number
Project
AM3517 (top-level)
Revision
1.1
8
Sheet 33 of 65
Drawn By:
Simon Scott
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
1.) Place the 100nF decoupling cap directly at pin 20 of the SN74HC244NSR IC
2.) Place the name of the LEDs (PROC_LED_x) on the silkscreen, next to the LED
Layout Notes:
1588_CLK
PO15880CLK
1588_CLK
DBG_UART0
RS232_CTRL
PWR_FAIL_INT
PWR_OFF_INT
RESPWRON
AUDIO_DATA
DDC_I2C
FMC_1_CTRL
FMC_0_CTRL
USB2_RST
e
USB1_RST
POU\S\B\1\0\R\S\T\
USB1_RST
POU\S\B\2\0\R\S\T\
USB2_RST
POHS0USB20STP
POHS0USB20NXT
POHS0USB20DIR
POHS0USB20DATA7
POHS0USB20DATA6
POHS0USB20DATA5
POHS0USB20DATA4
POHS0USB20DATA3
POHS0USB20DATA2
POHS0USB20DATA1
POHS0USB20DATA0
POHS0USB20CLK
POHS0USB2
HS_USB2
HS_USB2
USB_I2C_EN
am3517_power
6
POETH0RMII0TXEN
POETH0RMII0TXD1
POETH0RMII0TXD0
POETH0RMII0RXER
POETH0RMII0RXD1
POETH0RMII0RXD0
POETH0RMII0MDIO0DATA
POETH0RMII0MDIO0CLK
POETH0RMII0CRS0DV
POETH0RMII050MHZ0CLK
POETH0RMII
ETH_RMII
ETHER_RMII
ETH_PWRDWN
ap
POPROC0JTAG0TMS
POPROC0JTAG0TDO
POPROC0JTAG0TDI
POPROC0JTAG0TCK
POPROC0JTAG0T\R\S\T\
POPROC0JTAG
PROC_JTAG
PROC_JTAG
COD5
D5
YLW
PROC_LED_1
PID502
PID501
I--
2
PWR_FAIL_INT
PWR_OFF_INT
RESPWRON
2OE
PIU5013 2A2
PIU5011
11
2A1
13
15
PIU5015 2A3
17
PIU5017 2A4
PIU5019
19
18 SYS_BOOT0
1Y1 PIU5018
16 SYS_BOOT1
1Y2 PIU5016
14 SYS_BOOT2
1Y3 PIU5014
12 SYS_BOOT3
1Y4 PIU5012
POSUPPLY0EN0FPGA0VCCO0AUX0EN
POSUPPLY0EN0FPGA0VCCMGT0EN
POSUPPLY0EN0FPGA0VCCINT0EN
POSUPPLY0EN0FMC10SUPPLY0EN
POSUPPLY0EN0FMC10AUX0EN
POSUPPLY0EN0FMC00SUPPLY0EN
POSUPPLY0EN0FMC00AUX0EN
POSUPPLY0EN
SUPPLY_EN
POCLKS0IN0SYS0CLKREQ
POCLKS0IN0SYS0CLK
POCLKS0IN048M0CLK
POCLKS0IN032K0CLK
POCLKS0IN
CLKS_IN
POPWR0KILL
PWR_KILL
PWR_KILL
SUPPLY_EN
CLKS_IN
POI2C0PWR0MAN0SDA
POI2C0PWR0MAN0SCL
POI2C0PWR0MAN
I2C_PWR_MAN
PIR4702
I2C_PWR_MAN
USER_LED_1
l l
PWR_WARNS
POPWR0WARNS0VTTDDR30PG
POPWR0WARNS0VCCMGT0PG
POPWR0WARNS0R\E\S\P\W\R\O\N\
POPWR0WARNS0P\W\R\0\O\F\F\0\I\N\T\
POPWR0WARNS0P\W\R\0\F\A\I\L\0\I\N\T\
POPWR0WARNS0F\A\N\0\F\A\I\L\
POPWR0WARNS
1OE
2
1A1
4
PIU504 1A2
6
PIU506 1A3
8
PIU508 1A4
POE\T\H\0\R\E\S\E\T\
ETH_RESET
SYS_BOOT[7..0]
I
FAN_FAIL
VTTDDR3_PG
VCCMGT_PG
PWR_WARNS
1
SYS_BOOT[7..0]
POFPGA0SUSPEND
FPGA_SUSPEND
ETH_RESET
w
n
POFPGA0AWAKE
FPGA_AWAKE
FPGA_SUSPEND
To
POINIT0B0DIR
INIT_B_DIR
INIT_B_DIR
FPGA_AWAKE
120R
PORS2320DATA0TX
PORS2320DATA0RX
PORS2320DATA0RTS
PORS2320DATA0CTS
PORS2320DATA
RS232_DATA
120R
PIR4602
PODBG0UART10TX
PODBG0UART10RX
PODBG0UART10RTS
PODBG0UART10CTS
PODBG0UART1
DBG_UART1
RS232_DATA
COR47
R47
PIR4701
POFPGA0CONFIG0PROGRAM0B
POFPGA0CONFIG0INIT0B
POFPGA0CONFIG0DONE
POFPGA0CONFIG0DIN
POFPGA0CONFIG0CCLK
POFPGA0CONFIG
FPGA_CONFIG
DBG_UART1
COR46
R46
PIR4601
POSD0BUS0WP
POSD0BUS0DAT3
POSD0BUS0DAT2
POSD0BUS0DAT1
POSD0BUS0DAT0
POSD0BUS0CMD
POSD0BUS0CLK
POSD0BUS0CD
POSD0BUS
SD_BUS
FPGA_CONFIG
USER_LED_0
PODVI0VSYNC
PODVI0P\D\
PODVI0MON0SENS
PODVI0HSYNC
PODVI0DE
PODVI0DATA0230000
PODVI0DATA23
PODVI0DATA22
PODVI0DATA21
PODVI0DATA20
PODVI0DATA19
PODVI0DATA18
PODVI0DATA17
PODVI0DATA16
PODVI0DATA15
PODVI0DATA14
PODVI0DATA13
PODVI0DATA12
PODVI0DATA11
PODVI0DATA10
PODVI0DATA9
PODVI0DATA8
PODVI0DATA7
PODVI0DATA6
PODVI0DATA5
PODVI0DATA4
PODVI0DATA3
PODVI0DATA2
PODVI0DATA1
PODVI0DATA0
PODVI0CLK
PODVI
DVI
7
DVI
C
RTC_AUDIO_FP_SPI
of
6
I-
SD_BUS
BOOT_BUF_EN
ty
er
si
am3517_periph_b
GPMC_BUS
SDRC
am3517_periph_a
5
( (
PIU502
PIU502
COU5
U5
SN74LVC244ADB
VCC_3V3_PROC
CS2
CS1
MOSI
MISO
SCLK
CS0
I
PIU501
GND
PIC5102
100n
PIC5101
COC51
C51
MOSI
MISO
SCLK
CS
SPI_3CH
WAIT0
WAIT1
WAIT2
ni
v
U
CLK
WE
OE
ADV_ALE
CLE
WP
CS0
CS1
CS2
CS3_DMAREQ0
CS4
CS5_DMAREQ2
CS6_DMAREQ3
CS7_IODIR
D[15..0]
A[10..1]
GPMC_BUS
4
r
USB1_OC
POU\S\B\1\0\O\C\
USB2_OC
POU\S\B\2\0\O\C\
OTG_OC
POO\T\G\0\O\C\
POFP0SPI0PROC0SCLK
POFP0SPI0PROC0MOSI
POFP0SPI0PROC0MISO
POFP0SPI0PROC0C\S\
POFP0SPI0PROC
FP_SPI_PROC
SPI
MOSI
MISO
SCLK
CS
MOSI
MISO
SCLK
CS
R/B
3
v
D
C
151
I
POAUDIO0CTRL0SCLK
POAUDIO0CTRL0MOSI
POAUDIO0CTRL0MISO
POAUDIO0CTRL0C\S\
POAUDIO0CTRL
AUDIO_CTRL
SPI
SPI
WE
RE
ALE
CLE
WP
I '
PORTC0SPI0SCLK
PORTC0SPI0MOSI
PORTC0SPI0MISO
PORTC0SPI0C\S\
PORTC0SPI
RTC_SPI
PONAND0W\P\
PONAND0W\E\
PONAND0R\E\
PONAND0R0B\
PONAND0IO0150000
PONAND0IO15
PONAND0IO14
PONAND0IO13
PONAND0IO12
PONAND0IO11
PONAND0IO10
PONAND0IO9
PONAND0IO8
PONAND0IO7
PONAND0IO6
PONAND0IO5
PONAND0IO4
PONAND0IO3
PONAND0IO2
PONAND0IO1
PONAND0IO0
PONAND0CLE
PONAND0C\E\
PONAND0ALE
PONAND
NAND
CE
IO[15..0]
NAND_BUS
)
B
WP
_
BUSY0
BUSY1
CLK
WE
OE
ADV_ALE
CS0
CS1
CS2_DMAREQ0
CS3
CS4_DMAREQ1
CS5_DMAREQ2
CS6_IODIR
_
J~\
I
20
POFPGA0PROC0BUS0W\P\
POFPGA0PROC0BUS0W\E\
POFPGA0PROC0BUS0O\E\
POFPGA0PROC0BUS0D0150000
POFPGA0PROC0BUS0D15
POFPGA0PROC0BUS0D14
POFPGA0PROC0BUS0D13
POFPGA0PROC0BUS0D12
POFPGA0PROC0BUS0D11
POFPGA0PROC0BUS0D10
POFPGA0PROC0BUS0D9
POFPGA0PROC0BUS0D8
POFPGA0PROC0BUS0D7
POFPGA0PROC0BUS0D6
POFPGA0PROC0BUS0D5
POFPGA0PROC0BUS0D4
POFPGA0PROC0BUS0D3
POFPGA0PROC0BUS0D2
POFPGA0PROC0BUS0D1
POFPGA0PROC0BUS0D0
POFPGA0PROC0BUS0CLK
POFPGA0PROC0BUS0C\S\6\0IODIR
POFPGA0PROC0BUS0C\S\5\0D\M\A\R\E\Q\2\
POFPGA0PROC0BUS0C\S\4\0D\M\A\R\E\Q\1\
POFPGA0PROC0BUS0C\S\3\
POFPGA0PROC0BUS0C\S\2\0D\M\A\R\E\Q\0\
POFPGA0PROC0BUS0C\S\1\
POFPGA0PROC0BUS0C\S\0\
POFPGA0PROC0BUS0BUSY1
POFPGA0PROC0BUS0BUSY0
POFPGA0PROC0BUS0A\D\V\0ALE
POFPGA0PROC0BUS0A0100010
POFPGA0PROC0BUS0A10
POFPGA0PROC0BUS0A9
POFPGA0PROC0BUS0A8
POFPGA0PROC0BUS0A7
POFPGA0PROC0BUS0A6
POFPGA0PROC0BUS0A5
POFPGA0PROC0BUS0A4
POFPGA0PROC0BUS0A3
POFPGA0PROC0BUS0A2
POFPGA0PROC0BUS0A1
POFPGA0PROC0BUS
FPGA_PROC_BUS
D[15..0]
A[10..1]
FPGA_PROC_BUS
II ~ _
I II
I l
VCC
PODDR20W\E\
PODDR20VREF00V9
PODDR20UDQS10P
PODDR20UDQS10N
PODDR20UDQS00P
PODDR20UDQS00N
PODDR20UDM1
PODDR20UDM0
PODDR20R\A\S\
PODDR20ODT
PODDR20LDQS10P
PODDR20LDQS10N
PODDR20LDQS00P
PODDR20LDQS00N
PODDR20LDM1
PODDR20LDM0
PODDR20DQ100150000
PODDR20DQ1015
PODDR20DQ1014
PODDR20DQ1013
PODDR20DQ1012
PODDR20DQ1011
PODDR20DQ1010
PODDR20DQ109
PODDR20DQ108
PODDR20DQ107
PODDR20DQ106
PODDR20DQ105
PODDR20DQ104
PODDR20DQ103
PODDR20DQ102
PODDR20DQ101
PODDR20DQ100
PODDR20DQ000150000
PODDR20DQ0015
PODDR20DQ0014
PODDR20DQ0013
PODDR20DQ0012
PODDR20DQ0011
PODDR20DQ0010
PODDR20DQ009
PODDR20DQ008
PODDR20DQ007
PODDR20DQ006
PODDR20DQ005
PODDR20DQ004
PODDR20DQ003
PODDR20DQ002
PODDR20DQ001
PODDR20DQ000
PODDR20CKE
PODDR20CK0P
PODDR20CK0N
PODDR20C\S\
PODDR20C\A\S\
PODDR20BA020000
PODDR20BA2
PODDR20BA1
PODDR20BA0
PODDR20A0130000
PODDR20A13
PODDR20A12
PODDR20A11
PODDR20A10
PODDR20A9
PODDR20A8
PODDR20A7
PODDR20A6
PODDR20A5
PODDR20A4
PODDR20A3
PODDR20A2
PODDR20A1
PODDR20A0
PODDR2
DDR2
2
\
IIII
I I 111111
JJ
GND
A
1
I-
1'1'111
I I
10
(
v
C
B
A
D
I
I-
I-
III
I
CKE
I
y
0
DVI
)
152
'r
T
!~hH
~n
2
SD_CLK
PIR46202
PIU90AE13
AD11
AE11
PIU90AE11
AB12
PIU90AB12
AC12
PIU90AC12
AD12
PIU90AD12
AE12
PIU90AE12
AB13
PIU90AB13
AC13
PIU90AC13
AD13
PIU90AD13
AE13
PIU90AD11
4
5
w
n
L2
L1
M4
PIU90M4
M3
PIU90M3
M2
PIU90M2
M1
PIU90M1
N5
PIU90N5
N4
PIU90N4
N1
PIU90N1
R3
PIU90R3
R2
PIU90R2
R1
PIU90R1
R4
PIU90R4
T1
PIU90T1
T2
PIU90T2
T3
PIU90T3
T4
PIU90T4
T5
PIU90T5
U1
6
F20
UART2_CTS/MCBSP3_DX/GPT9_PWM_EVT/GPIO_144 PIU90F20
F19
UART2_RTS/MCBSP3_DR/GPT10_PWM_EVT/GPIO_145 PIU90F19
E24
UART2_TX/MCBSP3_CLKX/GPT11_PWM_EVT/GPIO_146 PIU90E24
E23
UART2_RX/MCBSP3_FSX/GPT8_PWM_EVT/GPIO_147 PIU90E23
N2
UART3_CTS_RCTX/GPIO_163 PIU90N2
N3
UART3_RTS_SD/GPIO_164 PIU90N3
P1
UART3_RX_IRRX/GPIO_165 PIU90P1
P2
UART3_TX_IRTX/GPIO_166 PIU90P2
PIU90U1
PIU90L1
PIU90L2
Date:
File:
A3
Size
Title
GPMC_D[15..0]
D[15..0]
CS0
CS1
CS2
CS3_DMAREQ0
CS4
CS5_DMAREQ2
CS6_DMAREQ3
CS7_IODIR
CLK
WE
OE
ADV_ALE
CLE
RS232
WP
WAIT0
WAIT1
WAIT2
RTS
CTS
RX
TX
RS232
7
POGPMC0BUS0WAIT2
POGPMC0BUS0WAIT1
POGPMC0BUS0WAIT0
POGPMC0BUS0W\P\
POGPMC0BUS0W\E\
POGPMC0BUS0O\E\
POGPMC0BUS0D0150000
POGPMC0BUS0D15
POGPMC0BUS0D14
POGPMC0BUS0D13
POGPMC0BUS0D12
POGPMC0BUS0D11
POGPMC0BUS0D10
POGPMC0BUS0D9
POGPMC0BUS0D8
POGPMC0BUS0D7
POGPMC0BUS0D6
POGPMC0BUS0D5
POGPMC0BUS0D4
POGPMC0BUS0D3
POGPMC0BUS0D2
POGPMC0BUS0D1
POGPMC0BUS0D0
POGPMC0BUS0CLK
POGPMC0BUS0CLE
POGPMC0BUS0C\S\7\0IODIR
POGPMC0BUS0C\S\6\0D\M\A\R\E\Q\3\
POGPMC0BUS0C\S\5\0D\M\A\R\E\Q\2\
POGPMC0BUS0C\S\4\
POGPMC0BUS0C\S\3\0D\M\A\R\E\Q\0\
POGPMC0BUS0C\S\2\
POGPMC0BUS0C\S\1\
POGPMC0BUS0C\S\0\
POGPMC0BUS0A\D\V\0ALE
POGPMC0BUS0A0100010
POGPMC0BUS0A10
POGPMC0BUS0A9
POGPMC0BUS0A8
POGPMC0BUS0A7
POGPMC0BUS0A6
POGPMC0BUS0A5
POGPMC0BUS0A4
POGPMC0BUS0A3
POGPMC0BUS0A2
POGPMC0BUS0A1
POGPMC0BUS
GPMC_BUS
Revision
1.1
DBG_UART1
PODBG0UART10TX
PODBG0UART10RX
PODBG0UART10RTS
PODBG0UART10CTS
PODBG0UART1
RS232_DATA
PORS2320DATA0TX
PORS2320DATA0RX
PORS2320DATA0RTS
PORS2320DATA0CTS
PORS2320DATA
8
Sheet 34 of 65
Drawn By:
Simon Scott
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
29/03/2011
C:\Users\..\am3517_periph_a.SchDoc
RHINO
Number
Project
AM3517 Peripherals (Part A)
CTS
RTS
RX
TX
ETH_RESET
POE\T\H\0\R\E\S\E\T\
POFPGA0SUSPEND
FPGA_SUSPEND
-
3
MMC2_CLK/MCSPI3_CLK/UART4_CTS/GPIO_130
MMC2_CMD/MCSPI3_SIMO/UART4_RTS/GPIO_131
MMC2_DAT0/MCSPI3_SOMI/UART4_TX/GPIO_132
MMC2_DAT1/UART4_RX/GPIO_133
MMC2_DAT2/MCSPI3_CS1/GPIO_134
MMC2_DAT3/MCSPI3_CS0/GPIO_135
MMC2_DAT4/MMC2_DIR_DAT0/MMC3_DAT0/GPIO_136
MMC2_DAT5/MMC2_DIR_DAT1/MMC3_DAT1/GPIO_137
MMC2_DAT6/MMC2_DIR_CMD/MMC3_DAT2/GPIO_138
MMC2_DAT7/MMC2_CLKIN/MMC3_DAT3/GPIO_139
To
GPMC_nCS0
GPMC_nCS1/GPIO_52
GPMC_nCS2/GPT9_PWM_EVT/GPIO_53
GPMC_nCS3/SYS_nDMAREQ0/GPT10_PWM_EVT/GPIO_54
GPMC_nCS4/SYS_nDMAREQ1/GPT9_PWM_EVT/GPIO_55
GPMC_nCS5/SYS_nDMAREQ2/GPT10_PWM_EVT/GPIO_56
GPMC_nCS6/SYS_nDMAREQ3/GPT11_PWM_EVT/GPIO_57
GPMC_nCS7/GPMIC_IO_DIR/GPT8_PWM_EVT/GPIO_58
GPMC_CLK/GPIO_59
GPMC_nWE
GPMC_nOE
GPMC_nADV_ALE
GPMC_nBEO_CLE/GPIO_60
GPMC_nBE1/GPIO61
GPMC_nWP/GPIO62
GPMC_WAIT0
GPMC_WAIT1/UART4_TX/GPIO_63
GPMC_WAIT2/UART4_RX/GPIO_64
GPMC_WAIT3/SYS_nDMAREQ1/UART3_CTS_RCTX/GPIO_65
-
1
~
FPGA_AWAKE
POFPGA0AWAKE
22R
22R
PIR8302
22R
PIR8502
22R
PIR33102
22R
PIR33802
22R
PIR3802
IQ'
PIR46201
R38
COR38
R83
COR83
PIR8301
R85
COR85
PIR8501
R331
COR334
PIR33101
R338
COR335
PIR33801
R462
COR336
PIR3801
GND
MMC1_CLK/GPIO_120
MMC1_CMD/GPIO_121
MMC1_DAT0/MCSPI2_CLK/GPIO_122
MMC1_DAT1/MCSPI2_SIMO/GPIO_123
MMC1_DAT2/MCSPI2_SOMI/GPIO_124
MMC1_DAT3/MCSPI2_CS0/GPIO_125
MMC1_DAT4/GPIO_126
MMC1_DAT5/GPIO_127
MMC1_DAT6/GPIO_128
PIU90AE10 MMC1_DAT7/GPIO_129
AA9
PIU90AA9
AB9
PIU90AB9
AC9
PIU90AC9
AD9
PIU90AD9
AE9
PIU90AE9
AA10
PIU90AA10
AB10
PIU90AB10
AC10
PIU90AC10
AD10
PIU90AD10
AE10
e
ap
C
,
SD_BUS
POSD0BUS0WP
POSD0BUS0DAT3
POSD0BUS0DAT2
POSD0BUS0DAT1
POSD0BUS0DAT0
POSD0BUS0CMD
POSD0BUS0CLK
POSD0BUS0CD
POSD0BUS
I
PROGRAM_B
INIT_B
DONE
CCLK
DIN
PIR11402
PIR11401
of
A[10..1]
I
SD_CLK
22R
22R
22R
22R
PIR11202
PIR11102
PIR11302
PIR11301
DSS_DATA0/UART1_CTS/GPIO_70
DSS_DATA1/UART1_RTS/GPIO_71
DSS_DATA2/GPIO_72
DSS_DATA3/GPIO_73
DSS_DATA4/UART3_RX_IRRX/GPIO_74
DSS_DATA5/UART3_TX_IRTX/GPIO_75
DSS_DATA6/UART1_TX/GPIO_76
DSS_DATA7/UART1_RX/GPIO_77
DSS_DATA8/GPIO_78
DSS_DATA9/GPIO_79
DSS_DATA10/GPIO_80
DSS_DATA11/GPIO_81
DSS_DATA12/GPIO_82
DSS_DATA13/GPIO_83
DSS_DATA14/GPIO_84
DSS_DATA15/GPIO_85
DSS_DATA16/GPIO_86
DSS_DATA17/GPIO_87
DSS_DATA18/MCSPI3_CLK/DSS_DATA4/GPIO_88
DSS_DATA19/MCSPI3_SIMO/DSS_DATA3/GPIO_89
DSS_DATA20/MCSPI3_SOMI/DSS_DATA2/GPIO_90
DSS_DATA21/MCSPI3_CS0/DSS_DATA1/GPIO_91
DSS_DATA22/MCSPI3_CS1/DSS_DATA0/GPIO_92
DSS_DATA23/DSS_DATA5/GPIO_93
DSS_PCLK/GPIO_66
DSS_HSYNC/GPIO_67
DSS_VSYNC/GPIO_68
PIU90AE24 DSS_ACBIAS/GPIO_69
22R AD24
22R PIU90AD25
AD25
PIR8702
22R PIU90AC23
AC23
PIR8802
22R PIU90AC24
AC24
PIR9002
22R
AC25
PIR9102
PIU90AC25
22R PIU90AB24
AB24
PIR9202
22R PIU90AB25
AB25
PIR9302
22R
AA23
PIR9402
PIU90AA23
22R PIU90AA24
AA24
PIR9502
22R PIU90AA25
AA25
PIR9602
22R PIU90Y22
Y22
PIR9702
22R PIU90Y23
Y23
PIR9802
22R PIU90Y24
Y24
PIR9902
22R Y25
PIR10002PIU90Y25
22R PIU90W21
W21
PIR10102
22R PIU90W22
W22
PIR10202
22R W23
PIR10302PIU90W23
22R W24
PIR10402
PIU90W24
22R PIU90W25
W25
PIR10502
22R PIU90V24
V24
PIR10602
22R V25
PIR10702PIU90V25
22R U21
PIR10802
PIU90U21
22R PIU90U22
U22
PIR10902
22R PIU90U23
U23
PIR11002
AE23
PIU90AE23
AD22
PIU90AD22
AD23
PIU90AD23
AE24
PIR8602
PIU90AD24
K1
GPMC_D15
GPMC_D15/GPIO_51 PIU90K1
K2
GPMC_D14
GPMC_D14/GPIO_50 PIU90K2
K3
GPMC_D13
GPMC_D13/GPIO_49 PIU90K3
K4
GPMC_D12
GPMC_D12/GPIO_48 PIU90K4
J1
GPMC_D11
GPMC_D11/GPIO_47 PIU90J1
J2
GPMC_D10
GPMC_D10/GPIO_46 PIU90J2
J3
GPMC_D9
GPMC_D9/GPIO_45 PIU90J3
J4
GPMC_D8
GPMC_D8/GPIO_44 PIU90J4
J5
GPMC_D7
GPMC_D7 PIU90J5
H1
GPMC_D6
GPMC_D6 PIU90H1
H2
GPMC_D5
GPMC_D5 PIU90H2
G1
GPMC_D4
GPMC_D4 PIU90G1
G2
GPMC_D3
GPMC_D3 PIU90G2
G3
GPMC_D2
GPMC_D2 PIU90G3
G4
GPMC_D1
GPMC_D1 PIU90G4
G5
GPMC_D0
GPMC_D0 PIU90G5
GPMC_BUS
GPMC_A[10..1]
8
A
B
C
D
I
D
COR111
R111
R112
COR112
R113
COR113
COR114
R114
PIR11001
R110
COR110
PIR10901
R109
COR109
PIR10801
PIR10701
PIR10601
R106
COR106
R107
COR107
COR108
R108
PIR10501
R105
COR105
PIR10401
PIR10301
R103
COR103
COR104
R104
PIR10201
R102
COR102
PIR10101
PIR10001
PIR9901
R99
COR99
COR100
R100
COR101
R101
PIR9801
R98
COR98
PIR9701
PIR9601
COR96
R96
COR97
R97
PIR9501
COR95
R95
PIR9401
PIR9301
PIR9201
R92
COR92
COR93
R93
COR94
R94
PIR9101
COR91
R91
PIR9001
PIR8801
COR88
R88
COR90
R90
COR87
R87
PIR8701
ty
G6
GPMC_A10
GPMC_A10/SYS_nDMAREQ3/GPIO_43 PIU90G6
F1
GPMC_A9
GPMC_A9/SYS_nDMAREQ2/GPIO_42 PIU90F1
F2
GPMC_A8
GPMC_A8/GPIO_41 PIU90F2
F3
GPMC_A7
GPMC_A7/GPIO_40 PIU90F3
F4
GPMC_A6
GPMC_A6/GPIO_39 PIU90F4
F6
GPMC_A5
GPMC_A5/GPIO_38 PIU90F6
F7
GPMC_A4
PIU90F7
GPMC_A4/GPIO_37
E1
GPMC_A3
GPMC_A3/GPIO_36 PIU90E1
GPMC_A2
E2
GPMC_A2/GPIO_35 PIU90E2
GPMC_A1
E3
PIU90E3
GPMC_A1/GPIO_34
DQ0_[15..0]
DQ1_[15..0]
III
SD_CARD
CLK
CMD
DAT0
DAT1
DAT2
DAT3
WP
CD
COR86
R86
PIR8601
IIImWtjw~wwl~i 11
>/
PIR11201
PIR11101
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
DATA16
DATA17
DATA18
DATA19
DATA20
DATA21
DATA22
DATA23
10R
er
si
ni
v
DQ1_14
DQ1_13
C2
DQ1_12
PIU90C2
C3
DQ1_11
PIU90C3
B3
DQ1_10
PIU90B3
A3
DQ1_9
PIU90A3
B4
DQ1_8
PIU90B4
C5
DQ1_7
PIU90C5
B5
PIU90B5 DQ1_6
D6
DQ1_5
PIU90D6
C6
DQ1_4
PIU90C6
E7
DQ1_3
PIU90E7
D7
DQ1_2
PIU90D7
B7
DQ1_1
PIU90B7
A7
DQ1_0
PIU90A7
A15
PIU90A15 DQ0_15
A16
DQ0_14
PIU90A16
B16
DQ0_13
PIU90B16
C16
DQ0_12
PIU90C16
D16
DQ0_11
PIU90D16
C17
DQ0_10
PIU90C17
D17
DQ0_9
PIU90D17
B18
DQ0_8
PIU90B18
B19
DQ0_7
PIU90B19
C19
DQ0_6
PIU90C19
D19
DQ0_5
PIU90D19
E19
DQ0_4
PIU90E19
C20
PIU90C20 DQ0_3
D20
DQ0_2
PIU90D20
A21
DQ0_1
PIU90A21
DQ0_0
B21
PIU90B21
B1
D2
PIU90D2
PIU90B1
C1
DQ1_15
PIU90C1
I II
FPGA_CONFIG_BUS
DATA[23..0]
COR84
R84
PIR8401
PIR8402
PIR8202
22R
10R
PIR8102
PIR8201
COR82
R82
PIR8101
COR81
R81
COR80
R80
PIR8001
PIR7901
U
-
DATA[23..0]
CLK
HSYNC
VSYNC
DE
MON_SENS
PD
COR77
COR78
R78
COR79
R79
PIR7801
R77
PIR7701
A14
E13
PIU90E13
D1
PIU90D1
E8
PIU90E8
B15
PIU90B15
C21
PIU90C21
A2
PIU90A2
A6
PIU90A6
B17
PIU90B17
B20
PIU90B20
B2
PIU90B2
B6
PIU90B6
A17
PIU90A17
A20
PIU90A20
C8
PIU90C8
A19
PIU90A19
A18
PIU90A18
A5
PIU90A5
A4
PIU90A4
B12
PIU90B12
F14
PIU90F14
PIU90A14
SDRC_D31
SDRC_D30
SDRC_D29
SDRC_D28
SDRC_D27
SDRC_D26
SDRC_D25
SDRC_D24
SDRC_D23
SDRC_D22
SDRC_D21
SDRC_D20
SDRC_D19
SDRC_D18
SDRC_D17
SDRC_D16
SDRC_D15
SDRC_D14
SDRC_D13
SDRC_D12
SDRC_D11
SDRC_D10
SDRC_D9
SDRC_D8
SDRC_D7
SDRC_D6
SDRC_D5
SDRC_D4
SDRC_D3
SDRC_D2
SDRC_D1
SDRC_D0
7
11111111
,
INIT_B_DIR
POINIT0B0DIR
GND
22R
PIR7602
22R
PIR7702
22R
PIR7802
22R
PIR7902
22R
PIR8002
1.) Place series termination resistors as close as possible to processor pins
2.) Routing of SDRC_STREN0: loopback trace must be length of SDRC_CLK trace + avg
length of SDRC_DQS0 and SDRC_DQS1 traces
3.) Routing of SDRC_STREN1: loopback trace must be length of SDRC_CLK trace + avg
length of SDRC_DQS2 and SDRC_DQS3 traces
AM3517ZCN
6
~
FPGA_CONFIG
POFPGA0CONFIG0PROGRAM0B
POFPGA0CONFIG0INIT0B
POFPGA0CONFIG0DONE
POFPGA0CONFIG0DIN
POFPGA0CONFIG0CCLK
POFPGA0CONFIG
>-------j-~ II
PIR8901
49R9
COR89
R89
D14
PIU90D14
SDRC_CKE0
22R
PIR7502
COR76
R76
PIR7601
:H.:;
100n
COC119
C119
A13
B13
10R
10R
11
PIC1 901
PIC1 902
PIR8902
PIU90B13
PIR7402
PIR7401
SDRC_nCS1
SDRC_nCS0
SDRC_DM3
SDRC_DM2
SDRC_DM1
SDRC_DM0
SDRC_DQS3P
SDRC_DQS2P
SDRC_DQS1P
SDRC_DQS0P
SDRC_DQS3N
SDRC_DQS2N
SDRC_DQS1N
SDRC_DQS0N
SDRC_ODT0
SDRC_STREN0
SDRC_STREN_DLY0
SDRC_STREN1
SDRC_STREN_DLY1
DDR_PADREF
VREFSSTL
PIU90A13
PIR7302
SDRC_nRAS
SDRC_nCAS
SDRC_nWE
SDRC_CLK
SDRC_nCLK
COR75
R75
PIR7501
C14
B14
PIU90B14
E14
PIU90E14
PIU90C14
22R
22R
PIR7202
COR72
COR73
R73
PIR7301
COR74
R74
22R
PIR7102
PIR7002
R72
PIR7201
R71
PIR7101
COR71
PIR7001
COR70
R70
22R
PIR6902
PIR6802
PIR6702
22R
22R
22R
PIR6602
SDRC_A14
SDRC_A13
SDRC_A12
B9
PIU90B9
SDRC_A11
A9
PIU90A9
SDRC_A10
E10
PIU90E10 SDRC_A9
D10
PIU90D10 SDRC_A8
C10
PIU90C10
SDRC_A7
B10
PIU90B10 SDRC_A6
A10
PIU90A10 SDRC_A5
E11
PIU90E11
SDRC_A4
D11
PIU90D11
SDRC_A3
C11
PIU90C11 SDRC_A2
B11
PIU90B11 SDRC_A1
A11
PIU90A11
SDRC_A0
B8
A8
PIU90A8
PIU90B8
5
-
VREF_0V9
CS
UDM1
LDM1
UDM0
LDM0
UDQS1_P
LDQS1_P
UDQS0_P
LDQS0_P
UDQS1_N
LDQS1_N
UDQS0_N
LDQS0_N
ODT
A[13..0]
BA[2..0]
22R
PIR6502
PIR6402
PIR6302
22R
22R
22R
PIR6202
22R
PIR6102
PIR6002
22R
22R
PIR5902
22R
PIR5802
D8
PIU90D8
Layout Notes:
4
(
DVI
PODVI0VSYNC
PODVI0P\D\
PODVI0MON0SENS
PODVI0HSYNC
PODVI0DE
PODVI0DATA0230000
PODVI0DATA23
PODVI0DATA22
PODVI0DATA21
PODVI0DATA20
PODVI0DATA19
PODVI0DATA18
PODVI0DATA17
PODVI0DATA16
PODVI0DATA15
PODVI0DATA14
PODVI0DATA13
PODVI0DATA12
PODVI0DATA11
PODVI0DATA10
PODVI0DATA9
PODVI0DATA8
PODVI0DATA7
PODVI0DATA6
PODVI0DATA5
PODVI0DATA4
PODVI0DATA3
PODVI0DATA2
PODVI0DATA1
PODVI0DATA0
PODVI0CLK
PODVI
A[13..0]
RAS
CAS
WE
CK_P
CK_N
BA[2..0]
f~1 f~1 ~~1 i~1 :s ;>~
22R
PIR5702
1
I
C
DQ1_[15..0]
I
DQ1_[15..0]
PIR5602
3
-
B
POSDRC0W\E\
POSDRC0VREF00V9
POSDRC0UDQS10P
POSDRC0UDQS10N
POSDRC0UDQS00P
POSDRC0UDQS00N
POSDRC0UDM1
POSDRC0UDM0
POSDRC0R\A\S\
POSDRC0ODT
POSDRC0LDQS10P
POSDRC0LDQS10N
POSDRC0LDQS00P
POSDRC0LDQS00N
POSDRC0LDM1
POSDRC0LDM0
POSDRC0DQ100150000
POSDRC0DQ1015
POSDRC0DQ1014
POSDRC0DQ1013
POSDRC0DQ1012
POSDRC0DQ1011
POSDRC0DQ1010
POSDRC0DQ109
POSDRC0DQ108
POSDRC0DQ107
POSDRC0DQ106
POSDRC0DQ105
POSDRC0DQ104
POSDRC0DQ103
POSDRC0DQ102
POSDRC0DQ101
POSDRC0DQ100
POSDRC0DQ000150000
POSDRC0DQ0015
POSDRC0DQ0014
POSDRC0DQ0013
POSDRC0DQ0012
POSDRC0DQ0011
POSDRC0DQ0010
POSDRC0DQ009
POSDRC0DQ008
POSDRC0DQ007
POSDRC0DQ006
POSDRC0DQ005
POSDRC0DQ004
POSDRC0DQ003
POSDRC0DQ002
POSDRC0DQ001
POSDRC0DQ000
POSDRC0CKE
POSDRC0CK0P
POSDRC0CK0N
POSDRC0C\S\
POSDRC0C\A\S\
POSDRC0BA020000
POSDRC0BA2
POSDRC0BA1
POSDRC0BA0
POSDRC0A0130000
POSDRC0A13
POSDRC0A12
POSDRC0A11
POSDRC0A10
POSDRC0A9
POSDRC0A8
POSDRC0A7
POSDRC0A6
POSDRC0A5
POSDRC0A4
POSDRC0A3
POSDRC0A2
POSDRC0A1
POSDRC0A0
POSDRC
SDRC
,
DQ0_[15..0]
-
DQ0_[15..0]
PROC_DDR2_BUS
22R
COR56
R56
A13 PIR5601
COR57
R57
A12 PIR5701
COR58
R58
A11 PIR5801
COR59
R59
A10 PIR5901
COR60
R60
A9 PIR6001
COR61
R61
A8 PIR6101
COR62
R62
A7 PIR6201
COR63
R63
A6 PIR6301
COR64
R64
A5 PIR6401
COR65
R65
A4 PIR6501
COR66
R66
A3 PIR6601
COR67
R67
A2 PIR6701
COR68
R68
A1 PIR6801
COR69
R69
A0 PIR6901
PIU90A12
A12
SDRC_BA0
22R
PIR5502
PIR5501
~i
COR54
COR55
R55
SDRC_BA2
C13
PIU90C13
SDRC_BA1
22R
PIR5402
COU9A
U9A
D13
PIU90D13
22R
PIR5302
R54
PIR5401
COR53
-
R53
PIR5301
BA2
BA1
BA0
2
-
A
1
-
I
r-
r-
f-
f-
f-
c-
-
1
RS232
R127
10k
1u
3
4
PIR13701
GND
PIR13801
R138
10k
1k
PIS104
PIR13501
1k
R135
COR135
PIS103
PIR13302
PIR13502
PIR13301
5
ON
ON
ETH, USB, MMC
OFF ETH, USB, NAND
MMC, ETH, USB
ON
OFF ON
OFF OFF NAND, ETH, USB
SW1 SW2 BOOT ORDER
VCC_3V3_PROC
Layout Note:
Place legend on silkscreen, next
to switches
ADE0204
SW2
SW1
R133
COR133
--= -
2
GND
R137
10k
PIR13702COR137 PIR13802COR138
PIS102
PIS101
S1
COS1
'Tl
100n
C121
COC121
BOOT_SW2
BOOT_SW1
L
PIC12101
PIC12102
1k65
PIR13602
PIR13402
1k65
6
PIR12801
R128
4k7
Date:
File:
A3
Size
Title
PIR12901
R129
4k7
PIR1280 COR128 PIR1290 COR129
GND
'V
R131
4k7
PIR130 1
PIR13 01
PIR13201
R132
4k7
PIR12401
PIR12501
SYS_BOOT0
SYS_BOOT1
SYS_BOOT2
SYS_BOOT3
SYS_BOOT4
SYS_BOOT5
SYS_BOOT6
SYS_BOOT7
R125
4k7
7
1.1
8
Sheet 35 of 65
Drawn By:
Simon Scott
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
29/03/2011
C:\Users\..\am3517_periph_b.SchDoc
RHINO
Number
Project
SYS_BOOT[7..0]
POSYS0BOOT070000
POSYS0BOOT7
POSYS0BOOT6
POSYS0BOOT5
POSYS0BOOT4
POSYS0BOOT3
POSYS0BOOT2
POSYS0BOOT1
POSYS0BOOT0
POHS0USB10STP
POHS0USB10NXT
POHS0USB10DIR
POHS0USB10DATA7
POHS0USB10DATA6
POHS0USB10DATA5
POHS0USB10DATA4
POHS0USB10DATA3
POHS0USB10DATA2
POHS0USB10DATA1
POHS0USB10DATA0
POHS0USB10CLK
POHS0USB1
HS_USB1
1588_GPIO[3..0]
PO15880GPIO030000
PO15880GPIO3
PO15880GPIO2
PO15880GPIO1
PO15880GPIO0
POUSB0I2C0EN
USB_I2C_EN
POU\S\B\2\0\R\S\T\
USB2_RST
POU\S\B\1\0\R\S\T\
USB1_RST
PORTC0SQW0I\N\T\
RTC_SQW/INT
POFMC010CTRL0PG0C2M
POFMC010CTRL0P\R\S\N\T\0\M\2\C\
POFMC010CTRL0I2C0SDA
POFMC010CTRL0I2C0SCL
POFMC010CTRL0I2C
POFMC010CTRL0GA1
POFMC010CTRL0GA0
POFMC010CTRL
FMC_1_CTRL
POFMC000CTRL0PG0C2M
POFMC000CTRL0P\R\S\N\T\0\M\2\C\
POFMC000CTRL0I2C0SDA
POFMC000CTRL0I2C0SCL
POFMC000CTRL0I2C
POFMC000CTRL0GA1
POFMC000CTRL0GA0
POFMC000CTRL
FMC_0_CTRL
POAUDIO0DATA0LRCOUT
POAUDIO0DATA0LRCIN
POAUDIO0DATA0DAC0DIN
POAUDIO0DATA0BCLK
POAUDIO0DATA0ADC0DOUT
POAUDIO0DATA
AUDIO_DATA
POHS0USB20STP
POHS0USB20NXT
POHS0USB20DIR
POHS0USB20DATA7
POHS0USB20DATA6
POHS0USB20DATA5
POHS0USB20DATA4
POHS0USB20DATA3
POHS0USB20DATA2
POHS0USB20DATA1
POHS0USB20DATA0
POHS0USB20CLK
POHS0USB2
HS_USB2
Revision
VCC_3V3_PROC
1588_GPIO[3..0]
FMC_I2C_SCL
FMC_I2C_SDA
PIR1240COR124 PIR12502COR125
R124
4k7
PIR1901 PIR1201
PIR1302COR130 PIR13 02COR131 PIR1320 COR132
R130
4k7
STP
CLK
DATA0
DATA1
DATA2
DATA7
DATA4
DATA5
DATA6
DATA3
DIR
NXT
ULPI
SCL
SDA
COR119
R119
4k7
COR120
R120
4k7
PIR1902 PIR120
8
PORTC0AUDIO0FP0SPI0SCLK
PORTC0AUDIO0FP0SPI0MOSI
PORTC0AUDIO0FP0SPI0MISO
PORTC0AUDIO0FP0SPI0C\S\2\
PORTC0AUDIO0FP0SPI0C\S\1\
PORTC0AUDIO0FP0SPI0C\S\0\
PORTC0AUDIO0FP0SPI
RTC_AUDIO_FP_SPI
AIC23_I2S
DATA7
DATA4
DATA5
DATA6
DATA3
CLK
STP
NXT
DIR
DATA0
DATA1
DATA2
ULPI
AM3517 Peripherals (Part B)
I-
1
TV_VREF
PIR13601
R136
COR136
TV_OUT2
TV_VFB2
PIR13401
COR134
R134
RESERVED3
-
General Notes:
1.) JTAG RTCK is used for adaptive clocking, and is not essential
2.) The SYS_CLKOUT(1/2) pins are used as GPIOs
2.) The TV interface pins are not used - the feedback resistors are merely to prevent
floating inputs
GND
PIC120 1
RESERVED1
TV_OUT1
TV_VFB1
PIU90N21
Y4
PIU90Y4
AA1
PIU90AA1
AA2
PIU90AA2
BOOT_SW2
AA3
PIU90AA3
AB1
PIU90AB1
BOOT_SW1
AB2
PIU90AB2
AC1
PIU90AC1
AC2
PIU90AC2
AC3
SYS_BOOT0/GPIO_2
SYS_BOOT1/GPIO_3
SYS_BOOT2GPIO_4
SYS_BOOT3/GPIO_5
SYS_BOOT4/MMC2_DIR_DAT2/GPIO_6
SYS_BOOT5/MMC2_DIR_DAT3/GPIO_7
SYS_BOOT6/GPIO_8
SYS_BOOT7/GPIO_115
SYS_BOOT8/GPIO_169 PIU90AC3
w
n
HSUSB2_CLK
HSUSB2_STP
HSUSB2_DIR
HSUSB2_NXT
HSUSB2_DATA0
HSUSB2_DATA1
~
C120
COC120
U2
V1
N21
PIU90V1 RESERVED2
PIU90U2
To
,il
PIC120 2
PIR12701
SYS_ALTCLK
e
I I
illll
PIR12601
R126
10k
32K_CLK
48M_CLK
I
PIR1260 COR126 PIR1270COR127
VCC_1V2_PROC
PIU90K25
K25
SYS_XTALIN
H25
PIU90H25 SYS_XTALOUT
K24
PIU90K24 SYS_32K
SYS_CLKREQ/GPIO_1
SYS_nRESPWRON
SYS_nRESWARM/GPIO_30
SYS_nIRQ/GPIO_0
JTAG_EMU1/GPIO_31
JTAG_EMU0/GPIO_11
TV_OUT2
TV_OUT1
TV_VFB1
TV_VFB2
TV_VREF
HDQ_SIO/SYS_ALTCLK/I2C2_SCCBE/I2C3_SCCBE/GPIO_170
II
SYS_CLK
M24
PIU90M24
PIU90T25
PIU90Y2
Y2
Y3
PIU90Y3
Y1
PIU90Y1
R24
PIU90R24
T25
H24
K21
PIU90K21
K20
PIU90K20
H23
PIU90H23
H20
PIU90H20
PIU90H24
AillilIIII j
CLKS_IN
POCLKS0IN0SYS0CLKREQ
POCLKS0IN0SYS0CLK
POCLKS0IN048M0CLK
POCLKS0IN032K0CLK
POCLKS0IN
SYS_CLKREQ
TV_OUT2
TV_OUT1
TV_VFB1
TV_VFB2
TV_VREF
SYS_ALTCLK PIU90L25
L25
AD17
AE18
PIU90AE18
AD18
PIU90AD18
AC18
PIU90AC18
AB18
PIU90AB18
AA18
PIU90AA18
Y18
PIU90Y18
AE19
PIU90AE19
AD19
PIU90AD19
AB19
PIU90AB19
AE20
PIU90AE20
AD20
PIU90AD20
AC20
PIU90AC20
AB20
PIU90AB20
AE21
PIU90AE21
AD21
PIU90AD21
AC21
PIU90AC21
AE22
PIU90AE22
PIU90AD17
!Wll!IUJ
lAI!illlillill
PROC_CLKS
SYS_BOOT7
PIR1201 PIR1201 PIR1230
4k7
4k7
COR123
R123
4k7
ap
ETK_CLK/MCBSP5_CLKX/MMC3_CLK/HSUSB1_STP/GPIO_12/HSUSB1_TLL_STP
ETK_CTL/MMC3_CMD/HSUSB1_CLK/GPIO_13/MM_FSUSB1_RXDP/HSUSB1_TLL_CLK
ETK_D0/MCSPI3_SIMO/MMC3_DAT4/HSUSB1_DATA0/GPIO_14/MM_FSUSB1_RXRCV/HSUSB1_TLL_DATA0
ETK_D1/MCSPI3_SOMI/HSUSB1_DATA1/GPIO_15/MM_FSUSB1_TXSE0/HSUSB1_TLL_DATA1
ETK_D2/MCSPI3_CS0/HSUSB1_DATA2/GPIO_16/MM_FSUSB1_TXDAT/HSUSB1_TLL_DATA2
ETK_D3/MCSPI3_CLK/MMC3_DAT3/HSUSB1_DATA7/GPIO_17/HSUSB1_TLL_DATA7
ETK_D4/MCBSP5_DR/MMC3_DAT0/HSUSB1_DATA4/GPIO_18/HSUSB1_TLL_DATA4
ETK_D5/MCBSP5_FSX/MMC3_DAT1/HSUSB1_DATA5/GPIO_19/HSUSB1_TLL_DATA5
ETK_D6/MCBSP5_DX/MMC3_DAT2/HSUSB1_DATA6/GPIO_20/HSUSB1_TLL_DATA6
ETK_D7/MCSPI3_CS1/MMC3_DAT7/HSUSB1_DATA3/GPIO_21/MM_FSUSB1_TXEN_N/HSUSB1_TLL_DATA3
ETK_D8/SYS_DRM_MSECURE/MMC3_DAT6/HSUSB1_DIR/GPIO_22/HSUSB1_TLL_DIR
ETK_D9/SYS_SECURE_INDICATOR/MMC3_DAT5/HSUSB1_NXT/GPIO_23/MM_FSUSB1_RXDM/HSUSB1_TLL_NXT
ETK_D10/UART1_TX/HSUSB2_CLK/GPIO_24/HSUSB2_TLL_CLK
ETK_D11/MCSPI3_CLK/HSUSB2_STP/GPIO_25/MM_FSUSB2_RXDP/HSUSB2_TLL_STP
ETK_D12/HSUSB2_DIR/GPIO_26/HSUSB2_TLL_DIR
ETK_D13/HSUSB2_NXT/GPIO_27/MM_FSUSB2_RXDM/HSUSB2_TLL_NXT
ETK_D14/HSUSB2_DATA0/GPIO_28/MM_FSUSB2_RXRCV/HSUSB2_TLL_DATA0
ETK_D15/HSUSB2_DATA1/GPIO_29/MM_FSUSB2_TXSE0/HSUSB2_TLL_DATA1
C
R25
McBSP1_CLKR/MCSPI4_CLK/GPIO_156 PIU90R25
P21
McBSP1_FSR/GPIO_157 PIU90P21
P22
McBSP1_DX/MCSPI4_SIMO/MCBSP3_DX/GPIO_158 PIU90P22
1588_GPIO0
P23
McBSP1_DR/MCSPI4_SOMI/MCBSP3_DR/GPIO_159 PIU90P23
1588_GPIO1
P25
McBSP_CLKS/GPIO_160/UART1_CTS PIU90P25
1588_GPIO2
P24
McBSP1_FSX/MCSPI4_CS0/MCBSP3_FSX/GPIO_161 PIU90P24
1588_GPIO3
N24
McBSP1_CLKX/MCBSP3_CLKX/GPIO_162 PIU90N24
I2C
t
BOOT_BUF_EN
POBOOT0BUF0EN
RESPWRON
POR\E\S\P\W\R\O\N\
POETH0PWRDWN
ETH_PWRDWN
POP\W\R\0\O\F\F\0\I\N\T\
PWR_OFF_INT
COR122
R122
COR121
R121
PIR120 PIR120 PIR12301
JTAG_TDO
JTAG_nTRST
JTAG_TMS_TMSC
JTAG_TDI
JTAG_TCK
JTAG_RTCK
SYS_CLKOUT2/GPIO_186
SYS_CLKOUT1/GPIO_10
of
GND
VCC_3V3_PROC
GA0
GA1
PRSNT_M2C
PG_C2M
I2C
LRCOUT
LRCIN
BCLK
ADC_DOUT
DAC_DIN
YV
: v------lJ
D
153
VCC_3V3_PROC
T24
U24
PIU90U24
T22
PIU90T22
T23
PIU90T23
U25
PIU90U25
T21
PIU90T21
M25
PIU90M25
N25
PIU90N25
PIU90T24
11
C
~
II
PWR_FAIL_INT
POP\W\R\0\F\A\I\L\0\I\N\T\
PO15880CLK
1588_CLK
I
TDO
TRST
TMS
TDI
TCK
ty
G20
NC1 PIU90G20
G21
NC2 PIU90G21
H19
NC3 PIU90H19
K22
NC4 PIU90K22
K23
NC5 PIU90K23
L21
NC6 PIU90L21
L22
NC7 PIU90L22
L23
NC8 PIU90L23
L24
PIU90L24
NC9
F17
NC10 PIU90F17
--'-I
f
POPROC0JTAG0TMS
POPROC0JTAG0TDO
POPROC0JTAG0TDI
POPROC0JTAG0TCK
POPROC0JTAG0T\R\S\T\
POPROC0JTAG
PROC_JTAG
~
RMII_MDIO_DATA/CCDC_DATA8/GPIO_107
RMII_MDIO_CLK/CCDC_DATA9/GPIO_108
RMII_RXD0/CCDC_DATA10/GPIO_109
RMII_RXD1/CCDC_DATA11/GPIO_110
RMII_CRS_DV/CCDC_DATA12//GPIO_111
RMII_RXER/CCDC_DATA13//GPIO_167
RMII_TXD0/CCDC_DATA14//GPIO_126
RMII_TXD1/CCDC_DATA152//GPIO_112
RMII_TXEN/GPIO_113
RMII_50MHZ_CLK/GPIO_114
1!~JjJ(J
~ ~~1'1L,VrYTYu'n~rL'T~I
.J '
JTAG_BUS
I
MDIO_DATA
MDIO_CLK
RXD0
RXD1
CRS_DV
RXER
TXD0
TXD1
TXEN
50MHZ_CLK
er
si
A22
McBSP4_FSX/GPIO_155/MM_FSUSB3_TXEN_N PIU90A22
B23
McBSP4_CLKX/GPIO_152/MM_FSUSB3_TXSE0 PIU90B23
A23
McBSP4_DR/GPIO_153/MM_FSUSB3_RXRCV PIU90A23
B22
McBSP4_DX/GPIO_154/MM_FSUSB3_TXDAT PIU90B22
GA0
GA1
PRSNT_M2C
PG_C2M
I2C
110 0-
POETHER0RMII0TXEN
POETHER0RMII0TXD1
POETHER0RMII0TXD0
POETHER0RMII0RXER
POETHER0RMII0RXD1
POETHER0RMII0RXD0
POETHER0RMII0MDIO0DATA
POETHER0RMII0MDIO0CLK
POETHER0RMII0CRS0DV
POETHER0RMII050MHZ0CLK
POETHER0RMII
ETHER_RMII
JJ
AE6
PIU90AE6
AD6
PIU90AD6
Y7
PIU90Y7
AA7
PIU90AA7
AB7
PIU90AB7
AC7
PIU90AC7
AD7
PIU90AD7
AE7
PIU90AE7
AD8
PIU90AD8
AE8
PIU90AE8
A24
C23
PIU90C23
PIU90A24
C24
PIU90C24
B24
PIU90B24
D24
PIU90D24
I'
RMII
ni
v
U
CCDC_PCLK/GPIO_94
CCDC_FIELD/CCDC_DATA8/UART4_TX/I2C3_SCL/GPIO_95
CCDC_HD/UART4_RTS/GPIO_96
CCDC_VDUART4_CTS/GPIO_97
CCDC_WEN/CCDC_DATA9/UART4_RX//GPIO_98
CCDC_DATA0/I2C3_SDA/GPIO_99
CCDC_DATA1/GPIO_100
CCDC_DATA2/GPIO_101
CCDC_DATA3/GPIO_102
CCDC_DATA4/GPIO_103
CCDC_DATA5/GPIO_104
CCDC_DATA6/GPIO_105
CCDC_DATA7/GPIO_106
McBSP3_DX/UART2_CTS/GPIO_140
McBSP3_DR/UART2_RTS/GPIO_141
McBSP3_CLKX/UART2_TX/GPIO_142
McBSP3_FSX/UART2_RX/GPIO_143
D25
C25
B25
PIU90B25
PIU90C25
PIU90D25
I,~ I, ~), I
~
POPWR0KILL
PWR_KILL
FPGA_VCCINT_EN
FPGA_VCCO_AUX_EN
FPGA_VCCMGT_EN
FMC0_SUPPLY_EN
FMC0_AUX_EN
FMC1_SUPPLY_EN
FMC1_AUX_EN
PIU90AD2
AD2
AD1
PIU90AD1
AE2
PIU90AE2
AD3
PIU90AD3
AE3
PIU90AE3
AD4
PIU90AD4
AE4
PIU90AE4
AC5
PIU90AC5
AD5
PIU90AD5
AE5
PIU90AE5
Y6
PIU90Y6
AB6
PIU90AB6
AC6
PIU90AC6
FMC_I2C_SCL PIU90W4
W4
I2C3_SCL/GPIO_184
FMC_I2C_SDAPIU90W5
W5
I2C3_SDA/GPIO_185
I2C2_SCL/GPIO_168
I2C2_SDA/GPIO_183
McBSP2_FSX/GPIO_116
McBSP2_CLKX/GPIO_117
McBSP2_DR/GPIO_118
McBSP2_DX/GPIO_119
AB16
AA16
AE17
PIU90AE17
PIU90AA16
PIU90AB16
AC16
PIU90AC16
AD16
PIU90AD16
II I,
DCD
DTR
DSR
RI
INVALID
W2
PIU90W2
I2C1_SDA
MCSPI2_CLK/HSUSB2_TLL_DATA7/HSUSB2_DATA7/GPIO_178
MCSPI2_SIMO/GPT9_PWM_EVT/HSUSB2_TLL_DATA4/HSUSB2_DATA4/GPIO_179
MCSPI2_SOMI/GPT10_PWM_EVT/HSUSB2_TLL_DATA5/HSUSB2_DATA5/GPIO_180
MCSPI2_CS0/GPT11_PWM_EVT/HSUSB2_TLL_DATA6/HSUSB2_DATA6/GPIO_181
MCSPI2_CS1/GPT8_PWM_EVT/HSUSB2_TLL_DATA3/HSUSB2_DATA3/GPIO_182/MM_FSUSB2_TXEN_N
, I,
POSUPPLY0EN0FPGA0VCCO0AUX0EN
POSUPPLY0EN0FPGA0VCCMGT0EN
POSUPPLY0EN0FPGA0VCCINT0EN
POSUPPLY0EN0FMC10SUPPLY0EN
POSUPPLY0EN0FMC10AUX0EN
POSUPPLY0EN0FMC00SUPPLY0EN
POSUPPLY0EN0FMC00AUX0EN
POSUPPLY0EN
SUPPLY_EN
-i
RS232_CRTL
SCL
SDA
W1
PIU90W1
PIU90V5
V5
UART1_TX/GPIO_148
UART1_RTS/GPIO_149
UART1_CTS/GPIO_150
UART1_RX/MCBSP1_CLKR/MCSPI4_CLK/GPIO_151
V4
PIU90V4
I2C1_SCL
PIU90W20
PIU90Y20
Y20
W20
Y19
PIU90Y19
AA19
PIU90AA19
HSUSB2_CLK
HSUSB2_STP
HSUSB2_NXT
HSUSB2_DIR
HSUSB2_DATA0
HSUSB2_DATA1
1'--->
PORS2320CTRL0RI
PORS2320CTRL0I\N\V\A\L\I\D\
PORS2320CTRL0DTR
PORS2320CTRL0DSR
PORS2320CTRL0DCD
PORS2320CTRL
RS232_CTRL
PODDC0I2C0SDA
PODDC0I2C0SCL
PODDC0I2C
DDC_I2C
SCL
SDA
COR118 DBG0_RX
R118
4k7 DBG0_CTS
DBG0_RTS
DBG0_TX
SCLK
MOSI
MISO
CS0
CS1
CS2
SPI_3CH
7
~'
POI2C0PWR0MAN0SDA
POI2C0PWR0MAN0SCL
POI2C0PWR0MAN
I2C_PWR_MAN
4k7
4k7
4k7
PIR1 802
PIR1 501 PIR1601 PIR1701 PIR1801
COR117
R117
PIR1 702
COR116
R116
PIR1 602
~VVv----L1
COR115
R115
rl
PIR1 502
I-
I2C
U_LED_1
6
r!AlJl'1l!ILJli
AI!JillAillJll!
AM3517ZCN
AE14
MCSPI1_CLK/MMC2_DAT4/GPIO_171 PIU90AE14
AD15
MCSPI1_SIMO/MMC2_DAT5/GPIO_172 PIU90AD15
AC15
MCSPI1_SOMI/MMC2_DAT6/GPIO_173 PIU90AC15
AB15
MCSPI1_CS0/MM2_DAT7/GPIO_174 PIU90AB15
AD14
MCSPI1_CS1/MMC3_CMD/GPIO_175 PIU90AD14
AE15
MCSPI1_CS2/MMC3_CLK/GPIO_176 PIU90AE15
AE16
MCSPI1_CS3/HSUSB2_TLL_DATA2/HSUSB2_DATA2/GPIO_177/MM_FSUSB2_TXDAT PIU90AE16
5
ll
POUSER0LED01
USER_LED_1
j
USB0_DP/UART3_RX_IRRX
USB0_DM/UART3_TX_IRTX
G24
PIU90G24
USB0_VBUS
G25
PIU90G25 USB0_ID
E25
PIU90E25 USB0_DRVVBUS/UART3_TX_IRTX
U_LED_0PIU90V2
V2
HECC1_TXD/UART3_RX_IRRX/GPIO_130
U_LED_1PIU90V3
V3
HECC1_RXD/UART3_RTS_SD/GPIO_131
F25
F24
PIU90F24
PIU90F25
COU9B
U9B
4
I
B
A
U_LED_0
DP
DM
VBUS
ID
DRVVBUS
USB_OTG_BUS
y
POUSER0LED00
USER_LED_0
POUSB0OTG0VBUS
POUSB0OTG0ID
POUSB0OTG0DRVVBUS
POUSB0OTG0DP
POUSB0OTG0DM
POUSB0OTG
USB_OTG
DBG0_RX
DBG0_TX
DBG0_RTS
DBG0_CTS
3
I
VCC_3V3_PROC
RX
TX
RTS
CTS
r======~~~~
~ ", , HI u~~u~ v
PODBG0UART00TX
PODBG0UART00RX
PODBG0UART00RTS
PODBG0UART00CTS
PODBG0UART0
DBG_UART0
2
_
SYS_BOOT[7..0]
I-
I-
I-
I-
D
C
B
A
D
C
B
A
PIU90V16
V16
V15
PIU90V15
V11
PIU90V11
V10
PIU90V10
U16
PIU90U16
U15
PIU90U15
U11
PIU90U11
U10
PIU90U10
T18
PIU90T18
T17
PIU90T17
T9
PIU90T9
T8
PIU90T8
R18
PIU90R18
R17
PIU90R17
R9
PIU90R9
R8
PIU90R8
M18
PIU90M18
L18
PIU90L18
L9
PIU90L9
L8
PIU90L8
K18
PIU90K18
K17
PIU90K17
K9
PIU90K9
K8
PIU90K8
J16
PIU90J16
J15
PIU90J15
J11
PIU90J11
J10
PIU90J10
H15
PIU90H15
H11
PIU90H11
H10
PIU90H10
VCC_1V8_PROC
Y9
PIU90Y9
W18
PIU90W18
U20
PIU90U20
R5
PIU90R5
H16
PIU90H16
H8
PIU90H8
G17
PIU90G17
G16
PIU90G16
G14
PIU90G14
G13
PIU90G13
G11
PIU90G11
G10
PIU90G10
G8
PIU90G8
F16
PIU90F16
F13
PIU90F13
F11
PIU90F11
F10
PIU90F10
F8
PIU90F8
N22
PIU90N22
1
VDDS1
VDDS2
VDDS3
VDDS4
VDDS5
VDDS6
VDDS7
VDDS8
VDDS9
VDDS10
VDDS11
VDDS12
VDDS13
VDDS14
VDDS15
VDDS16
VDDS17
VDDS18
VDDS19
VDD_CORE1
VDD_CORE2
VDD_CORE3
VDD_CORE4
VDD_CORE5
VDD_CORE6
VDD_CORE7
VDD_CORE8
VDD_CORE9
VDD_CORE10
VDD_CORE11
VDD_CORE12
VDD_CORE13
VDD_CORE14
VDD_CORE15
VDD_CORE16
VDD_CORE17
VDD_CORE18
VDD_CORE19
VDD_CORE20
VDD_CORE21
VDD_CORE22
VDD_CORE23
VDD_CORE24
VDD_CORE25
VDD_CORE26
VDD_CORE27
VDD_CORE28
VDD_CORE29
VDD_CORE30
VDD_CORE31
COU9C
U9C
1
ty
er
si
ni
v
U
2
of
e
ap
C
To
w
n
3
PIU90AE25 PIU90AE1 PIU90V18 PIU90V17 PIU90V14 PIU90V13 PIU90V12 PIU90V PIU90V8 PIU9018 PIU9017 PIU9014 PIU9013 PIU9012 PIU90 PIU908 PIU90T14 PIU90T13 PIU90T12 PIU90R16 PIU90R15 PIU90R14 PIU90R13 PIU90R12 PIU90R1 PIU90R1 PIU90P18 PIU90P17 PIU90P16 PIU90P15 PIU90P14 PIU90P13 PIU90P12 PIU90P1 PIU90P1 PIU90P PIU90P8 PIU90N18 PIU90N17 PIU90N14 PIU90N13 PIU90N12 PIU90N PIU90N8 PIU90M17 PIU90M16 PIU90M15 PIU90M14 PIU90M13 PIU90M12 PIU90M1 PIU90M1 PIU90M PIU90M8 PIU90L17 PIU90L16 PIU90L15 PIU90L14 PIU90L13 PIU90L12 PIU90L1 PIU90L1 PIU90K14 PIU90K13 PIU90K12 PIU90J18 PIU90J17 PIU90J14 PIU90J13 PIU90J12 PIU90J PIU90J8 PIU90H14 PIU90H13 PIU90H12 PIU90H PIU90A25 PIU90A1 PIU90N23
PIC12 02
PIC12 01
CAP_SRAM_MPU
CAP_SRAM_CORE
100n
C122
COC122
C123
COC123
100n
GND
PIC12302
PIC12301
PIC12402
PIC12401
C124
COC124
220n
2
CAP_USBPHY
GND
3
Date:
File:
A4
Size
Title
CAP_SRAM_MPU
CAP_SRAM_CORE
VCC_1V8_PROC
VCC_3V3_PROC
GND
PIU90AA15
PIU90E16
4
Sheet 36 of
Drawn By:
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
29/03/2011
C:\Users\..\am3517_power.SchDoc
RHINO
Number
Project
AM3517 Power
AA13
E17
PIU90E17
AA12
PIU90AA12
PIU90AA13
PIU90Y12
PIU90Y13
Y13
Y12
Y10
PIU90Y10
W16
PIU90W16
W15
PIU90W15
W13
PIU90W13
W12
PIU90W12
W10
PIU90W10
W9
PIU90W9
W6
PIU90W6
V7
PIU90V7
V6
PIU90V6
U19
PIU90U19
T20
PIU90T20
T19
PIU90T19
T7
PIU90T7
T6
PIU90T6
R7
PIU90R7
R6
PIU90R6
P20
PIU90P20
P19
PIU90P19
N19
PIU90N19
N7
PIU90N7
N6
PIU90N6
M7
PIU90M7
M6
PIU90M6
M5
PIU90M5
L19
PIU90L19
K19
PIU90K19
K7
PIU90K7
K6
PIU90K6
K5
PIU90K5
J7
PIU90J7
H18
PIU90H18
H17
PIU90H17
Y15
PIU90Y15
Y16
PIU90Y16
4
1.0
65
Simon Scott
Revision
E16
AA15
VCC_1V8_PROC_DPLL
N20
PIU90N20
F23
PIU90F23 VCC_3V3_PROC_USB
G22
PIU90G22 VCC_1V8_PROC_DPLL
F22
PIU90F22
CAP_USBPHY
L20
VDDSOSC PIU90L20 VCC_1V8_PROC
H21
VDDA_DAC PIU90H21 VCC_1V8_PROC_DPLL
H22
VSSA_DAC PIU90H22
J25
VSSOSC PIU90J25
VDDS_SRAM_MPU
VDDS_SRAM_CORE_BG0
CAP_VDD_SRAM_MPU
CAP_VDD_SRAM_CORE
VDDS_DPLL_MPU_USBHOST
VDDS_DPLL_PER_CORE
VDDA3P3V_USBPHY
VDDA1P8V_USBPHY
CAP_VDDA1P2LDO_USBPHY
VDDSHV1
VDDSHV2
VDDSHV3
VDDSHV4
VDDSHV5
VDDSHV6
VDDSHV7
VDDSHV8
VDDSHV9
VDDSHV10
VDDSHV11
VDDSHV12
VDDSHV13
VDDSHV14
VDDSHV15
VDDSHV16
VDDSHV17
VDDSHV18
VDDSHV19
VDDSHV20
VDDSHV21
VDDSHV22
VDDSHV23
VDDSHV24
VDDSHV25
VDDSHV26
VDDSHV27
VDDSHV28
VDDSHV29
VDDSHV30
VDDSHV31
VDDSHV32
VDDSHV33
VDDSHV34
VDDSHV35
VDDSHV36
VDDSHV37
AM3517ZCN
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
AE25
AE1
V18
V17
V14
V13
V12
V9
V8
U18
U17
U14
U13
U12
U9
U8
T14
T13
T12
R16
R15
R14
R13
R12
R11
R10
P18
P17
P16
P15
P14
P13
P12
P11
P10
P9
P8
N18
N17
N14
N13
N12
N9
N8
M17
M16
M15
M14
M13
M12
M11
M10
M9
M8
L17
L16
L15
L14
L13
L12
L11
L10
K14
K13
K12
J18
J17
J14
J13
J12
J9
J8
H14
H13
H12
H9
A25
A1
N23
VCC_1V2_PROC
154
D
C
B
A
A
I
III'I'
I
VCC_1V8_PROC
GND
3
of
155
I
GND
100n
Decoupling cap for VDDS_DPLL_PER_CORE
2
3
COC118
C118
100n
GND
PIC1 802
PIC1 801
4
Sheet 37 of
Drawn By:
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
29/03/2011
C:\Users\..\am3517_decoupling.SchDoc
RHINO
Number
Project
1.0
65
Simon Scott
Revision
Decoupling cap for VDDA3P3V_USBPHY
VCC_3V3_PROC_USB
Decoupling cap for VDDS_DPLL_MPU_USBHOST
AM3517 Supply Decoupling Caps
---
Date:
File:
A4
Size
Title
Decoupling cap for VDDA1P8V_USBPHY
w
n
COC114
C114
100n
GND
PIC1 402
PIC1 401
---
1
GND
100n
COC117
C117
PIC1 702
PIC1 701
HHII'
COC116
C116
PIC1 602
PIC1 601
To
Decoupling cap for VDDS_OSC
VCC_1V8_PROC_DPLL
HHII'
Layout Notes:
1.) Each decoupling capacitor should be connected to a group of 1, 2 or 3 adjacent power balls, and then to the closest ground ball.
2.) In the case of interconnected power pins, first connect the decoupling cap, then interconnect the pins.
Decoupling cap for VDDS_DPLL_PER_CORE
e
100n
COC113
C113
GND
PIC1 302
PIC1 301
VCC_1V8_PROC_DPLL
Decoupling cap for VDDS_SRAM_CORE_BG0
VCC_1V8_PROC_DPLL
HHII'
GND
100n
COC115
C115
HHII'
PIC1 502
PIC1 501
100n
COC112
C112
GND
PIC1 20
PIC1 201
HHII'
VCC_1V8_PROC_DPLL
Decoupling cap for VDDS_SRAM_MPU
HHII'
VCC_1V8_PROC
ap
Bypass capacitors for AM3517 VDDSHV pins:
1.) Place caps close to VDDS_HV pins
2.) Preference should be given to the placement of the 100nF caps over
the 10uF cap
Bypass capacitors for AM3517 VDD_CORE pins:
1.) Place caps close to VDD_CORE pins
2.) Preference should be given to the placement of the 100nF caps over
the 10uF cap
C
4
Bypass capacitors for AM3517 VDDS pins:
1.) Place caps as close to the VDDS pins as possible (prefereably
within 7mm)
2.) Preference should be given to the placement of the 100nF caps over
the 10uF caps
HHII'
GND
100n
COC111
C111
HHII'
PIC1 102
PIC1 101
VCC_1V8_PROC
"
II
"
II
"
II
"
II
"
II
"
II
"
II
"
II
"
II
"
II
"
II
"
II
"
II
"
II
"
II
"
A
B
C
D
I
D
ty
er
si
II
COC101 PIC102 COC102
COC104 PIC105 2 COC105
COC106 PIC107 2 C107
COC107 PIC10802 COC108
COC109 PIC1 0 2 C110
COC110
PIC9502 COC95
C95 PIC9602 COC96
C96 PIC9702 COC97
C97 PIC9802 COC98
C98 PIC9 02 COC99
C99 PIC10 02 COC100
C100 PIC10 2 C101
C102 PIC10302 COC103
C103 PIC104 2 C104
C105 PIC106 2 C106
C108 PIC109 2 C109
PIC9501 10u PIC9601 100n PIC9701 100n PIC9801 100n PIC9 01 100n PIC10 01 100n PIC10 1 100n PIC102 1 100n PIC10301 100n PIC104 1 100n PIC105 1 100n PIC106 1 100n PIC107 1 100n PIC10801 100n PIC109 1 100n PIC1 0 1 100n
VCC_3V3_PROC
GND
III'I'
I
C
ni
v
U
II
COC85 PIC8602 COC86
COC88 PIC8902 COC89
COC90 PIC9102 C91
COC91 PIC9202 COC92
COC93 PIC9402 C94
COC94
C79 PIC80 2 COC80
C80 PIC8102 COC81
C81 PIC8202 COC82
C82 PIC8302 COC83
C83 PIC8402 COC84
C84 PIC8502 C85
C86 PIC8702 COC87
C87 PIC8 02 C88
C89 PIC90 2 C90
C92 PIC9302 C93
PIC7902 COC79
PIC7901 10u PIC80 1 100n PIC8101 100n PIC8201 100n PIC8301 100n PIC8401 100n PIC8501 100n PIC8601 100n PIC8701 100n PIC8 01 100n PIC8901 100n PIC90 1 100n PIC9101 100n PIC9201 100n PIC9301 100n PIC9401 100n
VCC_1V2_PROC
GND
III'I'
"
II
"
II
"
II
"
II
"
II
"
II
"
II
"
II
"
II
"
II
"
II
"
II
"
II
"
II
"
II
"
B
2
II
COC61 PIC6202 COC62
COC64 PIC6502 COC65
COC66 PIC6702 C67
COC67 PIC6802 COC68
COC69 PIC70 2 C70
COC70 PIC7102 C71
COC71 PIC7202 C72
COC72 PIC7302 COC73
COC74 PIC7502 C75
COC75 PIC7602 C76
COC76 PIC7 02 C77
COC77 PIC7802 C78
COC78
PIC5 02 COC55
C55 PIC5602 COC56
C56 PIC5702 COC57
C57 PIC5802 COC58
C58 PIC5902 COC59
C59 PIC60 2 COC60
C60 PIC6102 C61
C62 PIC6302 COC63
C63 PIC6402 C64
C65 PIC6 02 C66
C68 PIC6902 C69
C73 PIC7402 C74
PIC5 01 10u PIC5601 10u PIC5701 10u PIC5801 10u PIC5901 100n PIC60 1 100n PIC6101 100n PIC6201 100n PIC6301 100n PIC6401 100n PIC6501 100n PIC6 01 100n PIC6701 100n PIC6801 100n PIC6901 100n PIC70 1 100n PIC7101 100n PIC7201 100n PIC7301 100n PIC7401 100n PIC7501 100n PIC7601 100n PIC7 01 100n PIC7801 100n
VCC_1V8_PROC
1
"
II
"
II
"
II
"
II
"
II
"
II
"
II
"
II
"
II
"
II
"
II
"
II
"
II
"
II
"
II
"
II
"
II
"
II
"
II
"
II
"
II
"
II
"
II
"
I
r-
~
~
u
,,'
"
2_.
....
J
\
CK_N
CK_P
CKE
ODT
DQ[15..0]
UDM
LDM
UDQS_N
UDQS_P
LDQS_N
LDQS_P
BA[2..0]
A[13..0]
VREF_0V9
III
CS
WE
CAS
RAS
I
u
I
2
VREF_0V9
I II
..••
1
DDR2_BUS
CS
WE
CAS
RAS
I
of
e
ap
C
To
3
w
n
3
156
r-
4
PIC12502
COC125
C125
PIC12501 100n
1.0
PIC12602
C126
COC126
PIC12601 100n
65
Simon Scott
Revision
GND
Sheet 38 of
Drawn By:
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
29/03/2011
C:\Users\..\am3517_ram.SchDoc
RHINO
Number
Project
PIR140 1
R140
COR140
1k
PIR13901
PIR140 2
R139
1k
PIR13902COR139
VCC_1V8_PROC
POPROC0DDR20BUS0W\E\
POPROC0DDR20BUS0VREF00V9
POPROC0DDR20BUS0UDQS10P
POPROC0DDR20BUS0UDQS10N
POPROC0DDR20BUS0UDQS00P
POPROC0DDR20BUS0UDQS00N
POPROC0DDR20BUS0UDM1
POPROC0DDR20BUS0UDM0
POPROC0DDR20BUS0R\A\S\
POPROC0DDR20BUS0ODT
POPROC0DDR20BUS0LDQS10P
POPROC0DDR20BUS0LDQS10N
POPROC0DDR20BUS0LDQS00P
POPROC0DDR20BUS0LDQS00N
POPROC0DDR20BUS0LDM1
POPROC0DDR20BUS0LDM0
POPROC0DDR20BUS0DQ100150000
POPROC0DDR20BUS0DQ1015
POPROC0DDR20BUS0DQ1014
POPROC0DDR20BUS0DQ1013
POPROC0DDR20BUS0DQ1012
POPROC0DDR20BUS0DQ1011
POPROC0DDR20BUS0DQ1010
POPROC0DDR20BUS0DQ109
POPROC0DDR20BUS0DQ108
POPROC0DDR20BUS0DQ107
POPROC0DDR20BUS0DQ106
POPROC0DDR20BUS0DQ105
POPROC0DDR20BUS0DQ104
POPROC0DDR20BUS0DQ103
POPROC0DDR20BUS0DQ102
POPROC0DDR20BUS0DQ101
POPROC0DDR20BUS0DQ100
POPROC0DDR20BUS0DQ000150000
POPROC0DDR20BUS0DQ0015
POPROC0DDR20BUS0DQ0014
POPROC0DDR20BUS0DQ0013
POPROC0DDR20BUS0DQ0012
POPROC0DDR20BUS0DQ0011
POPROC0DDR20BUS0DQ0010
POPROC0DDR20BUS0DQ009
POPROC0DDR20BUS0DQ008
POPROC0DDR20BUS0DQ007
POPROC0DDR20BUS0DQ006
POPROC0DDR20BUS0DQ005
POPROC0DDR20BUS0DQ004
POPROC0DDR20BUS0DQ003
POPROC0DDR20BUS0DQ002
POPROC0DDR20BUS0DQ001
POPROC0DDR20BUS0DQ000
POPROC0DDR20BUS0CKE
POPROC0DDR20BUS0CK0P
POPROC0DDR20BUS0CK0N
POPROC0DDR20BUS0C\S\
POPROC0DDR20BUS0C\A\S\
POPROC0DDR20BUS0BA020000
POPROC0DDR20BUS0BA2
POPROC0DDR20BUS0BA1
POPROC0DDR20BUS0BA0
POPROC0DDR20BUS0A0130000
POPROC0DDR20BUS0A13
POPROC0DDR20BUS0A12
POPROC0DDR20BUS0A11
POPROC0DDR20BUS0A10
POPROC0DDR20BUS0A9
POPROC0DDR20BUS0A8
POPROC0DDR20BUS0A7
POPROC0DDR20BUS0A6
POPROC0DDR20BUS0A5
POPROC0DDR20BUS0A4
POPROC0DDR20BUS0A3
POPROC0DDR20BUS0A2
POPROC0DDR20BUS0A1
POPROC0DDR20BUS0A0
POPROC0DDR20BUS
PROC_DDR2_BUS
r-
Date:
File:
A4
\
AM3517 DDR2 RAM (top level)
VREF_0V9
4
jl-
Size
Title
CS
WE
CAS
RAS
CK_N
CK_P
CKE
ODT
DQ1_[15..0]
UDM1
LDM1
UDQS1_N
UDQS1_P
LDQS1_N
LDQS1_P
DQ0_[15..0]
UDM0
LDM0
UDQS0_N
UDQS0_P
LDQS0_N
LDQS0_P
BA[2..0]
A[13..0]
PROC_DDR2_BUS
III
ddr2_bus
ty
er
si
ODT
CK_N
CK_P
CKE
ni
v
U
I,
I
I"
D
DDR2_BUS
BA[2..0]
A[13..0]
DQ[15..0]
UDM
LDM
UDQS_N
UDQS_P
LDQS_N
LDQS_P
2
l
C
ram_ddr2_1
ram_ddr2
ram_ddr2_0
ram_ddr2
ddr2_bus
\
B
A
1
(
--II
J
""
~••
D
C
B
A
--- -
III
2
I
PIR35702COR2
PIR35701
PIR35601
R357
4k7
VREF_0V9_DDR2
,,
,,
,,
,,
,,
j-11
1
'
GND
j-11
GND
1
'
157
I
BA[2..0]
A[13..0]
CK_N
CK_P
2
PIU690L3
L1
PIU690L1
BA0
BA1
BA2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
NC
of
e
ap
C
r-r--
r--
-
To
II'
~
GND
3
NC
NC
NC
NC
E2
R3
R7
PIU690R7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
LDQS
LDQS
UDQS
UDQS
COR7
R345
R346
COR8
PIR34601
COR9
R347
PIR34701
COR10
R348
PIR34801
COR11
R349
PIR34901
COR12
R350
PIR35001
R351
COR13
PIR35101
COR14
R352
PIR35201
COR15
R353
PIR35301
COR16
R354
PIR35401
COR17
R355
PIR35501
R358
COR18
PIR35801
COR19
R359
PIR35901
COR20
R360
PIR36001
COR21
R361
PIR36101
R362
COR22
PIR36201
G8
G2
PIU690G2
H7
PIU690H7
H3
PIU690H3
H1
PIU690H1
H9
PIU690H9
F1
PIU690F1
F9
PIU690F9
C8
PIU690C8
C2
PIU690C2
D7
PIU690D7
D3
PIU690D3
D1
PIU690D1
D9
PIU690D9
B1
PIU690B1
B9
PIU690B9
Hf-f- Yf-- YII'
Date:
File:
A4
Size
Title
LDQS_N
LDQS_P
22R
22R
22R
22R
PIR34602
22R
PIR34702
22R
PIR34802
22R
PIR34902
22R
PIR35002
22R
PIR35102
22R
PIR35202
22R
PIR35302
22R
PIR35402
22R
PIR35502
22R
PIR35802
22R
PIR35902
22R
PIR36002
22R
PIR36102
22R
PIR36202
PIR34502
PIR34402
PIR34302
DQ[15..0]
Hf-Hf-Hf-Hf-Hf-Hf--
~f--
4
Sheet 39 of
Drawn By:
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
29/03/2011
C:\Users\..\ram_ddr2.SchDoc
RHINO
Number
Project
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
UDQS_N
UDQS_P
PIR34202
22R
22R
PIR34102
DDR2 RAM
PIR34501
COR5
R343
COR6
R344
PIU690G8
PIR34401
E8
F7
PIR34301
COR3
R341
COR4
R342
PIU690F7
PIR34201
PIU690E8
PIR34101
PIU690B7
UDM
LDM
PIU690A8
A8
B7
B3
UDM
F3
LDM PIU690F3
PIU690B3
PIU690R3
PIU690E2
A2
PIU690A2
COU1
U69
W971GG6JB-25
VREF_0V9_DDR2
COC1
C450
100n
GND
w
n
PIU690A3 PIU690E3 PIU690J3 PIU690N1 PIU690P9 PIU690A7 PIU690B2 PIU690B8 PIU690D2 PIU690D8 PIU690E7 PIU690F2 PIU690F8 PIU690H2 PIU690H8 PIU690J7
-
-
1
L2
L3
BA0
BA1
BA2
PIU690L2
M8
M3
PIU690M3
M7
PIU690M7
N2
PIU690N2
N8
PIU690N8
N3
PIU690N3
N7
PIU690N7
P2
PIU690P2
P8
PIU690P8
P3
PIU690P3
M2
PIU690M2
P7
PIU690P7
R2
PIU690R2
R8
PIU690R8
PIU690M8
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
PIC450 2
PIC450 1
1.0
65
Simon Scott
Revision
Layout Notes:
1.) Place 100nF bypass capacitors within 7mm of IC pins
2.) Place the 22 ohm termination resistors as close to the IC pins as possible
3.) CK, UDQS and LDQS must be routed as a differential pairs
4.) All traces (except the power supplies) must have a 50 ohm single ended impedance
4
-
GND
ty
L8
CS
K3
WE
L7
PIU690L7 CAS
K7
PIU690K7 RAS
PIU690K3
PIU690L8
r--
r-1f--
~L
II
C451 PIC4520 COC3
C452 PIC45302 COC4
C453 PIC45 02 COC5
C454 PIC45 02 COC6
C455 PIC45602 COC7
C456 PIC45702 C457
C458 PIC45902 C459
C461
COC8
COC10
COC11
PIC45102 COC2
PIC45802 COC9
PIC460 2 C460
PIC46102 COC12
PIC4510 22u PIC45201 100n PIC45301 100n PIC45 01 100n PIC45 01 100n PIC45601 100n PIC45701 100n PIC45801 100n PIC45901 100n PIC460 1 100n PIC46101 100n
ODT
K8
PIU690K8 CK
J8
PIU690J8 CK
K2
PIU690K2 CKE
K9
PIU690K9
er
si
J1
PIU690A1 PIU690E1 PIU690J PIU690M PIU690R1 PIU690A9 PIU690C1 PIU690C3 PIU690C7 PIU690C PIU690E9 PIU690G1 PIU690G3 PIU690G7 PIU690G PIU690J1 PIU690J2
VCC_1V8_PROC
3
J2
r-r--
D
I
;,
CKE
- --- -
VREF_0V9
CS
WE
CAS
RAS
(l
PIR35602COR1
R356
4k7
I
CS
WE
CAS
RAS
--- ---
CKE
ODT
i 100R_DIFF
ni
v
UDQS_N
UDQS_P
LDQS_N
LDQS_P
U
-- -
VCC_1V8_PROC
ODT
CK_N
CK_P
CKE
ODT
UDM
LDM
DQ[15..0]
i 50_OHM
---
III
C
PODDR20BUS0W\E\0ram0ddr200
PODDR20BUS0VREF00V90ram0ddr200
PODDR20BUS0UDQS0ram0ddr2000P
PODDR20BUS0UDQS0ram0ddr2000N
PODDR20BUS0UDM0ram0ddr200
PODDR20BUS0R\A\S\0ram0ddr200
PODDR20BUS0ODT0ram0ddr200
PODDR20BUS0LDQS0ram0ddr2000P
PODDR20BUS0LDQS0ram0ddr2000N
PODDR20BUS0LDM0ram0ddr200
PODDR20BUS0DQ01500000ram0ddr200
PODDR20BUS0DQ150ram0ddr200
PODDR20BUS0DQ140ram0ddr200
PODDR20BUS0DQ130ram0ddr200
PODDR20BUS0DQ120ram0ddr200
PODDR20BUS0DQ110ram0ddr200
PODDR20BUS0DQ100ram0ddr200
PODDR20BUS0DQ90ram0ddr200
PODDR20BUS0DQ80ram0ddr200
PODDR20BUS0DQ70ram0ddr200
PODDR20BUS0DQ60ram0ddr200
PODDR20BUS0DQ50ram0ddr200
PODDR20BUS0DQ40ram0ddr200
PODDR20BUS0DQ30ram0ddr200
PODDR20BUS0DQ20ram0ddr200
PODDR20BUS0DQ10ram0ddr200
PODDR20BUS0DQ00ram0ddr200
PODDR20BUS0CKE0ram0ddr200
PODDR20BUS0CK0ram0ddr2000P
PODDR20BUS0CK0ram0ddr2000N
PODDR20BUS0C\S\0ram0ddr200
PODDR20BUS0C\A\S\0ram0ddr200
PODDR20BUS0BA0200000ram0ddr200
PODDR20BUS0BA20ram0ddr200
PODDR20BUS0BA10ram0ddr200
PODDR20BUS0BA00ram0ddr200
PODDR20BUS0A01300000ram0ddr200
PODDR20BUS0A130ram0ddr200
PODDR20BUS0A120ram0ddr200
PODDR20BUS0A110ram0ddr200
PODDR20BUS0A100ram0ddr200
PODDR20BUS0A90ram0ddr200
PODDR20BUS0A80ram0ddr200
PODDR20BUS0A70ram0ddr200
PODDR20BUS0A60ram0ddr200
PODDR20BUS0A50ram0ddr200
PODDR20BUS0A40ram0ddr200
PODDR20BUS0A30ram0ddr200
PODDR20BUS0A20ram0ddr200
PODDR20BUS0A10ram0ddr200
PODDR20BUS0A00ram0ddr200
PODDR20BUS0ram0ddr200
DDR2_BUS
UDM
LDM
UDQS_N
UDQS_P
LDQS_N
LDQS_P
DQ[15..0]
BA[2..0]
lJJJ--- - - -
BA[2..0]
A[13..0]
A1
E1
J9
M9
R1
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
A[13..0]
_9_______________" _
,
"
B
I
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DDR2_BUS
:$L _
I
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
9, __________
I
I I
A3
E3
J3
N1
P9
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
,
VREF
,,
,,
,,
VDDL
2
r
VSSDL
HH II.
nn
J7
A
1
I
c-
c-
c-
D
C
B
A
--- -
III
2
I
PIR37902COR2
PIR37901
PIR37801
R379
4k7
VREF_0V9_DDR2
,,
,,
,,
,,
,,
j-11
1
'
GND
j-11
GND
1
'
158
I
BA[2..0]
A[13..0]
CK_N
CK_P
2
PIU700L3
L1
PIU700L1
BA0
BA1
BA2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
NC
of
e
ap
C
r-r--
r--
-
To
II'
~
GND
3
NC
NC
NC
NC
E2
R3
R7
PIU700R7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
LDQS
LDQS
UDQS
UDQS
COR7
R367
R368
COR8
PIR36801
COR9
R369
PIR36901
COR10
R370
PIR37001
COR11
R371
PIR37101
COR12
R372
PIR37201
R373
COR13
PIR37301
COR14
R374
PIR37401
COR15
R375
PIR37501
COR16
R376
PIR37601
COR17
R377
PIR37701
R380
COR18
PIR38001
COR19
R381
PIR38101
COR20
R382
PIR38201
COR21
R383
PIR38301
R384
COR22
PIR38401
G8
G2
PIU700G2
H7
PIU700H7
H3
PIU700H3
H1
PIU700H1
H9
PIU700H9
F1
PIU700F1
F9
PIU700F9
C8
PIU700C8
C2
PIU700C2
D7
PIU700D7
D3
PIU700D3
D1
PIU700D1
D9
PIU700D9
B1
PIU700B1
B9
PIU700B9
Hf-f- Yf-- YII'
Date:
File:
A4
Size
Title
LDQS_N
LDQS_P
22R
22R
22R
22R
PIR36802
22R
PIR36902
22R
PIR37002
22R
PIR37102
22R
PIR37202
22R
PIR37302
22R
PIR37402
22R
PIR37502
22R
PIR37602
22R
PIR37702
22R
PIR38002
22R
PIR38102
22R
PIR38202
22R
PIR38302
22R
PIR38402
PIR36702
PIR36602
PIR36502
DQ[15..0]
Hf-Hf-Hf-Hf-Hf-Hf--
~f--
4
Sheet 40 of
Drawn By:
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
29/03/2011
C:\Users\..\ram_ddr2.SchDoc
RHINO
Number
Project
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
UDQS_N
UDQS_P
PIR36402
22R
22R
PIR36302
DDR2 RAM
PIR36701
COR5
R365
COR6
R366
PIU700G8
PIR36601
E8
F7
PIR36501
COR3
R363
COR4
R364
PIU700F7
PIR36401
PIU700E8
PIR36301
PIU700B7
UDM
LDM
PIU700A8
A8
B7
B3
UDM
F3
LDM PIU700F3
PIU700B3
PIU700R3
PIU700E2
A2
PIU700A2
COU1
U70
W971GG6JB-25
VREF_0V9_DDR2
COC1
C462
100n
GND
w
n
PIU70 A3 PIU70E3 PIU70J3 PIU70N1 PIU70 P9 PIU70 A7 PIU70B2 PIU70B8 PIU70D2 PIU70 D8 PIU70E7 PIU70F2 PIU70F8 PIU70H2 PIU70 H8 PIU70J7
-
-
1
L2
L3
BA0
BA1
BA2
PIU700L2
M8
M3
PIU700M3
M7
PIU700M7
N2
PIU700N2
N8
PIU700N8
N3
PIU700N3
N7
PIU700N7
P2
PIU700P2
P8
PIU700P8
P3
PIU700P3
M2
PIU700M2
P7
PIU700P7
R2
PIU700R2
R8
PIU700R8
PIU700M8
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
PIC4620
PIC46201
1.0
65
Simon Scott
Revision
Layout Notes:
1.) Place 100nF bypass capacitors within 7mm of IC pins
2.) Place the 22 ohm termination resistors as close to the IC pins as possible
3.) CK, UDQS and LDQS must be routed as a differential pairs
4.) All traces (except the power supplies) must have a 50 ohm single ended impedance
4
-
GND
ty
L8
CS
K3
WE
L7
PIU700L7 CAS
K7
PIU700K7 RAS
PIU700K3
PIU700L8
r--
r-1f--
~L
II
C463 PIC46 02 COC3
C464 PIC46502 COC4
C465 PIC46 02 COC5
C466 PIC46702 COC6
C467 PIC46802 COC7
C468 PIC46902 C469
C470 PIC47102 C471
C473
COC8
COC10
COC11
PIC46302 COC2
PIC470 2 COC9
PIC4720 C472
PIC47302 COC12
PIC46301 22u PIC46 01 100n PIC46501 100n PIC46 01 100n PIC46701 100n PIC46801 100n PIC46901 100n PIC470 1 100n PIC4710 100n PIC47201 100n PIC47301 100n
ODT
K8
PIU700K8 CK
J8
PIU700J8 CK
K2
PIU700K2 CKE
K9
PIU700K9
er
si
J1
PIU70 A1 PIU70 E1 PIU70J9 PIU70M9 PIU70R1 PIU70 A9 PIU70 C1 PIU70C3 PIU70C7 PIU70C9 PIU70 E9 PIU70G1 PIU70G3 PIU70G7 PIU70G9 PIU70J1 PIU70J2
VCC_1V8_PROC
3
J2
r-r--
D
I
;,
CKE
- --- -
VREF_0V9
CS
WE
CAS
RAS
(l
PIR37802COR1
R378
4k7
I
CS
WE
CAS
RAS
--- ---
CKE
ODT
i 100R_DIFF
ni
v
UDQS_N
UDQS_P
LDQS_N
LDQS_P
U
-- -
VCC_1V8_PROC
ODT
CK_N
CK_P
CKE
ODT
UDM
LDM
DQ[15..0]
i 50_OHM
---
III
C
PODDR20BUS0W\E\0ram0ddr201
PODDR20BUS0VREF00V90ram0ddr201
PODDR20BUS0UDQS0ram0ddr2010P
PODDR20BUS0UDQS0ram0ddr2010N
PODDR20BUS0UDM0ram0ddr201
PODDR20BUS0R\A\S\0ram0ddr201
PODDR20BUS0ODT0ram0ddr201
PODDR20BUS0LDQS0ram0ddr2010P
PODDR20BUS0LDQS0ram0ddr2010N
PODDR20BUS0LDM0ram0ddr201
PODDR20BUS0DQ01500000ram0ddr201
PODDR20BUS0DQ150ram0ddr201
PODDR20BUS0DQ140ram0ddr201
PODDR20BUS0DQ130ram0ddr201
PODDR20BUS0DQ120ram0ddr201
PODDR20BUS0DQ110ram0ddr201
PODDR20BUS0DQ100ram0ddr201
PODDR20BUS0DQ90ram0ddr201
PODDR20BUS0DQ80ram0ddr201
PODDR20BUS0DQ70ram0ddr201
PODDR20BUS0DQ60ram0ddr201
PODDR20BUS0DQ50ram0ddr201
PODDR20BUS0DQ40ram0ddr201
PODDR20BUS0DQ30ram0ddr201
PODDR20BUS0DQ20ram0ddr201
PODDR20BUS0DQ10ram0ddr201
PODDR20BUS0DQ00ram0ddr201
PODDR20BUS0CKE0ram0ddr201
PODDR20BUS0CK0ram0ddr2010P
PODDR20BUS0CK0ram0ddr2010N
PODDR20BUS0C\S\0ram0ddr201
PODDR20BUS0C\A\S\0ram0ddr201
PODDR20BUS0BA0200000ram0ddr201
PODDR20BUS0BA20ram0ddr201
PODDR20BUS0BA10ram0ddr201
PODDR20BUS0BA00ram0ddr201
PODDR20BUS0A01300000ram0ddr201
PODDR20BUS0A130ram0ddr201
PODDR20BUS0A120ram0ddr201
PODDR20BUS0A110ram0ddr201
PODDR20BUS0A100ram0ddr201
PODDR20BUS0A90ram0ddr201
PODDR20BUS0A80ram0ddr201
PODDR20BUS0A70ram0ddr201
PODDR20BUS0A60ram0ddr201
PODDR20BUS0A50ram0ddr201
PODDR20BUS0A40ram0ddr201
PODDR20BUS0A30ram0ddr201
PODDR20BUS0A20ram0ddr201
PODDR20BUS0A10ram0ddr201
PODDR20BUS0A00ram0ddr201
PODDR20BUS0ram0ddr201
DDR2_BUS
UDM
LDM
UDQS_N
UDQS_P
LDQS_N
LDQS_P
DQ[15..0]
BA[2..0]
lJJJ--- - - -
BA[2..0]
A[13..0]
A1
E1
J9
M9
R1
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
A[13..0]
_9_______________" _
,
"
B
I
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DDR2_BUS
:$L _
I
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
9, __________
I
I I
A3
E3
J3
N1
P9
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
,
VREF
,,
,,
,,
VDDL
2
r
VSSDL
HH II.
nn
J7
A
1
I
c-
c-
c-
D
C
B
A
B
1
I
I
CE
CLE
ALE
WE
RE
WP
R/B
GND
f-
I
2
4k7
PIR15302
COR153
R153
VCC_3V3_PROC
COC152
C152
100n
PIR15301
"II
COC153
C153
100n
ty
PIC15301
PIC15302
of
9
16
17
PIU19017
18
PIU19018
8
PIU1908
19
PIU19019
7
PIU1907
III'
II
GND
PIU1902 PIU1902 PIU19038 PIU1902 PIU19023 PIU19024 PIU19035
I/O15
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
3
47
46
45
PIU19045
40
PIU19040
33
PIU19033
28
PIU19028
27
PIU19027
26
PIU19026
44
PIU19044
43
PIU19043
42
PIU19042
41
PIU19041
32
PIU19032
31
PIU19031
30
PIU19030
29
PIU19029
PIU19046
PIU19047
I
3
ow
n
PIU190 PIU1902 PIU1903 PIU1904 PIU1905 PIU1906 PT
IU190 PIU190 PIU1904 PIU1905
e
MT29F2G16AADWP
ap
C
13
VSS
25
PIU19025 VSS
36
PIU19036 VSS
48
PIU19048 VSS
PIU19013
PIU19016
PIU1909
CE
CLE
ALE
WE
RE
WP
R/B
12
VCC
34
VCC
37
PIU19037 VCC
39
PIU19039 VCC
PIU19034
PIU19012
COU19
U19
VCC_3V3_PROC
II I
I..
159
-
4
Sheet 41 of
Drawn By:
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
29/03/2011
C:\Users\..\nand_flash.SchDoc
RHINO
Number
Project
NAND Flash
1.0
65
Simon Scott
Revision
-
Date:
File:
A4
Size
Title
IO15
IO14
IO13
IO12
IO11
IO10
IO9
IO8
IO7
IO6
IO5
IO4
IO3
IO2
IO1
IO0
IO[15..0]
4
A
B
C
D
I
D
IO[15..0]
PIC15201
PIC15202
er
si
100n
COC151
C151
I,
III'
IO[15..0]
PIC15101
"II
II II
-
C
PONAND0BUS0W\P\
PONAND0BUS0W\E\
PONAND0BUS0R\E\
PONAND0BUS0R0B\
PONAND0BUS0IO0150000
PONAND0BUS0IO15
PONAND0BUS0IO14
PONAND0BUS0IO13
PONAND0BUS0IO12
PONAND0BUS0IO11
PONAND0BUS0IO10
PONAND0BUS0IO9
PONAND0BUS0IO8
PONAND0BUS0IO7
PONAND0BUS0IO6
PONAND0BUS0IO5
PONAND0BUS0IO4
PONAND0BUS0IO3
PONAND0BUS0IO2
PONAND0BUS0IO1
PONAND0BUS0IO0
PONAND0BUS0CLE
PONAND0BUS0C\E\
PONAND0BUS0ALE
PONAND0BUS
NAND_BUS
NAND_BUS
PIC15102
ni
v
U
21
22
38
DNU
DNU
DNU
2
20
23
24
35
NC
NC
NC
NC
I
"II
III
I
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
A
1
§
E
I
1
2
3
4
5
6
10
11
14
15
I
r-
f-
II II
f-
D
160
I
1
PIX104
4
CRS/CRS_DV
COL
PIU1040
42
PIU1042
44
43
18p
COC14
C14
.J 1
1
GND
PIC1402
PIC1401
X2
X1
PIU105 PIU108 PIU1035 PIU1047
GND
of
14
TCK
TDI
TDO
TMS
TRST#
LED_ACT
8
PIU1010
PIU109
9
10
11
PIU1011
PIU108
12
PIU1012
3
49R9
PIR802
49R9
PIR1002
RD_N
RD_P
TD_N
TD_P
YLW_LEDYLW_LED+
PIJ1011
12
PIJ1012
Date:
File:
A4
Size
Title
Sheet 42 of
Drawn By:
PID10
PID102
1.0
M1
M2
PIJ10M2
PIJ10M1
D1
COD1
GRN
65
Simon Scott
Revision
SPD_LED
100MBPS
4
COC9
C9
PIC901 100n
PIC902
VCC_3V3_PROC
J00-0065NL
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
29/03/2011
C:\Users\..\100mbps_ethernet.SchDoc
RHINO
COC12
C12
1n
GND
PIC1202
PIC1201
100Mbps Ethernet PHY
Number
Project
7
8
PIJ108
PIJ107
11
NC
CHS_GND
GRN_LED+
GRN_LEDPIJ1010
PIJ109
9
10
3
PIJ103 RD+
RD_CT
5
PIJ105 RD_CT
6
PIJ106 RD-
COJ1
J1
1
TD+
TD_CT
4
PIJ104 TD_CT
2
PIJ102 TDPIJ101
General Notes:
1.) PHY address is set to default value (0x01)
2.) Auto-negotiation is enabled
3.) CLK_OUT is configured to output a clock signal
4.) DP83640 is configured to use RMII mode
5.) DP83640 is configured as the RMII master
JTAG
POJTAG0TMS
POJTAG0TDO
POJTAG0TDI
POJTAG0TCK
POJTAG0T\R\S\T\
POJTAG
SPD_LED
COR10
R10
PIR1001
COR8
R8
RD_CT
GND
COC8
C8
100n
PO15880CLK1
1588_CLK1
PIC801
PIC802
22R
PIR602 PO15880CLK2
1588_CLK2
PO15880GPIO030000
PO15880GPIO3
PO15880GPIO2
PO15880GPIO1
PO15880GPIO0
1588_GPIO[3..0]
22R
PIR502
100R_DIFF
i
VCC_3V3_PROC
GND
COC11
C11
100n
TD_CT
4
-
2
TCK
TDI
TDO
TMS
TRST
JTAG_BUS
100R
PIR1302
w
n
PIR1202
120R
PIR1201
COR12
R12
100R
49R9
PIR902
PIR1102
To
49R9
PIR702
PIR1101
R11
COR11
COR9
R9
PIR901
COR13
R13
26
PIU1026 PIR1301
27
PIU1027
28
PIU1028
13
PIU1013
PIU1014
16
PIU1016
17
PIU1017
e
LED_SPEED
LED_LINK
RD-
ap
C
RD+
TD-
TD+
Layout Notes:
1.) Place 100nF capacitors as close as possible to pins 4 and 5 on RJ45 jack
2.) Place green LED next to RJ45 jack
3.) Place text "100MBPS" on silkscreen, next to LED
4.) Place resistors and caps on the TD+, TD-, RD+, RD- lines as close to the IC as possible
5.) Route TD+, TD- and RD+, RD- as 100 ohm differential pairs, with equal lengths
6.) Place two 100nF bypass caps as close to each supply pin as possible
7.) Place the two 22 ohm resistors as close to pin 24 of the IC as possible
DP83640TVV
33
PIU1033
34
PIU1034
29
RESET
7
PIU107 PWRDOWN/INTN
PIU1029
PIU1031
31
MDC
30
PIU1030 MDIO
40
PIU1043
~-
ABMM2-25.000MHZ-E2-T
GND GND
~::!
PIX102
1=.0....
2
RXD_2
RXD_3
PIU1044
46
45
PIU1045
r--r--r---
GND
PIC1302
PIC1301
3
PIX103
1k5
PIR1402
RXD_0
RXD_1
PIU1046
41
ty
COR7
R7
PIR701
GPIO1_PU
21
1588_GPIO0
22
1588_GPIO1
23
PIU1023
1588_GPIO2
25
PIU1025
1588_GPIO3
36
PIU1036
37
PIU1037
PIU1022
PIU1021
COR5PIR501
R5
COR6
R6
PIR601
1588_GPIO[3..0]
PIR801
GND
PIC1 01
PIC1 02
'-----1
1
PIX101
X1
COX1
R14
COR14
PIR1401
RX_ER
PIU1041
39
GPIO1
GPIO2
GPIO3
GPIO4
GPIO8
GPIO9
CLK_OUT
24
PIU1024
GND
100n
COC10
C10
RD_PU
VCC_3V3_PROC
:
,
____ J
18p
COC13
C13
POPWRDWN0I\N\T\
PWRDWN/INT
VCC_3V3_PROC
RX_DV
PIU1039
38
GND
PIR402
RD_PU
RESET
POR\E\S\E\T\
RX_CLK
PIU1038
er
si
4k87
PIC10 1
PIC10 2
<
MDIO_CLK
MDIO_DATA
RX_DV
TXD_2
TXD_3
PIU106
COR4
R4
PIR401
TD_PU
<
C
5
6
11
PIU105
ni
v
U
PIU109 PIU1032 PIU1048 PIU102
VCC_3V3_PROC
PIC5 10 100n
VCC_3V3_PROC
r---,
CRS_DV
TXD_3
TX_EN
TX_CLK
3
PIU103 TXD_0
4
PIU104 TXD_1
PIU102
2
1
PIU101
COU1
U1
GND
PIC5 0 1 1n
COC439
PIC5 0 2 COC438
PIC5 102 C551
C550
CONN_SHLD
3
15L__ _
RXD0
RXD1
RXER
TXD0
TXD1
TXEN
50MHZ_CLK
TXD_3
JII'
I'
RMII
GPIO1_PU
PIR301
II
PORMII0TXEN
PORMII0TXD1
PORMII0TXD0
PORMII0RXER
PORMII0RXD1
PORMII0RXD0
PORMII0MDIO0DATA
PORMII0MDIO0CLK
PORMII0CRS0DV
PORMII050MHZ0CLK
PORMII
RMII
RX_DV
PIR201
Bootstrap Pullups
.J L
B
PIR10
R3
2k2
.JIIL
A
R2
2k2
II
COC2 PIC302 C3
COC3 PIC402 COC4
COC5 PIC602 COC6
COC7
PIC102 COC1
C1 PIC202 C2
C4 PIC502 C5
C6 PIC702 C7
PIC101 10u PIC201 100n PIC301 100n PIC401 100n PIC501 100n PIC601 100n PIC701 100n
.J L
19
32
48
,
R1
2k2
II
.J L
ANA33VDD
IO_VDD
IO_VDD
PIR302COR3
II
20
PIR20 COR2
,
PIR102 COR1
VCC_3V3_PROC
II
VREF
VCC_3V3_PROC
2
.J L
Vi
CD_VSS
ANAVSS
IO_CORE_VSS
IO_VSS
1
.J L
TD_PU
II
ru
, I1111111
....
,, L~ .~ .!L ..,,
CONN_SHLD
.J L
o
I
15
18
35
47
I
I
D
C
B
A
D
C
B
A
161
INVALID
DCD
DSR
RI
DTR
RS232_CRTL
TX
RTS
RX
CTS
DTR
19
18
17
PIU20017
16
PIU20016
15
PIU20015
20
PIU20020
2
MAX3243IPWR
21
PIU20021
INVALID
FORCEOFF
PIU20022
22
FORCEON
ROUT1
ROUT2
ROUT3
ROUT4
ROUT5
ROUT2B
PIU20023
23
PIU20018
PIU20019
PIU20 6 PIU20 7 PIU203
ty
er
si
14
DIN1
13
DIN2
12
PIU20012 DIN3
PIU20013
PIU20014
COU20
U20
PIU20 5
GND
of
PIC15602
C2-
C2+
24
e
PIU2002
2
1
PIU2001
PIU20024
28
PIU20028
100n
COC158
C158
100n
COC157
C157
To
PIC15802
PIC15801
PIC15702
PIC15701
RS232_RX
4
RS232_CTS
5
RS232_DCD
6
PIU2006
RS232_DSR
7
PIU2007
RS232_RI
8
PIU2008
PIU2005
PIU2004
ap
C1-
C1+
C
RIN1
RIN2
RIN3
RIN4
RIN5
RS232_TX
9
RS232_RTS
10
RS232_DTR
11
PIU20011
PIU20010
PIU2009
GND
DOUT1
DOUT2
DOUT3
100n
PIC15601
COC156
C156
100n
PIC15502
COC155
C155
PIC15501
3
w
n
3
29/03/2011
C:\Users\..\periph_rs232.SchDoc
RHINO
Number
Project
4
Sheet 43 of
Drawn By:
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
RS-232 Header for Peripherals
Date:
File:
A4
Size
Title
GND
RS232_DSR
2
RS232_RTS
4 PIJ604
RS232_CTS
6 PIJ606
RS232_RI
8 PIJ608
10 PIJ6010
PIJ602
SBH11-PBPC-D05-ST-BK
COJ6
J6
RS232_DCD PIJ601
1
RS232_RX PIJ603
3
RS232_TX PIJ605
5
RS232_DTR PIJ607
7
PIJ609 9
4
1.0
65
Simon Scott
Revision
-
1
DTR
VCC_3V3_PROC
Layout Notes:
1.) Place the 100nF decoupling caps as close to the power pins of the IC as possible
PORS2320CTRL0RI
PORS2320CTRL0I\N\V\A\L\I\D\
PORS2320CTRL0DTR
PORS2320CTRL0DSR
PORS2320CTRL0DCD
PORS2320CTRL
RS232_CTRL
PORS2320DATA0TX
PORS2320DATA0RX
PORS2320DATA0RTS
PORS2320DATA0CTS
PORS2320DATA
RS232_DATA
RS232
GND
ni
v
U
100n
PIC15401 PIC15402
COC154
C154
VCC_3V3_PROC
25
3
2
26
VCC
27
V+
GND
V-
1
C
B
A
D
I
,
f-
f-
f-
A
I
2
II'
GND
1
l
I
ASV-48.000MHZ-E-J-T
48MHz Oscillator
OUTPUT
~
GND
VDD
3
PIU803
4
PIU804
COC53
C53
10n
PIC5402
PIC5401
GND
C54
COC54
10n
e
GND
VCC_3V3_PROC
I
PIU802
OE
U8
COU8
PIU801
PIC5302
PIC5301
ap
PIU703
3
COC52
C52
10n
GND
PIC5201
-1H II'
II'
GND
OUTPUT
4
PIU704
C
.,
2
VDD
ASDK-32.768KHZ-LRT
32.768kHz Oscillator
GND
2
PIU702
l
OE
COU7
U7
~
PIU701
1
of
PIC5202
VCC_3V3_PROC
3
PIU603
PIU604
4
VCC_1V8_PROC
COR49
R49
22R
PIR5202
COR52
R52
To
22R
PIR5102
COR51
R51
22R
PIR4902
32K_CLK
SYS_CLK
3
PIR5201
J
162
4
4
Sheet 44 of
Drawn By:
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
29/03/2011
C:\Users\..\am3517_clocks.SchDoc
RHINO
Number
Project
AM3517 Clocks
-
Date:
File:
A4
Size
Title
48M_CLK
w
n
PIR5101
PIR4901
3
-
1
III'
I'
I
Layout Notes:
1.) Place decoupling caps as close to the power pins of each clock IC as possible
ty
er
si
GND
VDD
OUTPUT
AP3S2-26-ER
26MHz Oscillator
GND
OE
COU6
U6
2
PIU602
II'
GND
1
PIU601
~
PIR50 1
ni
v
U
R50
1k8
PIR50 2COR50
PIR4801
R48
1k5
PIR4802COR48
I
["1H II'
1.0
65
Simon Scott
Revision
A
C
B
D
I
D
SYS_CLK
32K_CLK
48M_CLK
2
H II '
C
SYS_CLKREQ
SYS_CLK
32K_CLK
48M_CLK
PROC_CLKS
\..
r
B
POPROC0CLKS0SYS0CLKREQ
POPROC0CLKS0SYS0CLK
POPROC0CLKS048M0CLK
POPROC0CLKS032K0CLK
POPROC0CLKS
PROC_CLKS
1
I
r-
f-
f-
•
l
I
5
ty
11
EN
3
4
5
PIJ1205
PIJ1204
PIJ1203
C407
COC407
4u7
PIC40802
PIC40801
GND
w
n
~JI'
III'
I
3
PIJ120M PIJ120M PIJ120M3 PIJ120M4
C408
COC408
100n
5V_OTG
GND
PIR45802
j
163
OTG_OC
GND
4
4
1.0
65
Simon Scott
f-Sheet 45 of
Drawn By:
Revision
POO\T\G\0\O\C\
OTG_OC
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
PIR29801
R298
4k7
PIR29802 COR298
VCC_3V3_PROC
29/03/2011
C:\Users\..\usb_otg.SchDoc
RHINO
Number
Project
USB On-the-Go
-
Date:
File:
A4
Size
Title
0R
COR330
R459
PIR45902
PIR45901
0R
COR329
R458
PIR45801
Mini USB-AB (67803-8020)
VBUS
DD+
ID
GND
COJ12
J12
I
2
TPS2051BDBVR
PIC407 2
PIC407 1
To
1
PIJ1201
2
PIJ1202
5V_OTG
3
('
1
PIU5602
OC
OTG_OC
3
PIU5603
1
PIU5601
OUT
e
ap
C
6
5
PIU5505
4
PIU5504
2
PIU5502
1
PIU5501
PIU5506
of
11 1'
GND
4
PIU5604
IN
COU56
U56
PIU5605
GND
GND
TPD4E004DRYR
VCC
IO4
IO3
IO2
IO1
I
GND
C406
COC406
100n
OTG_5V_EN
~II'
PIU5503
--{+-
VCC_5V_PROC
3
COU55
U55
er
si
ni
v
OTG_5V_EN
PIR29701
R297
10k
PIR29702 COR297
II If
I
1.) USB data pairs (DM and DP) must be routed as differential pairs, with 90 ohms differential impedance and equal length
2.) The TPD4E004DRYR IC must be placed directly on the DM and DP lines, and not connected via stubs
3.) The 4.7uF and 100nF capacitors should be placed as close as possible to the USB connector
4.) The TPD4E004DRYR should also be placed close to the USB connector, directly after the above mentioned caps
Layout Notes:
b;;
,,
,,
,,
,,
,
lll'
PIC406 2
PIC406 1
;
l
D
U
,
OTG_D_N
OTG_D_P
, ,
~
C
POUSB0OTG0VBUS
POUSB0OTG0ID
POUSB0OTG0DRVVBUS
POUSB0OTG0DP
POUSB0OTG0DM
POUSB0OTG
USB_OTG
VBUS
DM
DP
ID
DRVVBUS
USB_OTG_BUS
2
VCC_3V3_PROC_USB
90R_DIFF
i
ry,,
,••
1
B
A
1
L
GND
.nIl'
A
B
D
C
I
2
L
If-f--
M1
M2
M3
M4
L
T
f-
I
'-
f-
A
164
I
----111
PIU5403
J
I
PIR29401
PIR29402
11
+
COR294
R294
8k06
GND
3
i 90R_DIFF
9
4
5
e
To
PIJ10M PIJ10M2 PIJ10M3 PIJ10M4
COR327
R456
COR328
R457
w
n
PIR45702
PIR45602
0R
0R
PIR45601
GND
PIR45701
6
OC_B
OC_A
PIR29501
Date:
File:
A3
Size
Title
6
OC_A
USB2_OC
POU\S\B\2\0\O\C\
USB1_OC
POU\S\B\1\0\O\C\
PIU5208
8
5
OC_B
PIU5205
PIU5206
7
PIU5207
7
PIC40 1
GND
1.0
8
Sheet 46 of 65
Drawn By:
Simon Scott
Revision
PIC39701100n PIC39802150u PIC39 01 100n PIC40 02 150u
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
29/03/2011
C:\Users\..\usb_host.SchDoc
RHINO
Number
Project
PIC39 02
5V_USB2
8
COC398 C399
COC399 C400
COC400
C398
PIC39801
5V_USB1
COC397
C397
PIC39702
USB Host Transceivers
PIR29601
COR295 R296
COR296
R295
4k7
4k7
PIR29502 PIR29602
VCC_3V3_PROC
GND
r--
2
USB2_D_P
USB2_D_N
GND
ap
C
5
6
B_D7
B_D+
8
PIJ1108 B_GND
PIJ1107
PIJ1106
PIJ1105 B_VBUS
GND
PIU5201
OC2
OC1
OUT2
OUT1
r--
1
1.) The USB3320 devices are configured for HOST-only mode
COC405
C405
100n
of
Bypass caps for supply
pins 20, 21 and 32
USB Type-A (5787745-2)
1
A_VBUS
2
3
A_D+
4
PIJ1104 A_GND
PIJ1103
PIJ1102 A_D-
PIJ1101
COJ11
J11
EN2
EN1
TPS2052BDR
4
CPEN_B
PIU5204
CPEN_A
3
PIU5203
IN
COU52
U52
2
PIU5202
7
t.
General Notes:
1k
PIR29202
PIC40501
GND
VCC_3V3_PROC
-111
1.) All USB data pairs (DM and DP) must be routed as differential pairs, with 90 ohms differential impedance
2.) The 100nf and 100uF capacitors on the VUSB pins of the USB connectors, must be placed as close to the connector as possible
3.) The decoupling caps on IC power supply pins, must be placed as close to pins as possible
4.) The 8k06 resistor must be placed as close as possible to pin 24 of the IC
GND
24
12
PIU54012
PIU54024
n ,T
RBIAS
NC
COC404
C404
100n
PIC405 2
5V_USB2
5V_USB1
COC396
C396
100n
GND
PIC39601
PIC39602
VCC_5V_PROC
6
Ii
GND
RESET
1
CLKOUT
25
PIU54025 XO
PIC40401
5V_USB2
COC403
C403
100n
PIC40402
ty
er
si
5
A
B
C
D
I
D
Layout Notes:
4k7
27
PIU5401
PIU54027
I
COR293
R293
VCC_3V3_PROC
15
SPK_L PIU54015
16
SPK_R PIU54016
22
R292
23 COR292
PIU54023
PIU54022
PIR29201
18
19
PIU54019
PIU54018
PIU54017
CPEN_B
PIC40301
PIC403 2
-j
26
GND
f-
PIU54026 REFCLK
COR291
R291
8k06
i 90R_DIFF
Bypass caps for supply
pins 20, 21 and 32
USB1_D_P
USB1_D_N
--
PIR29301
PIR29302
,
VBUS
ID
ni
v
1k
PIR28902
GND
PIC39501
-
CLK
29
2
NXT
31
PIU54031 DIR
DP
DM
COC395
C395
100n
\
PIU5402
~
~
17
jjj
CPEN
PIR2910
PIR29102
PIC39401
VCC_3V3_PROC
VCC_3V3_PROC
8
REFSEL0 PIU5408
11
REFSEL1 PIU54011
14
REFSEL2 PIU54014
USB3320
PIC39502
:'"
PIU54029 STP
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
PIU54028 PIU5403 PIU5402 PIU54032 PIU54021
=
3
PIU5403
4
PIU5404
5
PIU5405
6
PIU5406
7
PIU5407
9
PIU5409
10
PIU54010
13
PIU54013
100n COU54
U54
COC402
C402
24
PIU53024
PIU53012
12
COC394
C394
100n
~r
GND
100n
PIC40201
f- :~II
COC401
C401
-
PIC40101
RBIAS
NC
PIC39402
5V_USB1
COC393
C393
100n
0
STP
NXT
DIR
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
PIC402
23
PIU53023
COR289
R289
22 PIR28901
PIU53022
15
SPK_L PIU53015
16
SPK_R PIU53016
VBUS
ID
U
17 CPEN_A
PIU53017
PIC39301
PIC39 02
4
f::=
f=
POU\S\B\2\0\R\S\T\
USB2_RST
ULPI
II'
GND
8
11
14
PIU53014
PIU53011
PIU5308
18
DP PIU53018
19
DM PIU53019
CPEN
REFSEL0
REFSEL1
REFSEL2
USB3320
n ,T
PIC401 2
PIU530
-----jll'
GND
'1
VCC_1V8_PROC
4k7
COR290
R290
PIR290 1
PIR290 2
RESET
REFCLK
PIU53028 PIU530 PIU5302 PIU5302 PIU53021
VCC_3V3_PROC
li'
r l
C
POHS0USB20STP
POHS0USB20NXT
POHS0USB20DIR
POHS0USB20DATA7
POHS0USB20DATA6
POHS0USB20DATA5
POHS0USB20DATA4
POHS0USB20DATA3
POHS0USB20DATA2
POHS0USB20DATA1
POHS0USB20DATA0
POHS0USB20CLK
POHS0USB2
HS_USB2
J
1
PIU5301
CLKOUT
25
PIU53025 XO
27
PIU53027
26
PIU53026
PIU53031
STP
NXT
DIR
I
B
I
31
2
PIU5302
29
PIU53029
5
PIU5305
PIU5304
DATA0
DATA1
DATA2
6
PIU5306
DATA3
7
PIU5307 DATA4
9
PIU5309 DATA5
10
PIU53010
DATA6
13
PIU53013 DATA7
3
4
100n COU53
U53
COC392
C392
PIU5303
PIC39201
PIC3920
-j
VCC_3V3_PROC
GND
100n
COC391
C391
f-
CLK
STP
NXT
DIR
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
,
POU\S\B\1\0\R\S\T\
USB1_RST
POHS0USB10STP
POHS0USB10NXT
POHS0USB10DIR
POHS0USB10DATA7
POHS0USB10DATA6
POHS0USB10DATA5
POHS0USB10DATA4
POHS0USB10DATA3
POHS0USB10DATA2
POHS0USB10DATA1
POHS0USB10DATA0
POHS0USB10CLK
POHS0USB1
HS_USB1
ULPI
PIC39101
PIC39102
28
30
VDD18
VDD18
20
VDD33
3
•
33
VCC_1V8_PROC
21
VBAT
~
,
f-
20
:1 __
I''I"
VDD18
VDD18
-
I
VDD33
f- :~II
jj
.:
28
30
32
~
VDDIO
2
=
GND
-
C)l
I
33
l-
'I
32
1
-
~r
21
-
o
\
1==tI~
GND
-
VBAT
-
Y f------1 1
VDDIO
I-
----1 1
M1
M2
M3
M4
-
, · :i
1
-
I
e-
e-
e-
e-
e-
I-
I-
A
B
I
MOSI
MISO
SCLK
CS
)
y
165
I
NC
*
V
PIU3405
GND
3
PIU3403
To
GND
PIC19301
PIC19302
COC193
C193
1F5
M1
PIJ90M1
3
w
n
GND
PIC19 02
PIC19 01
COC191
C191
22u
GND
COJ9
J9
SD Card Conn (145638009511859+)
GND
Date:
File:
A4
Size
Title
PORTC0SQW0I\N\T\
RTC_SQW/INT
PIJ903 PIJ906
100n
COC190
C190
1.0
65
Simon Scott
Revision
Sheet 47 of
Drawn By:
4
4
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
29/03/2011
C:\Users\..\sd_card_and_rtc.SchDoc
RHINO
Number
Project
SD Card and Real-time Clock
-
2
VBACKUP
lll'
1.) Place 100nF and 22uF decoupling caps as close to pin 4 of SD card connector as possible
2.) Place 100nF decoupling capacitor as close to pin 10 of DS1390 IC as possible
3.) Trace lengths between DS1390 and the crystal should be minimised, and should be as straight as possible
X1
X2
GND
PIC190 2
PIC190 1
('
f--
1
3
PIX403
f
ABS25-32.768KHZ-6-T
NC
;=,
=r=
PIX404
L
2
4
1
PIR18601
2k2
COR186
R186
nH I '
PIX402
I
PIU3401
2
PIU3402
9
PIU3409
COU34
U34
DS1390U-33+
SQW/INT
CD
WP
VCC_3V3_PROC
PIJ9010
11
PIJ9011
10
2
CMD
5
PIJ905 CLK
PIJ902
ap PIR18602
e
C
I
X4
COX4
I
6
DIN
7
PIU3407 DOUT
8
PIU3408 SCLK
4
PIU3404 CS
PIU3406
100n
PIU3401
GND
COC192
C192
YII'
PIC19201 PIC19202
7
DAT0
8
DAT1
9
PIJ909 DAT2
1
PIJ901 DAT3
PIJ908
PIJ907
PIJ904
VCC_3V3_PROC
3
'
1
PIX401
of
VCC_3V3_PROC
ty
er
si
PIR18401 PIR18501
2k2
22k
2k2
COR184 COR185
R184
R185
PIR18402 PIR18502
COR183
R183
1
Layout Notes:
SPI
CD
WP
ni
v
U
CMD
CLK
DAT0
DAT1
DAT2
DAT3
22k
PIR1801 PIR18201 PIR18301
22k
COR181 COR182
R181
R182
PIR1802 PIR1820 PIR18302
VCC_3V3_PROC
~
A
B
C
D
T
D
J
PORTC0SPI0SCLK
PORTC0SPI0MOSI
PORTC0SPI0MISO
PORTC0SPI0C\S\
PORTC0SPI
RTC_SPI
POSD0BUS0WP
POSD0BUS0DAT3
POSD0BUS0DAT2
POSD0BUS0DAT1
POSD0BUS0DAT0
POSD0BUS0CMD
POSD0BUS0CLK
POSD0BUS0CD
POSD0BUS
SD_BUS
SD_CARD
22k
22k
PIR17901 PIR1801
COR180
R180
COR179
R179
PIR17902 PIR1802
2
L
C
1
1'
10
I
r-----, 11
VCC
\.
ll
GND
4
VDD
.
.
r
I
5
L
'
VSS1
VSS2
::1
1
3
6
~
T
f-
'-
f-
A
B
C
DVI
I2C
SCL
SDA
PD
DE
VSYNC
HSYNC
MON_SENS
DATA[23..0]
CLK
GND
PIR32501
R325
10k
PIR3250 COR325
VCC_3V3_PROC
MON_SENS
DATA[23..0]
SCL_3V3
SDA_3V3
PIC43 01 10u PIC43 01 100n PIC43501 100n PIC43601 100n
1k
GND
PIR32601
GND
IDCK-
IDCK+
13
PIU61013
PIU61010
10
ISEL/RST
PD
2
DE
5
PIU6105 VSYNC
4
PIU6104 HSYNC
PIU6102
PIU61056
56
57
PIU61057
PIU610 PIU6102 PIU6103 PIU61023 PIU61029 PIU610 8
ty
er
si
ni
v
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
DATA16
DATA17
DATA18
DATA19
DATA20
DATA21
DATA22
DATA23
V_REF
U
63
62
PIU61062
61
PIU61061
60
PIU61060
59
PIU61059
58
PIU61058
55
PIU61055
54
PIU61054
53
PIU61053
52
PIU61052
51
PIU61051
50
PIU61050
47
PIU61047
46
PIU61046
45
PIU61045
44
PIU61044
43
PIU61043
42
PIU61042
41
PIU61041
40
PIU61040
39
PIU61039
38
PIU61038
37
PIU61037
36
PIU61036
PIU61063
3
PIU6103
15
PIU61015 BSEL/SCL
14
PIR32602
PIU61014 DSEL/SDA
COR326
R326
9
PIU6109 EDGE/HTPLG
35
PIU61035 DKEN
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
DATA16
DATA17
DATA18
DATA19
DATA20
DATA21
DATA22
DATA23
VCC_3V3_PROC
e
49
PIU61049
34
PIU61034
11
GND
3
MON_SENS
R321
4k7
PIR3210 COR321
To PIR3210
w
n
GND
PIU61011
6
PIU6106
7
PIU6107
8
PIU6108
COF2
F2
PIF202
Date:
File:
A4
Size
PIU6204
3
4
PIU6203
SCL1
SDA1
VREF1
PIU6201
GND
PIU6205
6
5
PIU6206
29/03/2011
C:\Users\..\video.SchDoc
RHINO
Number
Project
4
Sheet 48 of
Drawn By:
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
PIC43702
PIC43701
PIR3240
1.0
COC437
C437
100n
R324
220k
GND
65
Simon Scott
Revision
PIR32 01 PIR3201
R322
2k2
R323
2k2
VCC_5V_PROC
PIR32 02COR322 PIR320 COR323 PIR32401 COR324
COR332
R461
0R
HDMI (10029449-001RLF)
SCL_5V
SDA_5V
GND
PCA9306DCT
SCL2
SDA2
8
7
PIU6207
PIU6208
PIR460 1 PIR4610
COR331
R460
0R
PIR460 2 PIR46102
PIJ140M1 PIJ140M2 PIJ140M3 PIJ140M
17
GND
18
+5V
19
PIJ14019 HPD
PIJ14018
PIJ14017
EN
VREF2
GND
13
CEC
14
RSVRD
15
PIJ14015 DDC_SCL
16
PIJ14016 DDC_SDA
PIJ14014
PIJ14013
HDMI Video Transmitter
SCL_3V3
SDA_3V3
COU62
U62
PIU6202
2
VCC_3V3_PROC
Title
SCL_5V
SDA_5V
50mA Resettable
PIF201
VCC_5V_PROC
i 50R_SNGL_100R_DIFF
D2+
D2_SHLD
D210
CK+
11
CK_SHLD
12
PIJ14012 CKPIJ14011
PIJ14010
PIJ1403
3
PIJ1401
2
PIJ1402
1
PIJ1406
PIJ1405
5
6
4
PIJ1404
D1+
D1_SHLD
D1-
7
D0+
8
D0_SHLD
9
PIJ1409 D0PIJ1408
PIJ1407
COJ14
J14
1.) I2C interface on TFP410 is disabled
2.) The parallel bus is configured as 24-bits with single-edge clock
2.) Data on parallel bus is latched on FALLING clock edge
3.) Data deskew is disabled
General Notes:
-
2
NC
RESERVED
MSEN/PO1
CTL3/A3/DK3
CTL2/A2/DK2
GND
CK_P
CK_N
22
21
PIU61021
PIU61022
VCC_3V3_PROC
D2_P
D2_N
31
30
PIU61030
PIU61031
ap
TXC+
TXC-
TX2+
TX2-
PIU61027
27
D1_P
D1_N
TX1+
TX1-
28
PIU61028
510R
PIR32001
D0_P
D0_N
CTL1/A1/DK1
C
19 PIR32002
PIU61019
COR320
R320
VCC_3V3_PROC
PIL1001
25
TX0+ PIU61025
24
TX0- PIU61024
TFADJ
COU61
U61
TFP410MPAPREP GND
PIC43101 100n PIC43201 10u
PIL1002
COC431 PIC4320 C432
COC432
PIC43102 C431
VCC_3V3_PROC
4
-
1
of
PIU610 6 PIU61048 PIU6104 PIU6102 PIU61026 PIU61032 PIU6107 PIU61065
Layout Notes:
1.) The data inputs to the TFP410 IC (DATAx) must have equal lengths. Trace separation should be approx 5x height
2.) The data pairs to the HDMI connector (D0+, D0-, etc) must be routed as diff pairs, with the lengths matched (length < 50mm)
3.) These data differential pairs must have single-ended impedance of 50 ohms and differential impedance of 100 ohms
4.) Trace separation for the diff pairs should be 2x to 4x height
5.) Place each 100nF supply decoupling cap directly at each supply pin
6.) The PowerPad on the TFP410 must be connected to ground with vias (as per footprint)
PODVI0VSYNC
PODVI0P\D\
PODVI0MON0SENS
PODVI0HSYNC
PODVI0DE
PODVI0DATA0230000
PODVI0DATA23
PODVI0DATA22
PODVI0DATA21
PODVI0DATA20
PODVI0DATA19
PODVI0DATA18
PODVI0DATA17
PODVI0DATA16
PODVI0DATA15
PODVI0DATA14
PODVI0DATA13
PODVI0DATA12
PODVI0DATA11
PODVI0DATA10
PODVI0DATA9
PODVI0DATA8
PODVI0DATA7
PODVI0DATA6
PODVI0DATA5
PODVI0DATA4
PODVI0DATA3
PODVI0DATA2
PODVI0DATA1
PODVI0DATA0
PODVI0CLK
PODVI
DVI
PIC43 02 COC433
C433 PIC43 02 COC434
C434 PIC43502 COC435
C435 PIC43602 COC436
C436
PIL1202
GND
PIC42801 10u PIC42901 100n PIC430 1 100n
PIC42802 COC428
C428 PIC42902 COC429
C429 PIC430 2 COC430
C430
PIL1102
COL10
L10
3
B
A
C
D
I
D
PODDC0I2C0SDA
PODDC0I2C0SCL
PODDC0I2C
DDC_I2C
COL12
L12
PIL1201
VCC_3V3_PROC
COL11
L11
PIL1101
VCC_3V3_PROC
2
DGND
DGND
DGND
16
48
64
I
20
26
32
1
1
12
33
DVDD
DVDD
DVDD
23
29
TVDD
TVDD
TGND
TGND
TGND
PVDD
18
PGND
I
PWRPAD
I
166
17
\.'
65
"
GND
L
1
-
M1
M2
M3
M4
L
I
_ r--- ~~
II
1,1'
PIC14 02
PIC14 01
C141
COC141
II'
::ll'
~~II'
I
COC140
C140
1u
PIC14001 PIC14002
GND
GND
3
PIR14801
PIR14701
PIR14702
100k
R148
COR148
100k
R147
COR147
w
nPIR14802
COR146
R146
100k
To
PIR14601
PIR14602
PIR14501
R145
100k
PIR14502 COR145
GND
GND
PIR14 01
R144
100k
GND
Audio
GND
4
Sheet 49 of
Drawn By:
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
LINE_OUT
COJ5
1PIJ501J5
3PIJ503
2PIJ502
SJ-3523-SMT
PHONES
COJ4
1PIJ401J4
3PIJ403
2PIJ402
SJ-3523-SMT
LINE_IN
COJ3
1PIJ301J3
3PIJ303
2PIJ302
SJ-3523-SMT
29/03/2011
C:\Users\..\audio.SchDoc
RHINO
Number
Project
Date:
File:
A4
Size
Title
GND
'Ilf
2
1u
PIC13901 PIC13902
COC139
C139
e
100u
PIC13601 PIC13602
COC136
C136
COC134
C134
1n
PIC13402
PIC13401
1k
PIR14302
COR143
R143
PIR14301
PIR14 02COR144
1k
PIR14202
COR142
R142
PIR14201
100k
COR141
R141
PIR14 01
PIR14 02
4
1.0
65
Simon Scott
Revision
-
1
1.) Place label for each connector (LINE_IN, etc) on the
sikscreen, next to each connector
2.) Place the supply decoupling caps as close to the supply
pins as possible
1.) The control interface is configured for SPI mode
2.) The sampling rate is set to multiple of 8kHz, and
therefore cannot do 44.1kHz
GND
Layout Notes:
167
100n
C142
COC142
100u
2u2
PIC13501 PIC13502
ap
C
COC135
C135
=:=
10u
PIC1420
PIC14201
of
GND
:
I,
lll'
General Notes:
Decoupling caps for DVDD
and BVDD supply pins
I--
GND
12
PIU10012
13
PIU10013
9
PIU1009
10
PIU10010
PIU10017
COC133
C133
PIC13301 PIC13302
PIC13201 PIC13202
Ii
C143 PIC14 02 COC144
C144
PIC14302 COC143
PIC14301 1u PIC14 01 10n
VMID
I--
PIU1028 PIU10 PIU10 5
LOUT
ROUT
LHPOUT
RHPOUT
MICBIAS
2u2
III'
VCC_3V3_PROC
18p
GND
PIC13701
ty
17
18
PIU10018
20
PIU10020
19
PIU10019
VMID
COC132
C132
COC131
C131
1n
PIC13 02
PIC13 01
GND
f=
GND
4
PIX304
"II 1,1'
II
GND
GND GND
COC137
C137
CLKOUT
MICIN
LLINEIN
RLINEIN
16
PIU10016
er
si
VMID
TLV320AIC23BIPWR
Decoupling caps for
AVDD supply pin
GND
'Ilf
B
A
C
D
I
D
II
II
ABM3B-12.288MHZ-B2-T
PIC13702
2
PIU1002
14
ni
v
8
PIU10 UPIU1027 PIU108 PIU10 4
COU10
U10
GND
PIC12901 1u PIC130 1 10n
COC129 PIC130 2 C130
COC130
PIC12902 C129
3
'Ilf
C
2
I~
PIX302
1-'-
PIC13801
3
PIX303
XTO
PIU10026
26
XTI/MCLK
LRCIN
DIN
LRCOUT
DOUT
BCLK
PIU10025
25
5
PIU1005
4
PIU1004
7
PIU1007
6
PIU1006
3
PIU1003
1
18p
PIC13802
1
J
##
+ +
PIX301
\...
r
COX3
X3
POAUDIO0DATA0LRCOUT
POAUDIO0DATA0LRCIN
POAUDIO0DATA0DAC0DIN
POAUDIO0DATA0BCLK
POAUDIO0DATA0ADC0DOUT
POAUDIO0DATA
AUDIO_DATA
>f
LRCIN
DAC_DIN
LRCOUT
ADC_DOUT
BCLK
21
CS
23
SDIN
24
PIU10024 SCLK
22
PIU10022
MODE
PIU10023
PIU10021
GND
PIC12701 22u PIC12801 100n
COC127 PIC12802 COC128
PIC12702 C127
C128
2
rill'
COC138
C138
\...
AIC23_I2S
I
CS
MOSI
SCLK
MISO
VCC_3V3_PROC
Decoupling caps
for HPVDD supply
pin
PIL302
PIL202
I
B
POAUDIO0CTRL0SCLK
POAUDIO0CTRL0MOSI
POAUDIO0CTRL0MISO
POAUDIO0CTRL0C\S\
POAUDIO0CTRL
AUDIO_CTRL
SPI
COL3
L3
PIL301
COL2
L2
PIL201
27
f--
BVDD
VCC_3V3_PROC
1
DVDD
A
I
AVDD
~
HPVDD
1
~~II'
.---
DGND
~~II'
=~ = ~
.,1
'11 1
28
""
HPGND
"II
I
III'
11
.,1
'11 1
AGND
.,1
'11 1
f=
15
f=
I
f-
f-
f-
PIJ130M2 PIJ130M
10p
COC417
C417
1
GND
2
PIX502
1
PIC42301 100n PIC42401 100n PIC42501 100n PIC42601 100n PIC42701 100n
GND
GND
4
PIX504
3
PIX503
PIC41801
PIC41802
10p
COC418
C418
10k
COR307
R307
GND
PIR3071
PIR307 2
Decoupling Caps for FT4232HQ:
Place one cap at each VCCIO and
VREGIN pin
2
COR305
R305
GND
4u7
COC414
C414
PIR3081
PIR308 2
COR308
R308
12k
PIR30502
4
DM
DP
RESET
REF
PIU57014
PIU5706
7
8
3
5
GND
4
R319
COR319
PIR31901
2k2
R314
COR314
10k
EEPROM_DAT
EEPROM_CLK
TX
RX
RTS
CTS
RS232
11
PIU58011
TRST
5
PIR3150
330R
R315
COR315
D40
COD40
ORNG
PIR31601
R316
COR316
330R
PIR31602
PID40 2
PID40 1
PIU5802
PIU5801
PIR3170
PIR31702
PID4102
PID410
COC409
C409
GND
5
3
PIU5803
PIU5805
7
PIU5807
9
PIU5809
6
PIR3180
PIR31802
PID420
PID4201
PIR310 2
COR311
R311
10k
PIR310
5
SDA0
R302
10k
PIR302 1
R303
10k
PIU5908
PIU5904
GND
COC416
C416
PIR30 2
PIC41602
Date:
File:
A3
Size
Title
GND
1
NC PIU5901
7
SCL1 PIU5907
6
SDA1 PIU5906
TDI
JTAG_BUS
SCL
SDA
I2C
TCK
TDI
TDO
TMS
TRST
7
I2C
POI2C0SDA
POI2C0SCL
POI2C
POJTAG0TMS
POJTAG0TDO
POJTAG0TDI
POJTAG0TCK
POJTAG0T\R\S\T\
POJTAG
JTAG
8
1.1
8
Sheet 50 of 65
Drawn By:
Simon Scott
Revision
FPGA_SUPPLY_EN
POFPGA0SUPPLY0EN0FPGA0VCCO0AUX0EN
POFPGA0SUPPLY0EN0FPGA0VCCINT0EN
POFPGA0SUPPLY0EN
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
29/03/2011
C:\Users\..\usb_to_jtag_rs232.SchDoc
RHINO
Number
Project
USB to JTAG/I2C/RS-232
FPGA_VCCINT_EN
FPGA_VCCO_AUX_EN
FTDI_SUPPLY_EN_BUS
COU59
U59
PCA9515APWR
100n
PIC41601
FPGA_VCCINT_EN
FPGA_VCCO_AUX_EN
PIU5905 EN
2
3
PIU5903
PIR301
R301
10k
VCC_3V3_PROC
PIR30 1
R300
10k
7
PIR30 2COR300 PIR3012 COR301 PIR302 COR302 PIR30 1 COR303
VCC_3V3_PROC
PIU5902 SCL0
COR310
R310
4k7
GND
D42
COD42
ORNG
R318
COR318
330R
PIR3102
PIR309 1 PIR310
I2C_EN
SCL
SDA
COR309
R309
4k7
PIR309 2
COU58
U58
SN74LVC244ADB
2Y1
2Y2
2Y3
2Y4
18
1Y1 PIU58018
16 TDI_BUF
1Y2 PIU58016
14
1Y3 PIU58014
12
1Y4 PIU58012
100n
PIC40901 PIC40902
6
D41
COD41
ORNG
R317
COR317
330R
GND
VCC_3V3_PROC
LED Silkscreen Labels
(left to right):
DGB0_RX
DBG0_TX
DGB1_RX
DBG1_TX
D39
COD39
ORNG
2OE
w
n
GND
To
PIR31502
1OE
2A1
13
PIU58013
2A2
15
PIU58015 2A3
17
PIU58017 2A4
19
PIU58019
JTAG_EN
POUART10TX
POUART10RX
POUART10RTS
POUART10CTS
POUART1
UART1
PID3902
PID3901
1
PIU5801
PIR29 01
COR299
R299
2k2
PIR29 02
VCC_3V3_PROC
TCK
2
PIU5802
1A1
TDI
4
PIU5804
1A2
TDO_UNBUFPIU5806
6
1A3
TMS
8
PIU5808 1A4
JTAG_EN
POUART00TX
POUART00RX
POUART00RTS
POUART00CTS
POUART0
UART0
5
e
ap
TX
RX
RTS
CTS
RS232
I2C_EN
C
PIR30602
EEPROM_CS
U1_TX
U1_RX
of
U0_TX
U0_RX
1k
PIR30601
COR306
R306
SCL
SDA
TCK
TDO_UNBUF
TDI_BUF
TMS
TRST
JTAG_EN
FPGA_VCCINT_EN
FPGA_VCCO_AUX_EN
PIR31902
PIR3120 PIR310 PIR3140
R313
10k
PIR3120 PIR31 02 COR313PIR31402
R312
COR312
10k
PIU6004
4
60
36
PIU57036
PIU57060
VCC_3V3_PROC
3
DI PIU6003
1
DO PIU6001
CLK
93LC56BT-I/OT
6
PIU6006 VCC
2
PIU6002 VSS
CS
U60
COU60
GND
PIU6005
100n
PIC42202
C422
COC422
PIC42201
GND
PWREN
SUSPEND
48
DDBUS0 PIU57048
52
DDBUS1 PIU57052
53
DDBUS2 PIU57053
54
DDBUS3 PIU57054
55
DDBUS4 PIU57055
57
DDBUS5 PIU57057
58
DDBUS6 PIU57058
59
DDBUS7 PIU57059
38
CDBUS0 PIU57038
39
CDBUS1 PIU57039
40
CDBUS2 PIU57040
41
CDBUS3 PIU57041
43
PIU57043
CDBUS4
44
CDBUS5 PIU57044
45
CDBUS6 PIU57045
46
CDBUS7 PIU57046
ty
26
BDBUS0 PIU57026
27
BDBUS1 PIU57027
28
BDBUS2 PIU57028
29
BDBUS3 PIU57029
30
BDBUS4 PIU57030
32
BDBUS5 PIU57032
33
BDBUS6 PIU57033
34
PIU57034
BDBUS7
er
si
PIU5701 PIU5701 PIU570 PIU5701 PIU57015 PIU57025 PIU57035 PIU5704 PIU5701 PIU57065
VCC_3V3_PROC
TEST
PIU57013
13
OSCO
PIU5703
3
PIU5702 OSCI
2
63
PIU57063 EECS
62
PIU57062 EECLK
61
PIU57061 EEDATA
6
14
PIU5708
PIU5707
ni
v
FT4232HQ
16
ADBUS0 PIU57016
17
ADBUS1 PIU57017
18
ADBUS2 PIU57018
19
ADBUS3 PIU57019
21
ADBUS4 PIU57021
22
ADBUS5 PIU57022
23
ADBUS6 PIU57023
24
ADBUS7 PIU57024
COU57
U57
VCC_3V3_PROC
PIU5704 PIU5709 PIU57012 PIU57037 PIU57064 PIU5702 PIU57031 PIU57042 PIU570 6
VCC_1V8_USBREG
U
VREGIN
49
PIU57049
VREGOUT
50
PIU57050
GND
GND
EEPROM_CS
EEPROM_CLK
EEPROM_DAT
1k
PIR30401 PIR30501
Decoupling Caps for FT4232HQ:
Place one cap at each VCORE pin
GND GND
C424 PIC42502 COC425
C425 PIC42602 COC426
C426 PIC42702 COC427
C427
COC423 PIC42 02 COC424
PIC42302 C423
VCC_3V3_PROC
GND
PIC41901 100n PIC420 1 100n PIC42101 100n
C420 PIC42102 COC421
C421
COC419 PIC420 2 COC420
PIC41902 C419
PIC41701
PIC41702
4k7
ABM3B-12.000MHZ-10-1-U-T
GND
COR304
R304
PIR30402
D_N
D_P
90R_DIFF
i
PIC41401
PIC41402
VCC_1V8_USBREG
VCC_3V3_PROC
1.) The FT4232 USB IC is the JTAG master in the chain
2.) The current through the traffic LEDs is 3.9mA
General Notes:
PIC410 1 4u7 PIC41 01 4u7 PIC41201 100n PIC41301 100n
COX5
X5
PIX501
COC415
C415
100n
GND
PIC41501
PIC41502
3
1.) D_P and D_N must be routed as differential pair, with 90 ohms differential impedance, and equal lengths
2.) The 4 traffic LEDs must be placed in a line, with their silkscreen labels next to them
Layout Notes:
COC413
PIC410 2 COC410
C410 PIC41 02 COC411
C411 PIC41202 COC412
C412 PIC41302 C413
GND
PIL902
PIL901
COL9
L9
PIL802
PIL801
COL8
L8
I2C_EN
USB Type-B (292304-1)
1
VBUS PIJ1301
2
D- PIJ1302
3
D+ PIJ1303
4
GND PIJ1304
COJ13
J13
VCC_3V3_PROC
VCC_1V8_USBREG
168
II'
D
C
B
A
POI2C0EN
I2C_EN
2
4
9
VPHY
VPLL
1
M2
M1
12
37
64
VCORE
VCORE
VCORE
20
VCC
GND
10
20
31
42
56
VCCIO
VCCIO
VCCIO
VCCIO
AGND
GND
GND
GND
GND
GND
GND
GND
GND
GND
10
1
5
11
15
25
35
47
51
65
11
·
U0_TX
L
U0_RX
T
I
U1_RX
II f
U1_TX
-
VCC
:~
8
,
t""
GND
I
4
J
-
D
C
B
A
D
C
B
A
POJTAG0MASTER0TMS
POJTAG0MASTER0TDO
POJTAG0MASTER0TDI
POJTAG0MASTER0TCK
POJTAG0MASTER0T\R\S\T\
POJTAG0MASTER
JTAG_MASTER
1
TDO
TCK
TMS
TRST
TDI
JTAG_BUS
TCK
TMS
TRST
2
FMC_0_TDI
2
PIU1802
1
PIU1801
PIU180
PIU1804
GND
2
G
Y
Y
SN74LVC2G157DCT
U18
COU18
A/B
B
A
100n
PIC15001 PIC15002
GND
GND
PIU1704
G
7
PIU1807
3
PIU1803
5
PIU1805
PIU1707
7
PIU1703
PIU1705
5
ty
er
si
3
Y
Y
VCC_3V3_PROC
COC150
C150
FMC_1_PRSNTPIU1806
6
FMC_1_TDI
FMC_1_TDO
A/B
B
A
SN74LVC2G157DCT
COU17
U17
FMC_0_PRSNTPIU1706
6
PIU1702
1
PIU1701
FMC_0_TDO
100n
PIU1708
VCC_3V3_PROC
COC149
C149
PIC14901 PIC14902
GND
2
ni
v
U
8
VCC
GND
8
VCC
GND
4 1"
4
1
I
4
I
of
169
TMS
TRST
TCK
TMS
TRST
TCK
~
I" II,
TCK
TDI
TDO
TMS
TRST
JTAG_BUS
TCK
TDI
TDO
TMS
TRST
CTRL_1
GA0
GA1
PRSNT_M2C
PG_C2M
I2C
FMC_CTRL
GA0
GA1
PRSNT_M2C
PG_C2M
I2C
FMC_0_PRSNT
FMC_1_PRSNT
JTAG Chain
~
4
Sheet 51 of
Drawn By:
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
29/03/2011
C:\Users\..\jtag_chain.SchDoc
RHINO
Number
Project
Date:
File:
A4
Size
Title
1.0
65
Simon Scott
Revision
General Notes:
1.) The JTAG harnesses represent the actual JTAG pins on each IC (i.e. TDI on
a harness represents the TDI input pin)
Layout Notes:
1.) Place 100nF decoupling caps as close to pin 8 of the ICs as possible.
FMC_1_CTRL
POFMC010CTRL0PG0C2M
POFMC010CTRL0P\R\S\N\T\0\M\2\C\
POFMC010CTRL0I2C0SDA
POFMC010CTRL0I2C0SCL
POFMC010CTRL0I2C
POFMC010CTRL0GA1
POFMC010CTRL0GA0
POFMC010CTRL
POFMC000CTRL0PG0C2M
POFMC000CTRL0P\R\S\N\T\0\M\2\C\
POFMC000CTRL0I2C0SDA
POFMC000CTRL0I2C0SCL
POFMC000CTRL0I2C
POFMC000CTRL0GA1
POFMC000CTRL0GA0
POFMC000CTRL
FMC_0_CTRL
CTRL_0
FMC_CTRL
4
-
3
PO1G0JTAG0TMS
PO1G0JTAG0TDO
PO1G0JTAG0TDI
PO1G0JTAG0TCK
PO1G0JTAG0T\R\S\T\
PO1G0JTAG
1G_JTAG
PO100M0JTAG0TMS
PO100M0JTAG0TDO
PO100M0JTAG0TDI
PO100M0JTAG0TCK
PO100M0JTAG0T\R\S\T\
PO100M0JTAG
100M_JTAG
w
n
POFMC010JTAG0TMS
POFMC010JTAG0TDO
POFMC010JTAG0TDI
POFMC010JTAG0TCK
POFMC010JTAG0T\R\S\T\
POFMC010JTAG
FMC_1_JTAG
POFMC000JTAG0TMS
POFMC000JTAG0TDO
POFMC000JTAG0TDI
POFMC000JTAG0TCK
POFMC000JTAG0T\R\S\T\
POFMC000JTAG
FMC_0_JTAG
POPROC0JTAG0TMS
POPROC0JTAG0TDO
POPROC0JTAG0TDI
POPROC0JTAG0TCK
POPROC0JTAG0T\R\S\T\
POPROC0JTAG
PROC_JTAG
POFPGA0JTAG0TMS
POFPGA0JTAG0TDO
POFPGA0JTAG0TDI
POFPGA0JTAG0TCK
POFPGA0JTAG0T\R\S\T\
POFPGA0JTAG
FPGA_JTAG
To
JTAG_BUS
e
TCK
TDI
TDO
TMS
TRST
JTAG_BUS
TCK
TDI
TDO
TMS
TRST
JTAG_BUS
TCK
TDI
TDO
TMS
TRST
JTAG_BUS
TCK
TDI
TDO
TMS
TRST
JTAG_BUS
ap
C
TCK
FMC_1_TDI
FMC_1_TDO
TMS
TRST
TCK
FMC_0_TDI
FMC_0_TDO
TMS
TRST
TMS
TRST
TCK
TMS
TRST
TCK
3
C
B
A
D
1
,
f-
f-
-
f-
I I I~-
I
I
1
t
100n
2
PIC14701 PIC14702
of
GND
A
VCCA
SN74LVC1T45DBVR
5
PIU1205
DIR
B
4
PIU1204
COU12
U12
VCCB
6
GND
Data Flow Direction
PIU1206
VCC_2V5_FPGA
ty
GND
1OE
2OE
SN74AVC4T245PW
v
15
14
2
PIU1202
PIU1203
3
1
PIU1201
e
PIC14802
100n
PIC14801
COC148
C148
ap
GND
VCC_3V3_PROC
C
9
PIU1109
PIU11014
PIU11015
PIC14602
100n
t
11
1'
GND
To
GND
I
3
w
n
PIR14901
R149
10k
PIR14902 COR149
VCC_3V3_PROC
GND
3
170
-
4
Sheet 52 of
Drawn By:
Licensed under the TAPR Open
Hardware License
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29/03/2011
C:\Users\..\config_lvl_xlator.SchDoc
RHINO
Number
Project
-
Date:
File:
A4
POINIT0B0DIR
INIT_B_DIR
POCONFIG03V30PROGRAM0B
POCONFIG03V30INIT0B
POCONFIG03V30DONE
POCONFIG03V30DIN
POCONFIG03V30CCLK
POCONFIG03V3
CONFIG_3V3
1.0
65
Simon Scott
Revision
Configuration Interface Level Translator
r
Size
Title
INIT_B
DONE
CCLK
DIN
PROGRAM_B
FPGA_CONFIG_BUS
4
B
A
C
D
I
D
INIT_B
I'
GND
III'
6
COC147
C147
8
PIU1108
1DIR
2DIR
er
si
2
3
PIU1103
PIU1102
13
12
PIU11012
11
PIU11011
10
PIU11010
1B1
1B2
2B1
2B2
PIU11013
16
PIU11016
VCCB
PIC14601
COC146
C146
VCC_3V3_PROC
I'
GND
VCCA
4
1A1
5
PIU1105 1A2
6
PIU1106 2A1
7
PIU1107
2A2
PIU1104
1
PIU1101
11
DONE
ni
v
U
100n
COU11
U11
Data Flow Direction
III'
C
POCONFIG02V50PROGRAM0B
POCONFIG02V50INIT0B
POCONFIG02V50DONE
POCONFIG02V50DIN
POCONFIG02V50CCLK
POCONFIG02V5
CONFIG_2V5
COC145
C145
PIC14501 PIC14502
t
CCLK
DIN
PROGRAM_B
FPGA_CONFIG_BUS
GND
VCC_2V5_FPGA
2
V
II
B
A
1
t
I
r-
f-
f-
\.
A
B
I
I
I
SDA
SCL
I
I2C
2
1
PIP801
PIP802
GND
GND
PIR46801
R468
10k
PIR46802COR342
2
90131-0767
PIJ803
PIJ801
3
GND
PIR17 01
FP_SPI_PROC
POFP0SPI0PROC0SCLK
POFP0SPI0PROC0MOSI
POFP0SPI0PROC0MISO
POFP0SPI0PROC0C\S\
POFP0SPI0PROC
FAIL_INT
R177
4k7
PIR17 02COR177
RESPWRON
RST_PB
R467
2k2
GND
PIR46701
3 VCCO_AUX
PIU3303
7 VCCINT
PIU3307
VCC_12V
2Y
1Y
PIR4601
2k2
ty
4
COR172
R172
w
n
12V_IN
pwr_monitor
5V_PROC_MON
VCC_12V_FMC
VCC_3V3_FMC
VCC_2V5_FMC
5
To
VCCMGT_PG
e
ap
VCCMGT_PG
C
VTTDDR3_PG
3V3_FPGA_MON
2V5_FPGA_MON
6
I2C_MON_BUS
temp_monitor
I2C_MON_BUS
5V_PROC_IN
12V_FMC_IN
3V3_FMC_IN
2V5_FMC_IN
3V3_FPGA_IN
2V5_FPGA_IN
1V5_FPGA_IN
VTTDDR3_PG
PIR17202
1V5_FPGA_MON
0R005
PIR17201
GND
i SUPPLY_12V
1V2_FPGA_IN
1,2
- Power push-button
3,4
- Reset push-button
5,6
- Power LED
7,9
- Power
8,10,12,14 - Processor SPI
11,13
- FPGA I2C
Connector Pinout:
I2C_MON_BUS
INT
RESPWRON
RESET_PB
PROC_SUPPLY_EN
proc_power_supply
FMC1_SUPPLY_EN
FMC1_AUX_EN
FMC0_SUPPLY_EN
FMC0_AUX_EN
fmc_power_switches
FPGA_VCCMGT_EN
PIJ704
4
3
PIJ703
VCC_12V
1V2_FPGA_MON
of
FPGA_VCCO_AUX_EN
spartan6_ldo_supply
COR340
R466
FPGA_VCCINT_EN
spartan6_power_supply
er
si
PIR46702COR341PIR4602
ni
v
SN74LVC2G32DCTR
1
2
PIJ702
PIJ701
6
Date:
File:
A3
Size
Title
VCC_5V_PROC
VCC_1V2_MGT
VTT_0V75_DDR3
VCC_3V3_FPGA
VCC_2V5_FPGA
VCC_1V5_FPGA
VCC_3V3_PROC
VCC_1V8_PROC
VCC_1V2_PROC
VCC_3V3_PROC_USB
VCC_1V8_PROC_DPLL
OVER_TEMP
FAN_FAIL
VCC_1V2_FPGA
PWR_OFF_INT
PWR_FAIL_INT
RESPWRON
FAN_FAIL
VTTDDR3_PG
VCCMGT_PG
power_leds
OVER_TEMP
PWR_WARNS
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
PITP140
PITP130
PITP120
PITP1 0
PITP10
PITP90
PITP80
PITP70
PITP60
PITP50
PITP40
PITP30
Revision
TP14
COTP14
COTP13
TP13
COTP12
TP12
COTP11
TP11
COTP10
TP10
COTP9
TP9
COTP8
TP8
COTP7
TP7
COTP6
TP6
COTP5
TP5
COTP4
TP4
COTP3
TP3
1.1
POO\V\E\R\0\T\E\M\P\
OVER_TEMP
POWARN0OUT0VTTDDR30PG
POWARN0OUT0VCCMGT0PG
POWARN0OUT0R\E\S\P\W\R\O\N\
POWARN0OUT0P\W\R\0\O\F\F\0\I\N\T\
POWARN0OUT0P\W\R\0\F\A\I\L\0\I\N\T\
POWARN0OUT0F\A\N\0\F\A\I\L\
POWARN0OUT
WARN_OUT
8
7
8
29/03/2011
Sheet 53 of 65
C:\Users\..\pwr_supply_management.SchDoc
Drawn By:
Simon Scott
RHINO
Number
Project
Power Supply Management
FAN_FAIL
OVER_TEMP
7
OFF_INT
FAIL_INT
RESPWRON
FAN_FAIL
VTTDDR3_PG
VCCMGT_PG
I
FP_I2C_FPGA
POFP0I2C0FPGA0SDA
POFP0I2C0FPGA0SCL
POFP0I2C0FPGA
f-
PWR_PB
VCC_5V_PROC
1
2 PIJ802
RST_PB
3
4 PIJ804
SPI
PIR17802
PIJ805 5
6 PIJ806 PIR17801
R178
220R
8 PIJ808 COR178
CS
PIJ807 7
10 PIJ8010
MOSI
PIJ809 9
PIJ8011 11 12 PIJ8012
SCLK
PIJ8013 13 14 PIJ8014
MISO
J8
COJ8
10k
PIU3 04
90120-0122
P8
COP8
PIR45502
COR333
R455
PIR45501
PROC_SUPPLY_EN
ALWAYS_ON
GND
4k7
COR176
R176
PIR17501 PIR17601
4k7
COR175
R175
PIR17502 PIR17602
5
6
PIU3306
PIU3 08
U
GND
GND
+12V
+12V
39-28-1043
COJ7
J7
5
111111111111
1
GND
GND
4k7
COR174
R174
PIR17301 PIR17401
COR173
R173
4k7
PIR17302 PIR17402
2A
2B
PIU3305
PIU3302
1A
1B
COU33
U33
PIU3301
1
2
100n
VCC_3V3_PROC
4
-
VCC_3V3_PROC
I2C_PWR_MAN
POI2C0PWR0MAN0SDA
POI2C0PWR0MAN0SCL
POI2C0PWR0MAN
FMC1_SUPPLY_EN
FMC1_AUX_EN
FMC0_SUPPLY_EN
FMC0_AUX_EN
FPGA_VCCINT_EN
FPGA_VCCO_AUX_EN
FPGA_VCCMGT_EN
SUPPLY_EN_BUS
FPGA_VCCO_AUX_EN
FPGA_VCCINT_EN
GND
COC189
C189
PIC18901 PIC18902
COC187
C187
22n
GND
PIC18701
PIC18702
VCC_3V3_PROC
Note: to turn off, power but must be held in for 200ms
Processor then has 4.4 seconds to shutdown
FTDI_SUPPLY_EN_BUS
GND
LTC2951CTS8-1
8
KILL PIU3208
7
OFFT PIU3207
PROC_SUPPLY_EN
6
EN PIU3206
OFF_INT
5
INT PIU3205
10k
PIR46501
COR339
R465
PIR46502
3
A
B
C
D
I
D
171
POSUPPLY0EN0FPGA0VCCO0AUX0EN
POSUPPLY0EN0FPGA0VCCMGT0EN
POSUPPLY0EN0FPGA0VCCINT0EN
POSUPPLY0EN0FMC10SUPPLY0EN
POSUPPLY0EN0FMC10AUX0EN
POSUPPLY0EN0FMC00SUPPLY0EN
POSUPPLY0EN0FMC00AUX0EN
POSUPPLY0EN
SUPPLY_EN
680nF
GND
PIC18 01
COC188
C188
PWR_PB
PIC18 02
VIN
2
PIU3202
PB
3
PIU3203
KILLT
4
PIU3204 GND
1
PIU3201
COU32
U32
2
II
Note:
Place text "ALWAYS_ON" on
silkscreen, next to jumper header
POFTDI0SUPPLY0EN0FPGA0VCCO0AUX0EN
POFTDI0SUPPLY0EN0FPGA0VCCINT0EN
POFTDI0SUPPLY0EN
FTDI_SUPPLY_EN
GND
100n
VCC_12V
I
I
C
COC186
C186
PIC18601 PIC18602
POPWR0KILL
PWR_KILL
1
8
I
VCC
I
GND
-
,L
4
-
I
f-
f-
A
VCC_12V
PIC36 02
PIC36 01
COC366
C366
POFPGA0VCCINT0EN
FPGA_VCCINT_EN
22u
172
I
PIC37402
PIC37401
COC374
C374
III'
I'
"~~I'
I
FPGA_VCCO_AUX_EN
POFPGA0VCCO0AUX0EN
1
2
e
Elec
330u
COC373
C373
GND
PIC37301
PIC37302
PIC37502
PIC37501
COC375
C375
22u
GND
INH/UVLO
10
1
Track
SmartSync
3
PTH08T240W
PIU4901
PIU49010
w
n
11
PIU49011
VI
COU49
U49
PIU4902
To
2
PTH08T230W
PIU4703
5
6
7
PIU4707
PIU4706
PIU4705
6k98
Date:
File:
A4
Size
Title
GND
PIU4903 PIU490
5
SUPPLY_3V3 i
1k21
PIR28101
PIR28102
COR279 15k
R279
9
PIU4909
PIR27901
PIR27902
6
PIU4906
7
PIU4907
8
PIU4908
R281
COR281
PIU4905
GND
GND
PIC370 1
PIC370 2
COC370
C370
Tant
100u
COC378
C378
Tant
330u
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
PIC37801
PIC37802
-
4
COC379
C379
Tant
330u
1.0
PIR27702
65
Simon Scott
Revision
GND
PIC37901
PIC37902
0R005
PIR27701
VCC_3V3_FPGA
R277
COR277
PO3V30FPGA0MON
3V3_FPGA_MON
COC371
C371
Tant
330u
GND
PIC37101
PIC37102
0R005
PIR27102
COR271VCC_1V5_FPGA
R271
PO1V50FPGA0MON
1V5_FPGA_MON
PIR27101
-
29/03/2011
Sheet 54 of
C:\Users\..\spartan6_power_supply.SchDoc Drawn By:
RHINO
Number
Project
Spartan-6 Power Supplies
TurboTrans
+Sense
-Sense
VO Adjust
VO
PIR27502
PIR27302
VCC_3V3_FPGA
COR275
R275
PIR27501
3V3 10A FPGA + FMC Supply
GND
TurboTrans
+Sense
-Sense
VO Adjust
8
PIU4708
PIR27301
COR273 100k
R273
SUPPLY_1V5 i
r
FPGA_VCCO_AUX_EN
1.) 22uF input caps must be placed within 1.3cm of pin 2
2.) Resistor between "-Sense" and "VO Adjust" must be placed directly at the pins
Layout Notes for Supplies:
III'
I'
GND
Tant
330u
COC377
C377
0R005
PIR27602
VCC_12V
"~~I'
VCC_2V5_FPGA
III'
I'
GND
PIC37 01
PIC37 02
+: ~II'
Tant
330u
R276
COR276
ap
FPGA_VCCO_AUX_EN
C
GND
INH/UVLO
9
Track
1
PIU4701 SmartSync
PIU4709
f------l III'
I'
GND
2k37
PIR28002
COC376
C376
of
GND
COC367
C367
22u
10
PIU47010
4
PIU4704
III'
I'
GND
f------l III'
I'
PIU4803 PIU480
r
PIR28001
PIC37601
PIC37602
ty
PO2V50FPGA0MON
2V5_FPGA_MON
PIR27601
GND
PIC36702
PIC36701
VO
4
+: ~II'
GND
Track
SmartSync
PTH08T240W
PIU4801
10
1
I
PIU48010
TurboTrans
+Sense
-Sense
VO Adjust
H
22u
INH/UVLO
COR278 15k
R278
9
PIU4809
PIR27801
PIR27802
6
PIU4806
7
PIU4807
8
PIU4808
R280
COR280
Tant
330u
COC369
C369
COC365
C365
Elec
330u
VI
COU47
U47
I
Elec
330u
SUPPLY_2V5 i
6
11
PIU48011
VCC_2V5_FPGA
GND
PIC36901
PIC36902
er
si
ni
v
Tant
100u
f-
COC372
C372
5
PIU4805
COC368
C368
PIC36501
PIC36502
2
PIU4702
VCC_1V5_FPGA
6
PIC37201
PIC37202
VO
2V5 10A FPGA + FMC Supply
12k1
PIR27402
PIC36801
PIC36802
0R005
VCC_12V
FPGA_VCCO_AUX_EN
H
A
B
C
D
I
D
III'
I'
,
VI
COU48
U48
Ill'
I'
,
C
2
U
COR274
R274
III'
I'
f-
PIU4802
f
PIR27401
PIR27202
PIR27002
VCC_1V2_FPGA
COR270
R270
PIR27001
+: ~II'
GND
5
6
7
PIU4607
PIU4606
PIU4605
8
PIU4608
PIR27201
COR272
R272 100k
SUPPLY_1V2 i
f-
VCC_12V
GND
PIU4603
4
PIU4604
PO1V20FPGA0MON
1V2_FPGA_MON
1V5 6A FPGA + DRAM Supply
f
FPGA_VCCO_AUX_EN
PTH08T230W
TurboTrans
+Sense
-Sense
VO Adjust
VO
VCC_1V2_FPGA
"~~I'
GND
INH/UVLO
9
Track
1
PIU4601 SmartSync
PIU4609
10
PIU46010
VI
COU46
U46
1V2 6A FPGA VCCINT Supply
3
GND
2
III'
I'
B
I
III'
I'
GND
Elec
330u
COC364
C364
"~~I'
PIC36401
PIC36402
2
PIU4602
I
3
H I
III'
I'
GND
GND
'6
I
3
1
f-
3
4
H I
GND
GND
'6
+: ~II'
I
3
4
I
r-
r-
II
I
PIC3 702
PIC3 701
EN
SS
PIU4505
PIU4507
1
J
2
PIR26701
R267
4k99
----, II'
-----jH II'
:H II'
I
PIC3 502
PIC3 501
C335
COC335
10u
GND
To
i SUPPLY_1V2
3
w
n
173
GND
PIQ402
Q4
2N7002W
D38
COD38
GRN
FPGA_VTT
4
Sheet 55 of
Drawn By:
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
65
Simon Scott
Revision
1.0
FPGA_MGT
VCCMGT_PG
POVCCMGT0PG
GND
PIQ502
Q5
COQ5
2N7002W
PIQ503
PID3801
PID3802
PIR26402
R264
120R
PIR26401 COR264
VCC_3V3_FPGA
PIQ501
29/03/2011
C:\Users\..\spartan6_ldo_supply.SchDoc
RHINO
Number
Project
COD37
D37
GRN
POVTTDDR30PG
VTTDDR3_PG
PIQ401
PIR2602
PID3702
PID3701
PIQ403COQ4
R260
120R
PIR2601 COR260
VCC_3V3_FPGA
Spartan-6 LDO Power Supplies
-
Date:
File:
A4
Size
Title
VCCMGT_PG
PIR26501
R265
100k
PIR26502 COR265
VCC_3V3_PROC
VTTDDR3_PG
PIR2601
R262
100k
PIR2602 COR262
VCC_3V3_PROC
4
-
1
VCCMGT_PG
PIR26 01
PIR26702COR267
2k49
GND
3
PIU4503
8
PIU4508
VCC_1V2_MGT
COC333
C333
100n
GND
PIC3 302
PIC3 301
e
ap
C
R266
COR266
PIR26 02
li'
GND
PIU4506 PIU4501
PG
FB
10
9
PIU4509
PIU45010
of
III'
1.) For TPS51200, place caps at VLDOIN and VO close to the pins, via short+wide traces
2.) Connect the PowerPad of both ICs directly to the ground plane with vias, to help heat dissipation
3.) Place the name of each LED (e.g. FPGA_VTT) on the silkscreen, next to the LED
7
5
OUT
OUT
TPS74801DRC
ty
GND
:1
GND
IN
IN
PIU4501
2
PIU4502
I
1n
BIAS
4
PIU4504
COU45
U45
11
C337
COC337
er
si
Q
Layout Notes for Supplies:
1u
PIC33402
GND
GND
VTTDDR3_PG
4u7
PIC32602 PIC32601
VREF_0V75_DDR3
3
:~
GND
C336
COC336
1u
GND
Y II'
PIC3 601
PIC3 602
COC334
C334
PIC33401
PWRPAD
1V2 1.5A FPGA MGT Regulator
VCC_3V3_FPGA
~
FPGA_VCCMGT_EN
POFPGA0VCCMGT0EN
VCC_1V5_FPGA
III'
I'
B
A
C
D
I
D
::
::
::
::
::
III'
I'
GND
TPS51200
VIN
PGOOD
GND
EN
REFOUT
nPIU401 i
v
U
REFIN
VLDOIN
VO
PGND
VOSNS
10
PIU44010
9
PIU4409
8
PIU4408
7
PIU4407
6
PIU4406
VCC_3V3_FPGA
COC326
C326
III'
I'
C
Q
II
PIC32701 1n PIC32801 10u PIC32901 10u PIC3 0 1 10u PIC3 10 10u PIC3 201 10u
1
PIU4401
2
PIU4402
3
PIU4403
4
PIU4404
5
PIU4405
COU44
U44
0V75 3A DDR Term. Regulator
I
PIR26301
i SUPPLY_0V75
U
COC330PIC3 102 C331
COC331PIC3 20 C332
COC332
PIC32702 COC327
C327PIC32802 COC328
C328PIC32902 COC329
C329PIC3 0 2 C330
R263
10k
0V75 Ref
PIR2610
PIR26302COR263
R261
10k
PIR26102COR261
VTT_0V75_DDR3
T
B
A
VCC_1V5_FPGA
2
til'
11
1
:H II'
~rr-1II'
1-
6
11
~r
GND
PWRPAD
~rr-1II'
1-
I
r-
e-
e-
A2
PIU130A2
B2
PIU130B2
FMC1_SUPPLY_EN
POFMC10SUPPLY0EN
1
ON
VIN
VIN
VOUT
VOUT
PIU150C
ON
FMC1_SUPPLY_EN
C2
PIU160C2
e
VCC_2V5_FMC
EN
VIN
VOUT
w
n
GND
fet_sw_2
SI6463BDQ_switch
To
EN
VIN
VOUT
VCC_12V_FMC
GND
3
VCC_12V_FMC
POVCC012V0FMC
VCC_3V3_FMC
POVCC03V30FMC
POVCC02V50FMC
VCC_2V5_FMC
FMC1_SUPPLY_EN
VCC_3V3_FMC
VCC_12V_FMC
GND
PIU160C1
A1
PIU160A1
B1
PIU160B1
TPS22924C
VOUT
VOUT
i SUPPLY_2V5
ap
C
PIR15202
fet_sw_0
SI6463BDQ_switch
0R005
FMC0_SUPPLY_EN
FMC1_SUPPLY_EN
2
VIN
VIN
A2
PIU160A2
B2
PIU160B2
VCC_2V5_FMC
COU16
U16
COR152
R152
PIR15201
VCC_3V3_FMC
VCC_3V3_FMC
GND
A1
PIU150A1
B1
PIU150B1
TPS22924C
VOUT
VOUT
i SUPPLY_3V3
of
VCC_2V5_FMC1
ty
TPS22924C
A1
PIU140A1
B1
PIU140B1
i SUPPLY_2V5
VCC_2V5_FMC0
ni
vePIU140C1
rs
i
FMC0_SUPPLY_EN
C2
PIU140C2
PIU140A2
B2
PIU140B2
GND
VCC_AUX_FMC1
A2
U
VCC_2V5_FMC
VCC_3V3_FMC
COU14
U14
PIR15102
GND
--1II'
FMC0_SUPPLY_EN
ON
C2
PIU150C2
FMC1_AUX_EN
POFMC10AUX0EN
PIU130C
A1
PIU130A1
B1
PIU130B1
TPS22924C
VOUT
VOUT
i SUPPLY_3V3
VCC_AUX_FMC0
0R005
PIR15101
VCC_12V
Date:
File:
A4
Size
Title
EN
VIN
GND
VOUT
4
Sheet 56 of
Drawn By:
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
29/03/2011
C:\Users\..\fmc_power_switches.SchDoc
RHINO
Number
Project
VOUT
VCC_12V_FMC1
65
Simon Scott
Revision
1.0
SUPPLY_12V i
GND
fet_sw_3
SI6463BDQ_switch
EN
VIN
VCC_12V_FMC0
SUPPLY_12V i
fet_sw_1
SI6463BDQ_switch
FMC Power Supply Switches
FMC1_SUPPLY_EN
VCC_12V_FMC
i SUPPLY_3V3
VCC_3V3_FMC1
FMC0_SUPPLY_EN
VCC_12V_FMC
i SUPPLY_3V3
VCC_3V3_FMC0
OND
FMC0_SUPPLY_EN
POFMC00SUPPLY0EN
VIN
VIN
A2
PIU150A2
B2
PIU150B2
VCC_3V3_FMC
COU15
U15
ON
VIN
VIN
COU13
U13
VCC_2V5_FMC
C2
PIU130C2
POFMC00AUX0EN
FMC0_AUX_EN
VCC_3V3_FMC
PIR15002
COR151
R151
VCC_3V3_FPGA
4
>-
D
C
B
A
0R005
PIR15001
COR150
R150
VCC_2V5_FPGA
3
GND
2
GND
1
GND
C1
GND
C1
GND
t---
C1
174
C1
GND
-;II'
GND
t---;II'
GND
t---
o
D
C
B
A
A
I
B
I
1
2
10k
PIR43701
PIQ80S
e
ap
C
POGND0fet0sw00
GND
PIQ902
:I- ~
PIR43702
PIQ901
Si6463BDQ
COQ2
Q9
MMBT2222AW
PIQ80G
PIR43501
PIQ80D
To
R436
10k
I
3
w
n
PIR43601
PIR43602 COR3
3
PIC53802
PIC53801
II
COR2
R437
10k
COQ1
Q8
of PIQ903
COR1
R435
ty
PIR43502
er
si
f~1
"
175
-
4
Sheet 57 of
Drawn By:
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
29/03/2011
C:\Users\..\SI6463BDQ_switch.SchDoc
RHINO
Number
Project
Si6463BDQ FET Load Switch
-
Date:
File:
A4
Size
Title
100n
COC1
C538
POVOUT0fet0sw00
VOUT
4
1.0
65
Simon Scott
Revision
A
B
C
D
I
D
POEN0fet0sw00
EN
POVIN0fet0sw00
VIN
ni
v
U
2
I
C
1
I
r-
f-
f-
A
I
B
I
1
2
10k
PIR44001
PIQ100S
e
ap
C
POGND0fet0sw01
GND
PIQ1 02
:I- ~
PIR44002
PIQ1101
Si6463BDQ
COQ2
Q11
MMBT2222AW
PIQ10 G
PIR43801
PIQ100D
To
R439
10k
I
3
w
n
PIR43901
PIR43902 COR3
3
PIC53902
PIC53901
II
COR2
R440
10k
COQ1
Q10
of PIQ103
COR1
R438
ty
PIR43802
er
si
f~1
"
176
-
4
Sheet 58 of
Drawn By:
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
29/03/2011
C:\Users\..\SI6463BDQ_switch.SchDoc
RHINO
Number
Project
Si6463BDQ FET Load Switch
-
Date:
File:
A4
Size
Title
100n
COC1
C539
POVOUT0fet0sw01
VOUT
4
1.0
65
Simon Scott
Revision
A
B
C
D
I
D
POEN0fet0sw01
EN
POVIN0fet0sw01
VIN
ni
v
U
2
I
C
1
I
r-
f-
f-
A
I
B
I
1
2
10k
PIR44301
PIQ120S
e
ap
C
POGND0fet0sw02
GND
PIQ1302
:I- ~
PIR44302
PIQ1301
Si6463BDQ
COQ2
Q13
MMBT2222AW
PIQ120G
PIR44101
PIQ120D
To
R442
10k
I
3
w
n
PIR4201
PIR420 COR3
3
PIC540 2
PIC540 1
II
COR2
R443
10k
COQ1
Q12
of PIQ130
COR1
R441
ty
PIR44102
er
si
f~1
"
177
-
4
Sheet 59 of
Drawn By:
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
29/03/2011
C:\Users\..\SI6463BDQ_switch.SchDoc
RHINO
Number
Project
Si6463BDQ FET Load Switch
-
Date:
File:
A4
Size
Title
100n
COC1
C540
POVOUT0fet0sw02
VOUT
4
1.0
65
Simon Scott
Revision
A
B
C
D
I
D
POEN0fet0sw02
EN
POVIN0fet0sw02
VIN
ni
v
U
2
I
C
1
I
r-
f-
f-
A
I
B
I
1
2
10k
PIR44601
PIQ140S
e
ap
C
POGND0fet0sw03
GND
PIQ1502
:I- ~
PIR44602
PIQ1501
Si6463BDQ
COQ2
Q15
MMBT2222AW
PIQ140G
PIR44401
PIQ140D
To
R445
10k
I
3
w
n
PIR4501
PIR4502 COR3
3
PIC54102
PIC5410
II
COR2
R446
10k
COQ1
Q14
of PIQ1503
COR1
R444
ty
PIR44402
er
si
f~1
"
178
-
4
Sheet 60 of
Drawn By:
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
29/03/2011
C:\Users\..\SI6463BDQ_switch.SchDoc
RHINO
Number
Project
Si6463BDQ FET Load Switch
-
Date:
File:
A4
Size
Title
100n
COC1
C541
POVOUT0fet0sw03
VOUT
4
1.0
65
Simon Scott
Revision
A
B
C
D
I
D
POEN0fet0sw03
EN
POVIN0fet0sw03
VIN
ni
v
U
2
I
C
1
I
r-
f-
f-
COC162
C162
22u
GND
100n
COC172
C172
100n
COC173
C173
R166
22k
GND
PIC17302
PIC17301
PIR1601
VCC_5V_PROC
I2C_MON_BUS
POI2C0MON0BUS0SDA
POI2C0MON0BUS0SCL
POI2C0MON0BUS
PIR17 01
1
I2C
HOT_RESET
R171
4k7
PIR17 02COR171
,
RESET_PB
POR\E\S\E\T\0\P\B\
179
5ms power-up delay
GND
PIC17202
PIC17201
PIR16701
R167
47k
PIR16702COR167
PIR1602 COR166
VCC_1V8_PROC VCC_1V2_PROC
y
SDA
SCL
INH/UVLO
PTH08T230W
9
Track
1
PIU2101 SmartSync
PIU2109
10
PIU21010
Place 22uF cap within 1.3cm of pin 2
PIC1620
PIC16201
VI
PIC16702
PIC16701
22u
100n
C175
COC175
5ms power-up delay
GND
PIC17502
PIC17501
PIR170 1
R170
100k
PIR170 2COR170
VCC_3V3_PROC
VO
GND
PIR16402
169R
ni
v
U
PIU2106
100k
PIR16302
GND
GND
22u
COC168
C168
GND
COC176
C176
1n
2
12
13
11
26
29
SDAT
SCLK
HOT_RESET
TRESPWRON
LDO_EN
Tant
330u
L1
AGND1
AGND2
PGND1
PGND2
PGND3
PWRPAD
LOW_BAT
PWRFAIL
RESPWRON
INT
40
17
8
PIU2208
34
PIU22034
3
PIU2203
41
PIU22040
PIU22021
21
PIU22031
31
PROC_3V3_EN
LDO2_OUT
LDO1_OUT
2.2uH
PIL601
COL6
L6
2.2uH
PIL501
COL5
L5
2.2uH
PIL401
COL4
L4
PIU22041
PIU22017
II'
GND
PIR4601
R464
47k
PIR16901
R169
100k
4
Sheet 61 of
Drawn By:
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
29/03/2011
C:\Users\..\proc_power_supply.SchDoc
RHINO
Number
Project
COC174
C174
22u
POR\E\S\P\W\R\O\N\
RESPWRON
INT
POI\N\T\
i
SUPPLY_1V8
VCC_1V8_PROC
i
SUPPLY_3V3
VCC_3V3_PROC
i
SUPPLY_1V2
VCC_1V2_PROC
i
SUPPLY_3V3
1.1
65
Simon Scott
Revision
Note:
Although the I2C pins are powered by the 5V
input, they can be pulled up to 3.3V, and
therefore interface directly with 3.3V devices
PIR16801
R168
100k
COC171
C171
22u
GND
PIC17402
PIC17401
DCDC3_OUT
VCC_3V3_PROC
COC165
C165
22u
GND
PIC17 01
PIC17 02
DCDC2_OUT
i
SUPPLY_1V8
VCC_3V3_PROC_USB
COC163
C163
10u
VCC_1V8_PROC_DPLL
COC164
C164
10u
GND
PIC16501
PIC16502
DCDC1_OUT
AM3517 Power Supply
-
Date:
File:
A4
Size
Title
Used for sequencing only
(hysteris provides clean EN signal)
PIR46301
R463
47k
PIC16402
PIC16401
GND
LDO2_OUT
PIR46302 COR337PIR4602 COR338 PIR16802 COR168 PIR16902 COR169
VCC_1V8_PROC
DCDC3_OUT
DCDC2_OUT
DCDC1_OUT
PIC16301
PIC16302
GND
LDO1_OUT
4
-
3
PIL602
PIL502
PIL402
PROC_PERIPH_EN
w
n
27
PIU22027
28
PIU22028
16
PIU22016
18
PIU22018
20
PIU22020
4
PIU2204
2
PIU2202
35
PIU22035
33
PIU22033
7
PIU2207
9
PIU2209
To
VRTC
VLDO2
VLDO1
L3
VDCDC3
L2
VDCDC2
e
VCC_5V_PROC
PIR16202
Layout Note:
Connect PowerPad of TPS65023 to ground
plane with vias (as per footprint)
0R005
VDCDC1
COC161
C161
ap
C
PIC16 01
PIC16 02
COR162
R162
PIR16201
PO5V0PROC0MON
5V_PROC_MON
3
I II
TPS65023
PIU22029
30
PIU22030
PIU22026
PIU22011
22
PIU22022
25
DCDC1_EN
24
PIU22024 DCDC2_EN
23
PIU22023 DCDC3_EN
PIU22025
PIU22013
PIU22012
DEFLD01
DEFLD02
10
DEFDCDC1
32
DEFDCDC2
1
PIU2201 DEFDCDC3
PIU22032
PIU22010
HOT_RESET
PROC_PERIPH_EN
PIC17601 PIC17602
39
LOWBAT_SNS
38
PIU22038 PWRFAIL_SNS
PIU22039
15
PIU22015
VBACKUP
VSYSIN
VCC_5V_PROC
PROC_3V3_EN
of
VINLDO
PIU22014
14
PIU22019
19
PIU2206
VCC_5V_PROC
1u
COC170
C170
GND
PIC170 2
PIC170 1
GND
22u
COC169
C169
GND
PIC16902
PIC16901
ty
VCC
COC160
C160
Tant
100u
GND
PIC160 1
PIC160 2
6
VINDCDC1
36
PIU22036 VINDCDC2
5
PIU2205 VINDCDC3
VCC_5V_PROC
37
PIU22037
U22
COU22
VCC_5V_PROC
er
si
Note: place input caps and resistor
as close to IC pins as possible
PIR16502
PIC16802
PIC16801
COR163
R163
6
7
PIU2107
PIR16401
COR164
R164
8
PIU2108
PIR16301
5
PIU2105
4
PIU2104
Place 169R resistor directly at IC pins
TurboTrans
+Sense
-Sense
VO Adjust
COC167
C167
GND
1u
COC166
C166
10R
GND
PIC16 02
PIC16 01
COR165
R165
GND
PIR16501
VCC_5V_PROC
PIU2103
II'
I I
D
Elec
330u
COC159
C159
GND
PIC15901
PIC15902
2
PIU2102
i---+-------i:H
II'
C
B
A
VCC_12V
COU21
U21
Power Inputs
5V 6A Supply for Processor PMIC
2
Power Outputs
POPROC0SUPPLY0EN
PROC_SUPPLY_EN
GND
3
'------i:H
II'
Voltage
Selection
'-------I:H
Enables
I
H II'
,
Control
_
YH II'
Warnings
I
Y
~
L
Ground
1
I
D
C
B
A
B
VIN+
VIN-
I
PIU230
GND
PIU2604
PIU2603
SDA
SCL
I2C
GND
,,
VIN-
PIU2307
SDA
SCL
PIU30 3
PIU2605
7
8
PIU2608
PIU2607
PIU3005
PIU3006
INA219AIDCN
,,
VCC_3V3_PROC
I2C_SDA
I2C_SCL
GND
I2C_SDA
7
A0 PIU3007
8
A1 PIU3008
SDA
SCL
6
5
I2C_SDA
I2C_SCL
INA219AIDCN
A0
A1
I2C Address: 1000001
ty
2
PIU2704
VIN+
VIN-
7
8
PIU2708
PIU2707
e
ap
To
GND
w
n
2
PIU3102
2
PIU3101
1
GND
VIN-
VIN+
PIU3104
6
5
I2C_SDA
I2C_SCL
PIU3105
PIU3106
A0
A1
7
8
PIU3108
PIU3107
INA219AIDCN
~II'
~II'
GND
PIU3103
SDA
SCL
VCC_3V3_PROC
COC185
C185
PIC18502 PIC18501
100n
U31
COU31
I2C Address: 1000111
PO12V0FMC0IN
12V_FMC_IN
VCC_12V
3
VCC_3V3_PROC
1.) Place each INA219 device as close to its current-sensing resistor (5mR 1W) as possible
2.) Place the 100nF decoupling capacitor as close to the IC pin as possible
GND
I2C_SDA
I2C_SCL
PIU2705
PIU2706
INA219AIDCN
A0
A1
SDA
SCL
6
5
GND
INA219AIDCN
of PIU2703
C
PIU2702
1
PIU2701
I2C Address: 1000100
PO3V30FPGA0IN
3V3_FPGA_IN
Layout Notes:
PIU2407
VCC_3V3_PROC
I2C_SDA
I2C_SCL
GND
PIU2403
6
5
PIU2405
PIU2406
7
A0
8
A1 PIU2408
SDA
SCL
VCC_3V3_FPGA
VCC_3V3_PROC
COC181
C181
PIC18102 PIC18101
100n
COU27
U27
GND
er
si
ni
v
U
VIN-
PIU2402
2
VIN+
1
PIU2401
VCC_3V3_PROC
VIN-
PIU2502
2
VIN+
1
PIU2501
I2C Address: 1000010
VIN+
VIN-
VINPIU2902
2
VIN+
PIU2901
1
GND
PIU2903
GND
6
7
8
65
Simon Scott
Revision
1.0
I2C_SDA
PIU2908
Sheet 62 of
Drawn By:
4
I2C_SDA
PIU2907
,
VCC_3V3_PROC
PIU2906
I2C_SCL
5
PIU2905
INA219AIDCN
A0
A1
SDA
SCL
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
29/03/2011
C:\Users\..\pwr_monitor.SchDoc
RHINO
Number
Project
Power Monitor
PIU2904
PIU2808
PIU2807
7
8
VCC_3V3_PROC
I2C_SDA
I2C_SCL
PIU2805
PIU2806
6
5
GND
INA219AIDCN
GND
PIU2803
A0
A1
SDA
SCL
VCC_3V3_PROC
COC183
C183
PIC18302 PIC18301
100n
COU29
U29
I2C Address: 1001001
PO5V0PROC0IN
5V_PROC_IN
VCC_5V_PROC
I2C Address: 1000101
2
PIU2802
1
PIU2801
PIU2804
I2C_SDA
I2C_SCL
PIU2507
INA219AIDCN
GND
PIU2503
6
5
PIU2505
PIU2506
I2C_SDA
7
A0
8
A1 PIU2508
SDA
SCL
VCC_2V5_FPGA
VCC_3V3_PROC
COC182
C182
PIC18202 PIC18201
100n
COU28
U28
GND
PO2V50FMC0IN
2V5_FMC_IN
Date:
File:
A4
Size
Title
PIU2504
4
VCC_1V5_FPGA
VCC_3V3_PROC
COC179
C179
PIC17902 PIC17901
100n
COU25
U25
GND
PO1V50FPGA0IN
1V5_FPGA_IN
---
GND
I2C_SDA
I2C_SCL
GND
PIU2606
6
5
INA219AIDCN
PO1V20FPGA0IN
1V2_FPGA_IN
PIU240
VCC_1V2_FPGA
VCC_3V3_PROC
COC178
C178
PIC17802 PIC17801
100n
COU24
U24
GND
3
---
1
I2C Address: 1000110
PIU3002
2
PIU3001
VIN+
~II'
1
I2C_SDA
I2C_SCL
2
~II'
PO3V30FMC0IN
3V3_FMC_IN
T
PIU30 4
6
5
PIU2305
PIU2306
7
A0
8
A1 PIU2308
SDA
SCL
COU23
U23
VCC_3V3_FPGA
VCC_3V3_PROC
COC184
C184
PIC18402 PIC18401
100n
U30
COU30
GND
I2C_MON_BUS
POI2C0MON0BUS0SDA
POI2C0MON0BUS0SCL
POI2C0MON0BUS
I2C Address: 1000011
2
PIU2602
1
PIU2601
~
,,
l
D
PIU2304
VCC_2V5_FPGA
VCC_3V3_PROC
COC180
C180
PIC18002 PIC18001
100n
COU26
U26
GND
PO2V50FPGA0IN
2V5_FPGA_IN
180
C
VIN-
PIU2302
2
VIN+
PIU2301
1
100n
I2C Address: 1000000
PO12V0IN
12V_IN
GND
PIC17701
VCC_3V3_PROC
COC177
C177
PIC17702
4
Vs
GND
~II'
3
A
VCC_12V
4
Vs
GND
3
1
I'
4
III'
T
Vs
~II'
GND
III'
~II'
3
4
Vs
4
Vs
GND
3
GND
3
4
Vs
GND
3
I
I'
~II'
4
~II'
T
n
,
Vs
~II'
4
I'
Vs
III'
GND
~II'
T
3
~II'
I'
4
~II'
III'
T
Vs
T
!
~II'
T
~II'
GND
~II'
~II'
3
T
!
I'
GND
~II'
!
III'
A
B
D
C
I
3
T
I
r-
~
~
~
B
I
00
PIU5016
II'
GND
II'
GND
2
GND
GND
PIU510
GND
II'
~
I
3
w
n
TC654
To
SDA
SCLK
CF
I2C Address: 0011011
e
4
I2C_SDA
PIU5104
3
PIU5103
COC388
C388
1u8
2
PIU5102
I2C_SCL
PIC38 01
PIC38 02
ap
COC386
C386
10n
C
PIC38602
PIC38601
VIN
PIU510
820R
PIR28502
COC385
C385
PIC38501 PIC38502
100n
COC389
C389
PIC38901 PIC38902
100n
COC380
C380
100n
GND
PIC380 2
PIC380 1
COC383
C383
100n
PIQ701
R287
4R7
GND
OVER_TEMP
PIR28701
PIC38 02
PIC38 01
GND
PIR28702 COR287
PIQ602
PIQ703COQ7
COP4
P4
1
2
PIP402
PIP401
4
FAN1
22-11-2022
Q7
MMBT2222AW
PIR28 01
OVER_TEMP
POO\V\E\R\0\T\E\M\P\
FAN_FAIL
POF\A\N\0\F\A\I\L\
R288
4R7
PIR28 02COR288
PIQ702
Sheet 63 of
Drawn By:
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
29/03/2011
C:\Users\..\temp_monitor.SchDoc
RHINO
Number
Project
FAN2
22-11-2022
1.0
65
Simon Scott
Revision
Temperature Monitor and Fan Controller
6
PIU5106
7
PIU5107
8
PIU5108
-
Date:
File:
A4
Size
Title
FAULT
SENSE2
SENSE1
COR285
R285
PIR28501
PIU5109
9
GND
VOUT
I
-
1
oPIR28601 f
PIR28602COR286
1
PIU5101
COU51
U51
1u
PIC38101 PIC38102
820R
Q6
MMBT2222AW
PIP301
COP3
P3
1
2
PIP302
VCC_12V
11
1.) Place each 2-pin connector within 10cm of MAX1668
2.) Also place the FPGA and PROC 2-pin connectors within 10cm of the respective devices
3.) Place the AMB 2-pin connector near a board edge
4.) Route each DXN and DXP pair parallel to each other, with guard GND traces on either side
5.) Keep DXN and DXP pairs away from high-speed busses
I2C Address: 0011000
MAX1668
11
ADD0
10
ADD1 PIU50010
PIU50011
R286
22k
duty cycle of 95%)
VCC_3V3_PROC
COC381
C381
PIR28202 PIQ601
1'
A
B
C
D
I
D
181
U
Routing notes for MAX1668:
(~
7
DXP4
8
PIU5008 DXN4
PIR28401
Ill'I'
PIU5007
OVER_TEMP
I2C_SDA
13
SMBDATA PIU50013
I2C_SCL
14
SMBCLK PIU50014
12
PIU50012
GND
100n
ty
er
si
COC382
C382
H::lI'
2n2
5
PIU5005 DXP3
6
PIU5006 DXN3
ALERT
15
PIU50015
PIC3820
PIC38201
R284
6k8 VIN = 2.52V (gives default
PIR28402COR284
VCC_3V3_PROC
COR282
R282
PIR28201
4
I
C
00
=~
22-11-2022
,---
1 DX3_P
2 DX3_N
PIP702
~
COC390
C390
2n2
3
DXP2
4
PIU5004 DXN2
PIU5003
(~
PIP701
r-
COC387
C387
STBY
I I
COP7
P7
Hf- Hf- Hf-
PIC38702
PIC38701
PIC390 2
PIC390 1
DXP1
DXN1
PIU509
PIR28302
1
=~
22-11-2022
1 DX2_P
2 DX2_N
PIP602
PIP601
1
2
PIU5002
PIU5001
COU50
U50
220R
ni
v
U
PIQ603COQ6
~~
AMB
00
2n2
COC384
C384
'----r'
PIC38401
(~
COP6
P6
PIC38402
f--
PIR28301
COR283
R283
VCC_3V3_PROC
I2C_SDA
I2C_SCL
r-1H II'
22-11-2022
1 DX1_P
PIP501
2 DX1_N
PIP502
SDA
SCL
3
HH II'
FPGA
PROC
COP5
P5
POI2C0MON0BUS0SDA
POI2C0MON0BUS0SCL
POI2C0MON0BUS
I2C_MON_BUS
I2C
r--
9
2
T
VCC
A
1
l'
GND
~~
16
r
10
HH II'
VDD
I
00
GND
00
5
I
r-
f-
f-
B
A
C
I
1k
PIQ102
Q1
MMBT2222AW
GND
PIR15702
PIQ101
FPGA_1V2
2
GRN
COD10
D10
FPGA_3V3
of
1k
PIQ20
e
ap
C
COD8
D8
GRN
FPGA_1V5
PIR1601
I
3
GND
COD11
D11
GRN
ToPID102
PID1 0
w
n
R161
220R
PIR1602 COR161
VCC_5V_PROC
Q2
MMBT2222AW
GND
PIR15802
PIQ201
PIR1501
PID802
PID801
PIQ203COQ2
R155
820R
PIR1502 COR155
VCC_12V
3
182
A4
Size
Title
2k2
PIQ302
4
Sheet 64 of
Drawn By:
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
65
Simon Scott
Revision
1.0
FPGA_2V5
Q3
MMBT2222AW
GND
PIR15902
PIQ301
29/03/2011
C:\Users\..\power_leds.SchDoc
-
il
Date:
File:
RHINO
Number
Project
COR159
R159
PIR15901
Power LEDs
PROC_5V
VCC_2V5_FPGA
D9
GRN
PIR15601
PID902 COD9
PID901
PIQ30 COQ3
R156
820R
PIR15602COR156
VCC_12V
4
-
1
GND
PID10
PID10 2
PIR1601
R160
100R
PIR1602 COR160
VCC_3V3_FPGA
COR158
R158
PIR15801
ty
er
si
VCC_1V5_FPGA
ni
v
U
~II'
1r
II'
1.) Place these 5 LEDs in a line, next to the Power Good LEDs for the LDO supplies
2.) Place the name of each LED (as indicated on the schematic, next to each LED
symbol, e.g. FPGA_1V2) on the silkscreen, alongside each LED
Layout Note:
COR157
R157
PIR15701
GRN
COD7
D7
820R
COR154
R154
PIR15401
PID702
PID701
PIQ103COQ1
PIR15402
VCC_12V
2
1r
D
VCC_1V2_FPGA
1
C
B
A
D
I
f-
f-
f-
I
I
MTG_HOLE-156_P
MTG_HOLE-156_P
MTG_HOLE-156_P
PIC230 1 100n
MTG_HOLE-156_P
MTG_HOLE-156_P
I
fid12
COfid12
fid11
COfid11
Fiducial-1mm
fid10
COfid10
Fiducial-1mm
183
fid17
COfid17
fid16
COfid16
fid15
COfid15
Fiducial-1mm
fid14
COfid14
Fiducial-1mm
ffi
fid13
COfid13
Fiducial-1mm
ffi
ffi
ffi
ffi
2
ffi
Fiducial-1mm
Fiducial-1mm
ffi
Fiducial-1mm
Fiducial-1mm
fid9
COfid9
GND
3
MTG_HOLE-106_P
Date:
File:
A4
Size
Title
GND
4
Sheet 65 of
Drawn By:
Licensed under the TAPR Open
Hardware License
(www.tapr.org/OHL)
29/03/2011
C:\Users\..\mounting_holes_fids.SchDoc
RHINO
Number
Project
Mounting Holes and Fiducials
PIM170
COC253PIC26202 C262
COC254
PIC26102 C261
PIC2610 1n
PIC26201 100n
COM17
M17
GND
PIC25401 100n
-
1
Fiducial-1mm
Fiducial-1mm
Fiducial-1mm
ffi
Fiducial-1mm
MTG_HOLE-106_P
To
PIM160
COC251PIC260 2 C260
COC252
PIC25902 C259
PIC25901 1n
PIC260 1 100n
COM16
M16
GND
PIC25201 100n
PIC25301 1n
e
MTG_HOLE-106_P
PIC23601 100n
PIC25101 1n
PIM150
COM15
M15
GND
PIC23501 1n
COC235PIC25402 C254
COC236
PIC25302 C253
w
n
MTG_HOLE-106_P
PIC23401 100n
MTG_HOLE-106_P
PIM130
COC227PIC23602 C236
COC228
PIC23502 C235
COM13
M13
GND
COC233PIC25202 C252
COC234
PIC25102 C251
PIM140
COM14
M14
ap
fid8
COfid8
ffi
fid7
COfid7
ffi
fid6
COfid6
ffi
fid5
COfid5
fid4
COfid4
C
FMC_1
GND
PIC23 01 1n
MTG_HOLE-106_P
PIM1 0
COC219PIC2 802 C228
COC220
PIC2 702 C227
PIC2 701 1n
PIC2 801 100n
COM11
M11
4
-
Fiducial-1mm
Fiducial-1mm
Fiducial-1mm
Fiducial-1mm
ffi
fid3
COfid3
ffi
fid2
COfid2
GND
of
MTG_HOLE-106_P
PIM120
COC225PIC23402 C234
COC226
PIC23 02 C233
COM12
M12
GND
PIM10 0
COC217PIC2 602 C226
COC218
PIC2 502 C225
PIC2 501 1n
PIC2 601 100n
ot~II' ot~II'
fid1
COfid1
MTG_HOLE-156_P
COC239PIC25802 C258
COC250
PIC25702 C257
PIC25701 1n
PIC25801 100n
PIM80
M8
COM8
GND
ty
er
si
MTG_HOLE-156_P
PIC23 01 100n
COC231PIC250 2 C250
COC232
PIC23902 C239
PIC23901 1n
PIC250 1 100n
PIM60
COM6
M6
GND
PIC2310 1n
MTG_HOLE-106_P
ot~II' ot~II'
GND
C263 PIC26402 C264
COC256
PIC26302 COC255
1n
100n
PIC26301
PIC26401
PIM90
COM9
M9
GND
COC238
C255 PIC25602 C256
PIC25 02 COC237
PIC25 01 1n
PIC25601 100n
PIM70
M7
COM7
GND
COC230
C237 PIC23802 C238
PIC23702 COC229
PIC23701 1n
PIC23801 100n
PIM50
COM5
M5
GND
PIC2 901 1n
PIM40
COC223PIC23 02 C232
COC224
PIC23102 C231
MTG_HOLE-156_P
ni
v
PIC2 401 100n
U
COM4
M4
GND
PIC2 301 1n
COM10
M10
FMC_0
3
1.0
65
Simon Scott
Revision
I
D
PIM210
COM21
M21
PIM20 0
COM20
M20
MTG_HOLE-156_P
MTG_HOLE-156_P
MTG_HOLE-156_P
PIC2 01 100n
PIM30
COC222
PIC2 902 COC221
C229 PIC230 2 C230
COM3
M3
GND
PIC2 10 1n
MTG_HOLE-156_P
PIM20
COC215PIC2 402 C224
COC216
PIC2 302 C223
COM2
M2
ot~II' ot~II'
PIM190
COM19
M19
PIM180
COM18
M18
Tooling Holes
for Assembly
MTG_HOLE-156_P
PIM10
COC214
PIC2 102 COC209
C221 PIC2 02 C222
COM1
M1
MICRO-ATX PCB
2
ot~II' ot~II'
C
B
A
1
I
I
ffi
f-
D
C
B
A
AP P E N D I X C
L AYOUT OF THE R HINO H IDE
To
w
n
The Rhino Hide is the proposed enclosure for Rhino. It is a 1U rack-mount box that houses the Rhino PCB,
the power supply, the FMC cards and the RF cards. It also contains a front-panel PCB for power and reset
switches and status LEDs. The proposed layout for the Rhino Hide is given below, while the full specification
can be found on the attached CD.
ap
e
PROPOSED LAYOUT OF THE RHINO HIDE
AC
Kettle
Plug
FAN
C
CONNECTORS
DC
Rear
Power Power
Jack Switch
of
RHINO
ty
20mm
MEAN WELL
NES-100
100W 12VDC
POWER SUPPLY
PROCESSOR
ni
v
er
si
FPGA
FMC CARD
FMC CARD
U
Front
Panel
Conn.
Maximise
Distance
100mm
FAN
Front Panel PCB and Cutouts:
Power switch, status LEDs
FAN
FAN
Front Panel SMA
Connectors
Notes:
1.) Red blocks indicate heat sources
2.) Fan blocks indicate possible fan locations. Only 2 fans (at most) should be required.
Designer should pick the two best locations to maximise air flow over heat sources
3.) Components have been drawn to scale. However, the positions of components are not
fixed, and should be determined by designer.
184
AP P E N D I X D
L ISTING OF F ILES ON ATTACHED CD
e
Description
This document in PDF format
Gateware for 1Gbps Ethernet PHY test
Gateware for CX4 test
Gateware to flash FPGA LEDs
Gateware for DDR3 SDRAM test
Gateware to test FMC connector 0
Gateware to test FMC connector 1
Gateware for FPGA-processor bus test
Source code for the U-Boot bootloader
Source code for U-Boot standalone test apps
Source code for the X-Loader bootloader
Specification for the Rhino Hide
The Altium Designer project for the Rhino board
Installation file for the free Altium Designer Viewer
Altium PcbDoc file and Gerbers
The STEP model of the Rhino board
The X-rays for one of the Rhino prototype boards
Photographs of the Rhino board
The Rhino schematics in PDF format
ap
Sub-directories
–
rhino 1gbe test
rhino 10gbe test
rhino blinky
rhino ddr3 memtest
rhino fmc0 test 75mhz
rhino fmc1 test 75mhz
rhino proc intrfc test
u-boot
u-boot standalone apps
x-loader
–
altium rhino project
altium viewer
pcb
pcb 3d model
pcb xrays
photos
schematics
U
ni
v
rhino hide
schematics and pcb
er
si
processor software
ty
of
C
Root Directory
dissertation
fpga gateware
To
w
n
A CD has been included with this thesis, containing the PCB design files and test software. The contents of
this CD are shown below:
Further explanation is now given on how best to view these files. The gateware designs were developed in
Xilinx ISE 12, and are hence best viewed in this program. If, however, Xilinx ISE is not available, the .VHD
files in each gateware directory can be opened in a text editor.
The schematics and PCB files can be viewed in a number of different ways. The schematics are available in
PDF format, which is sufficient for most viewing purposes. The easiest method to view the PCB design file
is by using the free Altium Designer Viewer. This viewer, which has been included on the CD, must first be
installed. The Rhino51b.PcbDoc file in the /schematics and pcb/pcb directory can then be opened directly in
the Altium viewer. Alternatively, the Gerber files, which can be found in the same directory, can be opened in
a Gerber viewer program.
185
For the very interested reader, the complete Rhino PCB project can be opened in the Altium Designer Viewer.
The project file to open is /schematics and pcb/altium rhino project/rhino.PrjPCB. Note that one might need
to set the Device Sheets directory in Altium Viewer to /schematics and pcb/altium rhino project/device sheets
for this to work correctly.
The 3D model of the Rhino PCB has also been included. This 3D model is in the STEP file format, and can
be opened using a number of 3D CAD tools, such as AutoDesk Inventor, Pro Engineer and SolidWorks.
U
ni
v
er
si
ty
of
C
ap
e
To
w
n
Lastly, the X-rays for one of the PCBs can be found in the /schematics and pcb/pcb xrays directly. It is
suggested that these X-rays are viewed using the HTML document in this directory.
186
B IBLIOGRAPHY
To
w
n
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ap
e
[2] K. Asanovic et al., “The Parallel Computing Laboratory at U.C. Berkeley: A Research Agenda Based
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[4] D. A. Patterson and J. L. Hennessy, Computer Organization and Design, Fourth Edition. Morgan Kaufmann, 2009.
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U
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[19] S. Derrien and P. Quinton, “Hardware Acceleration of HMMER on FPGAs,” Journal of Signal Processing Systems, vol. 58, no. 1, pp. 53 – 67, 2010.
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U
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er
si
[41] Texas Instruments, “SLVS670H TPS65023 Datasheet,” Dec. 2009.
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U
[44] Marvell, “88E1111 Datasheet MV-S100649-00, Rev. I,” Mar. 2010.
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189
[52] D. Brooks, “Crosstalk Coupling: Single-Ended vs. Differential,” Tech. Rep. TECH6650-W, Mentor
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ty
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ap
e
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n
[58] Intel, “Intel(R) PRO Network Connections Software Version 12.1 Release Notes,” Apr.
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LAN allOS 12 1 PV Intel 141678.txt.
190